IOMMU: A Detailed view

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1 12/1/14 Security Level: Security Level: IOMMU: A Detailed view Anurup M. Sanil Kumar D. Nov, 2014 HUAWEI TECHNOLOGIES CO., LTD.

2 Contents n IOMMU Introduction n IOMMU for ARM n Use cases n Software Architecture n Summary

3 Input/Outpu t Memory Management Unit IOMMU Memory Physical Address Space IOMMU MMU Virtual Addresses /Device Addresses Physical Addresses Device Virtual Address Space CPU HUAWEI TECHNOLOGIES CO., LTD. Page 3

4 Why IOMMU? Address Translation Isolation Without IOMMU many devices are unable to address the complete address range supported by the host processor IODevices can corrupt the memory without memory isolation Device VA 1 TLB MIS S IOMMU IOTLB Translation Logic 2 3 TLB UPDA TE TLB HIT 2 or 4 Physical Memory Physical Memory Access Denied Device Physical Memory IO Device IO Page Table 3 Page Fault / Invalid Memory System Bus IOMMU System Bus IOMMU provides the unique address translation for the device address to address more than its actual capability. (This translation is independent of MMU) HUAWEI TECHNOLOGIES CO., LTD. Page 4 IOMMU provides memory protection and enables secure memory access

5 IOMMU: Pros and Cons Pros Large Memory Allocation; No need to be physically contiguous Devices can access physical memory addresses higher than 4GB (non-dac devices as well) Can be programmed to make the memory region appear to be contiguous to the device on the bus. Device Isolation (avoid DMA attacks) Cons Degradation of performance from translation and management overhead (can be mitigated by a TLB) Consumption of physical memory for the added I/O page (translation) tables. This can be mitigated if the tables can be shared with the processor. Peripheral memory paging can be supported by an IOMMU. (PCIe Address Translation Services (ATS) Page Request Interface (PRI) extension can detect and signal the need for memory manager services.) Interrupt remapping. HUAWEI TECHNOLOGIES CO., LTD. Page 5

6 Contents n IOMMU Introduction n IOMMU for ARM n Use cases n Software Architecture n Summary HUAWEI TECHNOLOGIES CO., LTD. Page 6

7 IOMMU in ARM IOMMU in ARM is named as System Memory Management Unit (SMMU) Supports Address translation and isolation Two stage transaltion to support Virtualization Stage 1, from VA (Virtual address) to IPA (Intermediate Physical Address) Stage 2, from IPA to PA (Physical Address) hypervisor will define translation tables to perform this. ARM releases SMMU specifications to support the implementations Currently SMMUv2 is the latest official release The mainline Linux kernel has the SMMUv2 driver implemented This driver currently supports (drivers/iommu/arm_smmu.c) SMMUv1 and v2 implementations Stream-matching and stream-indexing v7/v8 long-descriptor format Non-secure access to the SMMU 4k and 64k pages, with contiguous pte hints Up to 42-bit addressing (dependent on VA_BITS) Context fault reporting Memory Physical Address Space SMMU Device Virtual Address Space MMU CPU HUAWEI TECHNOLOGIES CO., LTD. Page 7

8 Contents n IOMMU Introduction n IOMMU for ARM n Use cases n Software Architecture n Summary HUAWEI TECHNOLOGIES CO., LTD. Page 8

9 Use cases CPU address space I/O address space Physical Memory System Bus DMA CPU copies from bounce buffer to destination DMA CPU address space Access Denied SMMU SMMU Device DMA 4GB Guest OSn 0 4GB Guest OS1 X1 Xn An 0 A1 Virtual Address space Virtualization n Enables devices to address more than its addressing capability without DAC or bounce buffers n Two stage address translation helps to manage virtual devices along with isolation Stage 1 Stage 1 4GB Physical Address space n Memory protection helps in DMA and Virtualization use cases n Scatter gather DMA capabilities n High performance user space drivers Xn X1 0 Under Guest OS control 4GB An A1 0 Intermediate Physical Address space Stage 2 4GB 0 X1 An Xn A1 HUAWEI TECHNOLOGIES CO., LTD. Page 9

10 Contents n IOMMU Introduction n IOMMU for ARM n Use cases n Software Architecture n Summary HUAWEI TECHNOLOGIES CO., LTD. Page 10

11 Software Architecture Device/User 1 Device/User n Clients that uses the iommu DMA Mapping /arch/arm/mm Attaches clients to use iommu awared dma ops (dma-mappings.c) IOMMU Main Driver (/drivers/iommu/*) Almost all the features of IOMMU are abstracted at this layer (iommu.c, arm-smmu.c ) ARM SMMU(IOMMU) HW Support Support IOMMU support on Hardware HUAWEI TECHNOLOGIES CO., LTD. Page 11

12 Code Flow: DMA API to IOMMU dma-mapping.c iommu.c arm_smmu.c Device driver dma-mapping.c (arch\arm\mm) DMA Mapping /arch/<arch>/mm IOMMU Main Driver (/drivers/iommu/*) IOMMU HW Support iommu.c HUAWEI TECHNOLOGIES CO., LTD. Page 12

13 Code Flow: IOMMU to Specific IOMMU Drive r iommu.c Device driver DMA Mapping /arch/<arch>/mm arm_smmu.c IOMMU Main Driver (/drivers/iommu/*) IOMMU HW Support HUAWEI TECHNOLOGIES CO., LTD. Page 13

14 Contents n IOMMU Introduction n IOMMU for ARM n Use cases n Software Architecture n Summary HUAWEI TECHNOLOGIES CO., LTD. Page 14

15 Summary ARM SMMU is getting refined and new versions with more features expected In Linux Kernel, iommu developments are active, especially for ARM SMMU New drivers and features (PCIe/ATS, VFIO ) Focus on Virtualization Support and extensions Performance optimizations HUAWEI TECHNOLOGIES CO., LTD. Page 15

16 IOMMU Mailing List HUAWEI TECHNOLOGIES CO., LTD. Page 16

17 Thank you

18 Reference - IOMMU information - ARM SMMU v2 specification Linux kernel mainline source code 3.17 HUAWEI TECHNOLOGIES CO., LTD. Page 18

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