Main Memory. Memories. Hauptspeicher. SIMM: single inline memory module 72 Pins. DIMM: dual inline memory module 168 Pins

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1 23 Memories Main Memory 2 Hauptspeicher SIMM: single inline memory module 72 Pins DIMM: dual inline memory module 68 Pins / Statische RAMs schnell aber teuer / Dynamische RAMs höhere Integration möglich 3 4

2 Speicherzyklus " Speicher-Bänke Dynamische RAMs (DRAM): Speicherinhalt muß regelmäßig aufgefrischt werden. Speicherzelle adressieren Zykluszeit CPU Bus C P U C a c h e Datum auslesen/laden DRAM: Speicher erholen Memory. M e m o r y b a n k B u s M e m o r y M e m o r y b a n k b a n k 2 M e m o r y b a n k 3 Zugriffszeit Speicher-Verschränkung 5 6 Interleaving Speicher-Referenz-Lokalität Speicherzugriffe erfolgen in den überwiegenden Fällen auf sukzessive Adressen. zeitlich aufeinander folgende Zugriffe beziehen sich dann auf verschiedene Modeln. Kein Zugriffskonflikt entsteht. Adressraum Speichermodule 7 8

3 Verschränkte Speicherzyklen Modul verborgen Modul2 Adressieren Lesen/Schreiben Adressieren Erholen Lesen/Schreiben Erholen " Die Organisation des Gesamtspeichers : Hierarchie von Speicherebenen " Diese enthält Speicher unterschiedlicher Größe und unterschiedlicher Zugriffsgeschwindigkeit Virtueller Speicher Register s Hauptspeicher Virtueller Speicher Massenspeicher Speicherverwaltung notwendig 9 Virtueller Speicher Virtual Memory Der Hauptspeicher kann als für den Sekundärspeicher dienen. Vorteile: Illusion eines großen Physikalischen Speichers Programm- Relokation Speicherschutz 2

4 Paging:Seitenverwaltung des Virtuellen Speichers Page Tables Virtual page number Page table Physical page or Valid disk address Physical memory Disk storage Pages: virtual memory blocks Page faults: the data is not in memory, retrieve it from disk huge miss penalty, thus pages should be fairly large (e.g., 4KB) reducing page faults is important (LRU is worth the price) can handle the faults in software instead of hardware using write-through is too expensive so we use writeback Virtual page number Translation Physical page number Virtual address Page offset Page offset Physical address 4 Page Tables What if the data is on disk? Pa ge table register Virtual address Virtual page number Page off set Valid 2 2 Physica l pa ge num ber Load the page off the disk into a free block of memory, using a DMA transfer. Meantime switch to some other process waiting to be run. Page table When the DMA is complete, get an interrupt and update the process's page table If then pag e is no t present in me mory So when switched back to the task, the desired data will be in memory Physica l pa ge num ber Page off set Physical add ress 5 6

5 Virtual Memory vrs. Virtual memory terms compared to cache terms: block --- Page or segment Miss --- Page fault or address fault How is virtual memory different from caches? What Controls Replacement: HW for cache misses, operating system for page faults Size of processor address determines the size of virtual memory, cache size is independent of the processor address size secondary storage used as swap space and for storing file system Typical Parameter Ranges for Virtual Memory and " Parameter First-level cache VM " block (page) size 6-28 bytes 4 K- 64 Kbytes " hit time -2 cycles 4- cycles " miss penalty 8- cycles 7-6 cycles " miss rate.5-%.-.% " data memory size 8 K-64 K 6 MB-8 GB 7 8 Virtual Memory Four questions for VM? Q: Where can a block be placed in the main memory? Anywhere because of the exorbitant miss penalty Q2: Which block should be replaced on a miss? LRU (needs use bits) Q3: What happens on a write? Write Back (write through to secondary storage is not feasible) Virtual Memory Problem Page Table too big! 4GB Virtual Memory 4 KB page ~ million Page Table Entries 4 MB just for Page Table Q4: How is a block found if it is in the upper level? Page table: can be large Inverted page table: hashing virtual address (p.t. only size of physical memory) reduce address translation time by a translation look-aside buffer TLB 9 2

6 Physical Memory 2-Level Page Table 2nd Level Page Tables... Super Page Table Virtual Memory Stack Heap Static Code Program operates in its virtual address space Virtual to Physical Address Translation virtual address (inst. fetch load, store) Each program operates in its own virtual address space Each is protected from the other HW mapping physical OS can decide where each goes in memory address (inst. fetch load, store) Hardware (MMU) provides virtual -> physical mapping Physical memory (incl. caches) 2 22 MMU Memory Management Unit: Speicher-Verwaltungseinheit Adressen Adressen virtuell MMU physical. CPU Hauptspeicher Technique for Fast Address Translation: Translation Lookaside Buffer TLB Small (32-28 entries) cache of recently translated page addresses often fully associative TLB entry: tag holds portion of virtual address, data portion holds a physical page frame number, protection field valid bit, usually a use bit and dirty bit Ausnahme process tag? ==> tagged TLB 23 24

7 Beschleunigung der Adreßumsetzung für Adreß- Translationen : Translation Lookaside Buffer: TLB Typical TLB Format Virtual Physical Dirty Ref Valid Access Address Address Bit Rights Virtual page number Valid Tag TLB Physical page address Physical memory TLB just a cache on the page table mappings Page table Physical page Valid or disk address TLB access time comparable to cache Disk storage (much less than main memory access time) Ref: Used to help calculate LRU on replacement Dirty Bit: since use write back, need to know whether or not to write page to disk when replaced What if TLB - Miss? Addressing Option : Hardware checks page table and loads new CPU CPU CPU A Page Table Entry into TLB - evicting an old entry from the TLB Option 2: Hardware traps to OS, up to OS to decide what to do TLB VA PA PA VA Tag s TLB VA VA PA PA Tag s VA L2 MEM TB PA MEM MEM Example:MIPS follows Option 2: Hardware knows nothing about page table format 27 Conventional Physical Organization Virtually Addressed Translate only on miss Synonym Problem Overlap access with VA translation: requires cache index to remain invariant across translation 28

8 TLB and Physical Real or Physical V ir t u a l a d d r e s s T L B a c c es s no Y e s T L B m i s s e x c ep ti o n T L B h i t? P h y s i c al ad d r e s s No W r i t e? Y e s T r y t o r e a d d at a f r o m c a c h e N o W r it e a c c es s Y es b it o n? C a c h e m I s s s s s ta l l No C ac h e h i t? Y e s W r i t e p r ot e c t i o n e x c e pt i o n W r it e d at a in t o c a c h e, u p d a t e t h e t a g, a n d p ut t h e d at a a n d t h e a d d r e s s i n t o t h e w r it e b u ff e r D el i v e r d a t a 29 3 t o t h e C P U Memory Stage: Physical Memory Stage: Virtual Only cache misses access TLB Index is part of the displacement 3 32

9 " Very complicated memory systems: Characteristic Intel Pentium Pro PowerPC 64 Virtual address 32 bits 52 bits Physical address 32 bits 32 bits Page size 4 KB, 4 MB 4 KB, selectable, and 256 MB TLB organization A TLB for instructions and a TLB for data A TLB for instructions and a TLB for data Both four-way set associative Both two-way set associative Pseudo-LRU replacement LRU replacement Instruction TLB: 32 entries Instruction TLB: 28 entries Data TLB: 64 entries Data TLB: 28 entries TLB misses handled in hardware TLB misses handled in hardware Conclusion Apply Principle of Locality Recursively Reduce Miss Penalty? add a (L2) cache Manage memory to disk? Treat as cache - Use Page Table of mappings vs. tag/data in cache Virtual memory to Physical Memory Translation too slow? Add a cache of Virtual to Physical Address Translations, called a TLB Characteristic Intel Pentium Pro PowerPC 64 organization Split instruction and data caches Split intruction and data caches size 8 KB each for instructions/data 6 KB each for instructions/data associativity Four-way set associative Four-way set associative Replacement Approximated LRU replacement LRU replacement Block size 32 bytes 32 bytes Write policy Write-back Write-back or write-through Conclusion Multiprocessors Virtual Memory allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound. Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well. TLB to reduce performance cost of VM Need more compact representation to reduce memory size cost of simple -level page table (especially bit address) 35 36

10 s are Critical for Performance s and Coherence Reduce average latencey Reduce average bandwidth s play key role in all cases Reduce average data access time Reduce bandwidth demands placed on shared interconnect " Many processor can shared data efficiently " What happens when store & load are executed on different processors? P P P 37 private processor caches create a problem Copies of a variable can be present in multiple caches A write by one processor may not become visible to others» They ll keep accessing stale value in their caches => coherence problem What do we do about it? Organize the mem hierarchy to make it go away Detect and take actions to eliminate the problem 38 Snooping s Contention for Tags " controller must monitor bus and processor Can view as two controllers: bus-side, and processor-side With single-level cache: dual tags (not data) or dual-ported tag RAM " must reconcile when updated, but usually only looked up Respond to bus transactions Tags used by the processor Tags d Data Tags 39 Tags used by the bus snooper 4

11 Snoopy -Coherence Protocols MESI State Address Data P $ Bus snoop Pn $ Mem I/O devices -memory transaction " Bus is a broadcast medium & s know what they have " Controller snoops all transactions on the shared bus relevant transaction if for a block it contains take action to ensure coherence " invalidate, update, or supply value depends on state of the block and the protocol 4 42 Reporting Snoop Results: " MESI protocol, need to know Is block dirty; i.e. should memory respond or not? Is block shared; i.e. transition to E or S state on read miss? " Three wired-or signals Shared: asserted if any cache has a copy Dirty: asserted if some cache has a dirty copy " needn t know which, since it will do what s necessary Snoop-valid: asserted when OK to check other two signals " actually inhibit until OK to check Design Choices Controller updates state of blocks in response to processor and snoop events and generates bus transactions Snoopy protocol set of states state-transition diagram actions Basic Choices Write-through vs Write-back Invalidate vs. Update Snoop Processor Ld/St Controller State Tag Data 43 44

12 Basic Design Multilevel Hierarchies P P P P L L L Ad dr Cm d Bussid e controller Tags a nd state fo r snoo p Comp arato r Tag To co ntro ller d ata RA M Write-b ack b uffer Data Tags and state for P Processorside co ntroller " Independent snoop hardware for each level? processor pins for shared bus L2 contention for processor cache access? " Snoop only at L2 and propagate relevant transactions L2 L2 Snoop stat e Ad dr Comp arato r Cmd To cont rolle r System bu s Data buffer A ddr Cmd 45 " Inclusion property () contents L is a subset of L2 (2) any block in modified state in L is in modified state in L2 => all transactions relevant to L are relevant to L2 2 => on BusRd L2 can wave off memory access and inform L 46 Shared Disadvantages placement identical to single cache only one copy of any cached block fine-grain sharing Potential for positive interference one processor prefetches data for another Smaller total storage only one copy of code/data used by both processors. P Switch (Interleaved) (Interleaved) Main Memory Pn Fundamental bandwidth limitation Increases latency of all accesses X-bar Larger cache hit time determines processor cycle time!!! Potential for negative interference one processor flushes data needed by another P Switch (Interleaved) (Interleaved) Main Memory Pn Can share data within a line without ping-pong 47 48