& Data Processing 2. Exercise 3: Memory Management. Dipl.-Ing. Bogdan Marin. Universität Duisburg-Essen

Transcription

1 Folie a: Name & Data Processing 2 3: Memory Management Dipl.-Ing. Bogdan Marin Fakultät für Ingenieurwissenschaften Abteilung Elektro-und Informationstechnik -Technische Informatik-

2 Objectives Memory Management Virtual Memory Concepts Paging and Segmentation

3 Memory Management Data Structures How does OS keep track of unused and used blocks? Bit Maps Memory divided into small allocation units (say 4 bytes) Special bit map, one bit assigned for each unit bit per 4 bytes (32 bits) bit map occupies (wastes?) /33 of total memory Each bit provides the status of the corresponding memory unit if unit is free ; if unit is used Simple data structure to maintain but expensive to use for memory allocation E.g. 4 free bytes are needed search for a run of consecutive s in map! Linked Lists Dynamic data structure with an entry for each memory block P for used partition, H for unused block Start address of partition, Length of partition Pointer to next entry Need to detect and merge adjacent H entries into a single H entry expensive Best-fit placement requires examining the complete list whereas first-fit only requires finding the first H entry which is big enough first-fit much quicker Alternative is to keep list sorted in increasing/decreasing partition length expensive

4 Memory Management Data Structures Fig. Memory Structure a. Memory structure b. Bit map c. Linked list Fig. Linked list combinations mergingfor (a) requires changing entry 2 from P to H (b) requires merging entries 2 and 3 into a single H ( list is one entry shorter) (c) requires merging entries and 2 into a single H (list is one entry shorter) (d) requires merging entries,2 and 3 into a single H (list is two entries shorter)

5 Memory Allocation The following methods applies for variable partitioning of memory space. Best fit : allocate smallest hole that fit Worst fit : allocate the largest hole First fit : allocate the first hole that fit from the beginning Next fit : allocate the first hole that fit since last operation

6 Memory Allocation:. Consider a swaping system in which memory consists of the following hole sizes in memory order: H H H2 H3 H4 H5 H6 H7 K 4KB 2KB 8KB 7KB 9KB 2KB 5KB Which hole is taken for a succesive segment request of a) 2 KB b) KB c) 9KB for first fit? Repeat the questions for best fit, worst fit and next fit. First Fit (first hole that fit) a) H2 b) H c) H3 Best Fit (smalest hole that fit) a) H6 b) H c) H5 Worst Fit (largest hole) a) H2 b) H3 c) H7 Next Fit (first hole that fit since last op) a) H2 b) H3 c) H5

7 Memory Allocation: 2. Explain how the following algorithms work in allocating memory:. First fit. 2. Best fit. 3. Worst fit. Given free memory blocks of K, 5K, 2K, 3K and 6K (in this order on a linked list), how would each of the above algorithms place requests for 22K, 47K, 2K and 426K (requested in that order)? Which algorithm makes best use of memory? Initially: Memory Allocation: Conclusion: Best Fit uses memory best

8 Buddy System () Memory blocks are available in size of 2 k where S <= k <= L, and 2 S : Smallest size of block that can be allocated 2 L : Largest size of block that can be allocated : Given a memory consisting of a single continous piece of 64 pages, allocate space for a 8-page request. Allocate another 8 page request. Allocate 4 page request. Release the allocated space for the second 8- page request. Release the allocated space for the first 8-page request. 64

9 Buddy System (2) 64 Too big, divide the 64-page chunk into half Too big, divide a 32-page chunk into half Too big, divide a 6-page chunk into half Just right! 8-page chunk fits in

10 Buddy System (3) Request for another 8-page chunk Just right! Second 8-page chunk fits in Qn : Allocate space for a 4-page request 6-page chunk is too big, half it page buddy is still too big each, half it again Just right! 4-page request fits in

11 Buddy System (4) Release space for the second 8-page request page chunk released Qn : Release space for the first 8-page request After the second 8-page chunk released Two 8-page chunk buddy merge to get 6-page chunk back Only buddies can merge!

12 Virtual Memory (VM) concepts: Paging Physical Address (PA) the address seen by the physical memory address range limited by the amount of physical memory that is available 4MB RAM 22-bit physical address address range divided into small uniform chunks called page frames typically 4K to 32K Virtual Address (VA) the address used by the process address range limited by the CPU address range 32-bit CPU 32-bit virtual address 4 GB of virtual memory address range divided into small uniform chunks called pages page size must be the same as the page frame size VA to PA mapping Process memory consists of a collection of contiguous pages which map to possibly non-contiguous page frames Process making a VA reference must be mapped to a PA reference Paging not swapping Instead of swapping whole process to disk, process pages are paged to disk

13 VA to MA mapping: Page Tables VA = [ p d ] and PA = [ f d ] PA = f-bit frame number + d-bit offset 2 f+d bit PA VA = p-bit page table index + d-bit page offset 2 p+d bit VA Usually p >> f since VA range >> PA range p-bits used to retrieve corresponding f-bit frame from per process page table One page table per process Address of page table entry = Page Table Ptr. + p 2 p entries in page table Typical page table entry: [P M R rwx access f-bit frame number] P = -bit Present bit ( if page in memory, if page not in memory) M = -bit Modified bit ( if page has been modified ( dirty ), if not) R = -bit Referenced bit ( if page has been referenced recently, if not) If P = page not in memory (on swap disk) page fault OS enters page fault handling routine is there a free page? If not page out a page according to page replacement strategy (R and M bits used to determine best page to evict R= and M= is a good candidate) read in required page from swap disk (page in) and modify page table accordingly restart instruction

14 VA to PA address translation system Address translation in a paging system

15 VA to PA example VA = [page address offset ] VA = [p d] = [8 2] 2 8 = 256 virtual pages P (present bit) M (modification bit) VA No. of virtual page 2 P M... If P= : Hit = Read If P=: take available page with M= and overwrite with reloaded page If A= and all available pages show M= ) Take content of a page in main memory and restore secondary page 2) Reload page from second memory into free page No. of physical page PA...

16 VA to PA (/2) A computer with a 6 bit address, a 4KB page size, has 64K of VA and 32K of PA. The page table for this computer is given in the following figure. Assuming that at a given time the running process issues the following instruction: MOV REG, 896 Which will be the outcome of the Memory Management Unit mapping? Page table Present bit

17 VA to PA (2/2) VA =[ p d ] and PA =[f d ] 4K pages d=2 (since 2 2 =496) 64K of VA p+d=6 (since 2 6 =65536) p=4 32K of PA f+d=5 (since 2 5 =32768) f=3 since 2 p =2 4 =6 6 entry page table is needed, where each entry = [3 bit frame address P ] Process issues instruction MOV REG, 896 VA= 896 VA= [p= d= ] p=2 entry 2 from page table is refered Entry 2 has P= and f= PA = [f= d= ] = 2458 MMU mapping produces: MOV REG, 2458

18 Multi-level Page Tables Situation: Process is assumed to have access to complete VA range Page table is too big! e.g. 32-bit CPU and 4K pages p = = million entry page table entries at least byte MB per page table per process! Multi-level Page Tables 2-level page tables VA = [ p q d ] and PA = [ f d ] p-bits to index top-level page table returns pointer to 2 nd -level page table q-bits to index 2 nd -level page table returns f-bit page frame 2 p entries in top-level page table each entry spans 2 q+d of VA memory top-level page table entry: [ Pointer to 2 nd -level page table ] 2 q entries in 2 nd -level page table each entry spans 2 d of VA memory ( page) 2 nd -level page table entry: [P M R f-bit frame number] there are 2 p x (2 nd -level page tables)! BUT not all of these are needed Adv.: Only keep those lower-level page tables that are needed Disadv.: n-level page tables require n memory references to perform translation!

19 Multi-level Page Tables 2 Level Page Table p=, q=, d=2 (VA=[ p q d ])

20 Multi-level Page Tables A computer with 32 bit address uses a 2 level page table. Virtual addresses are split into 9-bit top level page table field and -bit second level page field, and an offset. How large are the pages and how many are there in the address space? VA = [ p q d ] and PA = [ f d ] 9-bit top level page table field p=9 -bit second level page field q= 32 bit address p+q+d=32 d= 32 p q = 32 9 =2 Page is 2 d = 2 2 = 4K page Number of bits for the virtual page is: p + q = 2 Number of virtual pages is 2 2

21 Pure Segmentation SA = [ s d ] and PA = [ Base + d ] s-bit used to reference entry in segment table 2s entries in segment table; Segment table entry = [ length base ] Length (limit): specifies the maximum size of the segment Base: start address of segment in main memory If (d > length) then segmentation fault else PA = (Base + d) Address translation in a segmentation system

22 Segmentation with Paging Segmentation with Paging the best of both worlds Segment table contains pointer to page table for data within segment Length of segment must be in integer number of pages No need for length specification use page fault mechanism

23 Fragmentation Analysis (holes are represented by empty boxes) Definitions: m = bytes of the total memory s= average size of segments ks (k>=) average size of holes f= % of total of memory unused = (ammount of memory used by unused segments)/(total memory) 5% Rule (Knuth) n= numebr of segments h= number of holes h=n/2 (on average if there are n segments we expect (n/2) holes) Analysis of the free space: Conclusions: If the holes are half size of segments (k=.5) f = 2% If holes are quarter size (k=.25) f=% Smaller hole sizes more efficient memory utilisation

24 Page Replacement Policy

25 Page Replacement Policy: LRU

26 Page Replacement Structures

27 Second-Chance FIFO Policy

28 Clock Policy

29 NRU and NFU Policy

30 Page Replacement Policy: A computer has four page frames. The time of loading, time of last access and the R and M bits for each page are as shown bellow (the times are in clock ticks): Page Loaded Last Ref. R M a) Which page will NRU replace? b) Which page will FIFO replace? c) Which page will LRU replace? d) Which page will Second Chance replace? a) R=, M= (class = best page to be replaced by NRU) in above table page 2 will be replaced by NRU b) FIFO (First In First Out) in above table page 3 will be replaced by FIFO c) LRU replaces the page with the oldest last access record in above table page will be replaced by LRU d) Second Chance: check the tail of the queue (oldest page) if R= then reset R and move page to head of queue otherwise remove page page 3 has R=, algorithm resets the R bit and moves page 3 at the head of the list and search again the new tail of the list. Page 2 is the new tail of the list, R= therefore page 2 will be replaced by Second Chance

31 Next Week: Cache.. Check the webpage for exercises! EXAM: Tu. 25/7/26 LD Sporthalle 3.3