ATI 215PADAKA12FG Graphics Processor extracted from ATI Radeon X1950 Pro Graphics Card

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Henry Dennis
7 years ago
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1 ATI 215PADAKA12FG Graphics Processor extracted from ATI Radeon X195 Pro Graphics Card Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 5, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 2 Device Overview 2.1 Package and Die Overview 2.2 Die Features 2.3 Selected Package Analysis 3 Process 3.1 General Structure 3.2 Passivation and Dielectrics 3.3 Metallization 3.4 Vias and Contacts 3.5 Logic and I/O Transistors, and STI 3.6 Isolation 3.7 Wells 4 SRAM Cell Analysis 4.1 SRAM Cell Overview and Schematics 4.2 8T SRAM Plan View Analysis 4.3 8T SRAM Cross-Sectional Analyses (Parallel to Bitlines) 4.4 6T SRAM Plan View Analysis 4.5 6T SRAM Cross Sectional Analyses 5 Materials Analysis 5.1 Materials Analysis Overview 5.2 SEM-EDS Analysis 5.3 TEM-EDS Analysis of the Dielectrics 5.4 TEM-EDS Analysis of the Metals 5.5 TEM-EDS Analysis of Transistors

3 Structural Analysis 6 Critical Dimensions 6.1 Package and Die 6.2 Dielectrics, Metals and Vias 6.3 Logic Transistors, Polysilicon, and STI 6.4 SRAM 7 Statement of Measurement Uncertainty and Scope Variation 8 References Report Evaluation

4 Overview Overview 1.1 List of Figures 2 Device Overview Package Top Package Bottom Package X-Ray Die Photograph Die Markings Die Photograph Backside Polysilicon Die Corner A Die Corner B Die Corner C Die Corner D Hexagonal Pad Arrangement Square Pad Arrangement Pad Under Bump Metallization Standard Logic Layout at Polysilicon Standard Logic Cell at Polysilicon Dummy Gates in Logic Layout at Polysilicon Gate Array at Polysilicon Dummy Polysilicon Array Separating Circuit Blocks Silicon Die and Fiberglass Substrate Solder Bump Overview Solder Bump/Die Interface Solder Bump/Package Land Interface Package Ball 3 Process General Die Structure Die Edge Die Seal Passivation FESEM ILD 7 FESEM ILD 7 TEM ILD 6 TEM ILD 5 TEM ILD 4 TEM ILD 3 TEM ILD 2 TEM ILD 1 TEM PMD FESEM PMD TEM STI Under Polysilicon and Gates FESEM

5 Overview Minimum Pitch Metal Metal 7 to Metal 1 and ILD Stack Minimum Pitch Metal 7 FESEM Metal 7 TEM Minimum Pitch Metal 6 FESEM Metal 6 TEM Metal 6 Liner TEM Minimum Pitch Metal 5 FESEM Metal 5 TEM Minimum Pitch Metal Metal 4 TEM Minimum Pitch Metal Metal 3 TEM Minimum Pitch Metal Metal 2 TEM Minimum Pitch Metal 1 FESEM Metal 1 TEM Minimum Pitch Via Minimum Pitch Via 6 and Minimum Pitch Via 4 and 3 FESEM Via 4 TEM Via 3 TEM Minimum Pitch Via 2 and Via 1 TEM Contact to Poly TEM Contact to S/D TEM Contact to S/D, Top TEM Contact to S/D, Bottom TEM Contacts to Polysilicon TEM Butted Contact in 6T SRAM General View of Logic MOS Transistors and Minimum Width STI FESEM Logic Transistor Gate (Length) TEM T SRAM NMOS Transistor Gate (Length) TEM T SRAM PMOS Transistor Gate (Length) TEM Transistor Gate (Width) TEM Logic Transistor Gate Dielectric NMOS Gates at Silicon Delineation PMOS Gates at Silicon Delineation I/O Transistor Gate TEM I/O Transistor Gate Dielectric TEM Minimum Width STI Logic Area P-Well and N-Well SCM Logic Area P-Well Profile SIMS Logic Area N-Well Profile SIMS SRAM Area P-Well Profile SIMS SRAM Area N-Well Profile SIMS

6 Overview SRAM Cell Analysis Dual Port 8T SRAM Cell Schematic T SRAM Cell Schematic T SRAM at Metal T SRAM at Metal T SRAM at Metal T SRAM at Polysilicon T SRAM at Silicon NMOS Pull Down Transistors TEM NMOS Access Transistors TEM PMOS Pull Up Transistors TEM T SRAM at Polysilicon T SRAM at Silicon T SRAM at Metal T SRAM at Metal T SRAM at Metal NMOS Pull Down and Access Transistors FESEM PMOS Pull Up Transistors FESEM 5 Materials Analysis SEM-EDS Spectrum of UBM SEM-EDS Spectrum of UBM SEM-EDS Spectrum of UBM SEM-EDS Analysis of Solder Bump SEM-EDS Analysis of Package Land Plating (Top) SEM-EDS Analysis of Package Land TEM-EDS Spectrum of Passivation 1, 3, and TEM-EDS Spectrum of Passivation 2 and TEM-EDS Spectrum of ILD TEM-EDS Spectrum of ILD TEM-EDS Spectrum of ILD 7-2 and ILD TEM-EDS Spectrum of ILD TEM-EDS Spectrum of ILD TEM-EDS Spectrum of ILD TEM-EDS Spectrum of PMD 2 and PMD TEM-EDS Spectrum of PMD TEM-EDS Spectrum of PMD TEM-EDS Spectrum of STI TEM-EDS Spectrum of Metal 1 Liner TEM-EDS Spectrum of Gate Silicide TEM-EDS Spectrum of MOS S/D Silicide

7 Overview List of Tables 1 Overview Device Identification PADAKA12FG Device Summary PATAKA12FG Process Summary 2 Device Overview Package and Die Critical Dimensions 3 Process Measured Dielectric Thicknesses Measured Metal Line Thicknesses Minimum Observed Metal Line Horizontal Dimensions Minimum Observed Via and Contact Pitch Transistor Horizontal Dimensions Transistor Vertical Dimensions 4 SRAM Cell Analysis T SRAM Cell and Transistor Dimensions T SRAM Cell and Transistor Dimensions 6 Critical Dimensions Package and Die Critical Dimensions Measured Dielectric Thicknesses Measured Metal Line Thicknesses Minimum Observed Metal Line Horizontal Dimensions Minimum Observed Via and Contact Pitch Transistor Horizontal Dimensions Transistor Vertical Dimensions T SRAM Cell and Transistor Dimensions T SRAM Cell and Transistor Dimensions

8 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 5 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

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