Tan, Yung Sern; Yeo, Kiat Seng; Boon, Chirn Chye; Do, Manh Anh. Tan, Y. S., Yeo, K. S., Boon, C. C., & Do, M. A. (2011).

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1 Title esign o a hysteresis requency lock detector or dualloops clock and data recovery circuit Authors itation Tan, Yung Sern; Yeo, Kiat Seng; Boon, hirn hye; o, Manh Anh Tan, Y. S., Yeo, K. S., Boon,.., & o, M. A esign o a hysteresis requency lock detector or dualloops clock and data recovery circuit. 011 IEEE International onerence o Electron evices and Solid- State ircuits, pp.1-. ate 011 UL ights 011 IEEE. Personal use o this material is permitted. Permission rom IEEE must be obtained or all other uses, in any current or uture media, including reprinting/republishing this material or advertising or promotional purposes, creating new collective works, or resale or redistribution to servers or lists, or reuse o any copyrighted component o this work in other works. The published version is available at: [

2 esign o a hysteresis lock detector or dual-loops clock and data recovery circuit Yung Sern TAN, Kiat Seng YEO, Senior Member, IEEE, hirn hye BOON, and Manh Anh O, Senior Member, IEEE VITUS, an I esign entre o Excellence at the School o Electrical and Electronic Engineering, Nanyang Technological University, Singapore tany016@ntu.edu.sg Abstract In dual-loops clock and data recovery circuit design, lock detector is crucial in controlling the switching within loop. The setting o the requency accuracy o lock detector is a tough task as large ppm will leads to a longer lock time or phase tracking loop and small ppm will leads to more switching time between the loops. A novel lock detector with hysteresis property is proposed in this paper. It provides two dierent ppms in both dierent conditions; a smaller ppm or in-lock condition and a larger ppm or out-o-lock condition. This paper also provides a detailed analysis o the proposed lock detector at dierent conditions. The proposed lock detector is simulated in um technology and it consumes 1.1-mW at a 1.8V supply voltage. Index Terms dual-loops clock and data recovery circuit, requency lock detector, hysteresis property. I. INTOUTION As the demand or data communication has increased exponentially in the past decade, optical iber has become one o the critical mediums in communication system. ue to the importance o clock and data recovery circuit in optical communication system [1], researchers have introduced dierent types o architecture []. In order to achieve a aster locking time, dual-loops architectures were explored [3, 4]. Fig. 1 shows the block diagram o a dual-loops architecture [5]. The architecture is ormed by two main loops: a requency tracking loop and a phase tracking loop. The lock detector L [6] in this architecture acts as a vital role to control the switching between the loops. At the starting, as the requency o voltage control oscillator VO is urther away rom the operating requency, the L will enable the requency tracking loop. The requency tracking loop will track the VO requency so that its requency is within a certain ppm o the required operating requency. The L will then switch the loop to phase tracking loop when VO requency meets the required ppm. The loop will then continue to track the requency and phase o the VO and provides a recovered clock. The L will only switch the loop back to requency in F EF Fig. 1. P L PF etime ata P P F IV LPF VO Block diagram o a dual-loops architecture. tracking loop when the VO requency is being interrupted and is out o the required ppm. Through this architecture, the is able to track its requency with a shorter time. The locking range o the is also expanded through the additional requency tracking loop. One o the problems in the conventional L architecture is that there is only one required ppm to switch between requency tracking loop and phase tracking loop [7]. The setting o the required ppm has been a challenging task or the designer. When the required ppm is set to be small, the requency tracking loop will track the VO requency to a closer operating requency which helps to shorten the lock time o the. However, during the phase tracking loop, the VO requency may be out o the required ppm i it is set to be too small. Instead o having a shorter lock time, the will then take a longer time to lock as more switching activity occurs between both requency tracking loop and phase tracking loop. However, i the required ppm is set to be large, the phase tracking loop will have a longer lock time as the VO requency is urther away rom the operating requency. In order to circumvent this diiculty, a novel lock detector with hysteresis property is proposed in this paper. Section II describes the architecture o the proposed L and section III shows the calculation and analysis o the proposed L. Section IV provides simulation results and discussion while section V summarizes the paper. /N Phase Tracking Loop Tracking Loop F VO

3 II. AHITETUE OF THE POPOSE LOK ETETO In order to circumvent the problem o having only one required ppm, the hysteresis property o the proposed L provides two dierent required ppms or two dierent conditions. uring the requency tracking loop, the required ppm is preerred to be small so that the lock time o the can be decreased. Vice versa, the required ppm is preerred to be larger when the is in the phase tracking loop which prevents the loop rom switching back to requency tracking loop while the is recovering the clock. Through these conditions, the hysteresis property o L will have smaller required ppm to switch the loop rom requency tracking loop to phase tracking loop in-lock condition and vice versa or a larger required ppm to switch the loop rom phase tracking loop to requency tracking loop out-o-lock condition. Fig. shows the block diagram o the proposed L architecture. It is basically composed o N-bits counters, three -lip-lops FF, and a ew decision logic circuits. The main purpose o the counter is to count the cycle number o the reerence clock F EF and the VO clock ater the divider F IV respectively. The pass-transistor logic ater the counter is to control the hysteresis property o the L circuit. The decision logic circuit at the bottom o Fig. helps to decide whether the requency is lock or not. The main concept o the proposed L architecture is that during the in-lock condition, both N-bit counters o F EF and F IV will begin to start counting the number o cycles o each clock. The logic circuit will then compare the value o both cycles. I either one o the counter reaches the number o N while the other number is still smaller than N-1, then the logic value o will become one which means that the requency o VO is still greater than the required ppm. A small pulse o reset signal,, will then occur and trigger a low to the output signal, LOK. The counters will then being reset and recount the number o cycle again. The whole process will continue until the other counter number is greater or equal to N-1. The timing diagrams o the in-lock condition are shown in Fig. 3a. As or the out-o-lock condition, the pass transistor logic will then increase the number o cycle count. Instead o comparing the cycle number o N-1 + 1, the logic circuit is now compared to the cycle number o N-1 + k, where k is an integer. ue to this increase in number, the required ppm has increased or out-o-lock condition. Fig. 3b F EF F IV Fig.. LK N-bit ounter ESET LK N-bit ounter ESET Block diagram o the proposed L architecture. shows the timing diagrams o out-o-lock condition. The ollowing section will show the calculation and analysis o the proposed L circuit. III. ALULATION AN ANALYSIS For the in-lock condition, the logic circuit compares both cycle number o N-1 and N In order to obtain a logic high or the LOK signal, the period o VO has to satisy the ollowing conditions, 1 TEF TIV A 0 A k B 0 B k -FF + 1a + 1 T T 1b and IV EF where T EF and T IV are the period o F EF and F IV respectively. By combining these two conditions, the -FF ESET -FF ESET LOK LOK

4 A 1A N-bit ounter F EF B 1B N-bit ounter ecision Logic ircuit F IV Fig. 4. Layout o the proposed L architecture. LOK around ±488ppm and the equation can be written as lock VO lock 3 A k A 0 F EF A k B 1B 0 F IV a In order or the lock detector to change rom in-lock to out-o-lock, it will then use N-1 + k, where k is an integer, as a reerence instead o N Hence, the requency range will be larger and is given by k + lock VO As the value o N has been set by the previous required ppm, the ppm or out-o-lock is then being set by the value o k. I the value o k is chosen to be, the required ppm is around ±1950ppm and can be written as N 1 + k lock lock VO lock 5. LOK b Fig. 3. Timing diagrams o the proposed L architecture. requency range o IV and VO or the in-lock is given as ollows, EF IV +1 lock VO N 1 +1 where lock is the required VO requency. When N is equal to 1, the required ppm or in-lock condition will be EF lock a b IV. SIMULATION ESULTS AN ISUSSION The proposed L circuit is implemented by using Global-oundries 0.18-μm MOS process. It is simulated in adence SpectreF environment. The N-bit counter is implemented with the transmissionn gate architecture and the logic gates are implemented with static complementary MOS technology. Fig. 4 shows the layout diagram o the proposed L design. It consumes a total area o µm. In order to ensure the unctionality o the proposed L, it is simulated in a dual-loops design shown in Fig. 1. The operates under a data rate o 10-Gb/s with a requency divider o 16. The simulation results are shown in Fig. 5. At the starting, as VO requency is very ar away or the operating requency, the LOK signal is low to enable the requency tracking loop to track the requency. As the requency o VO is being locked, the LOK signal changes to high. The phase tracking loop

5 ppm or out-o-lock condition. It oers a compact design and consumes only 1.1-mW at 1.8V supply voltage. Fig. 5. tracking tracking Finished Tracking Interruption LOK signal set back to low due to LPF interruption Simulation results o the proposed L architecture. will start to track the phase and recover the clock. However, when there are some interruptions to the control voltage, the L will then signal a low to the LOK signal so that the requency tracking loop will track the requency again. At a power supply voltage o 1.8V, the proposed L consumes only 1.1-mW. V. ONLUSION A novel lock detector with hysteresis property is proposed in this paper. It has the ability to give a smaller required ppm or in-lock condition and a larger required EFEENES [1] J. Savoj and B. azavi, High-speed MOS circuits or optical receivers. Boston: Kluwer Academic Publishers, 001. [] H. Ming-ta and G. Sobelman, "Architectures or multigigabit wire-linked clock and data recovery," ircuits and Systems Magazine, IEEE, vol. 8, pp , 008. [3]. Fan-Ta and W. Jen-Ming, "An Extended Phase etector.56/3.gb/s lock And ata ecovery design with igitally Assisted etector," in ircuits and Systems, 009. ISAS 009. IEEE International Symposium on, 009, pp [4] Y. Jae-Wook, K. Tae-Ho, K. ong-kyun, and K. Jin-Ku, "A MOS 5.4/3.4Gbps dual-rate clock and data recovery design or isplayport v1.," in SO onerence SO, 010 IEEE International, 010, pp [5] S. Byun, J.. Lee, J. H. Shim, K. A. K. K. Kim, and H. K. A. Y. H. K. Yu, "A 10-Gb/s MOS and EMUX I With a uarter-ate Linear Phase etector," Solid-State ircuits, IEEE Journal o, vol. 41, pp , 006. [6] V. Melikyan, A. Hovsepyan, M. Ishkhanyan, and T. Hakobyan, "igital lock detector or PLL," in esign & Test Symposium EWTS, 008 East-West, 008, pp [7] A. Hovsepyan, V. Melikyan, M. Ishkhanyan, T. Hakobyan, and G. Harutyunyan, " detector with stable parameters," in esign and Test Workshop IT, 009 4th International, 009, pp. 1-4.