An Optimized Implementation Truncated Multiplier in FPGA Technology

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1 An Optimized Implementation Truncated Multiplier in FPGA Technology 1 K. Yogitha Bali M.Tech, VLSI Design, 2 Chakri Sreedhar, Asst. Professor, ECE Department, 1 yogitha.konidala@gmail.com, 2 chakri.sreedhar@gmail.com. ABSTRACT: Multiplication of two numbers is one of the most area consuming arithmetic operations in highperformance circuits as it generates a product with twice the original bit width. The truncation of product bits to the required precision of truncated multipliers offers significant improvements in area, delay and power. The proposed method reduces the number of full adders and half adders during the tree reduction. Usually the product of two numbers appears as output in the form of LSB and MSB. Multiplication is frequently required in digital signal processing. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most signal processing applications, a rounded product is desired to avoid growth in word size. Thus an important design goal is to reduce the area requirement of the rounded output multiplier. This paper presents a method for parallel multiplication which computes the products of two n-bit numbers by summing only the most significant columns with a variable correction method. Keywords: Truncated multiplier, truncated error, modified booth algorithm, high speed applications, partial products. I. INTRODUCTION parallel multipliers provide high speed method for multiplications, but require large area for VLSI implementation. In most signal processing applications, rounded product is required to avoid growth in word size. Thus an important aim is to design a multiplier which required less area and that is possible with the truncated multiplier. In the wireless multimedia word, DSP systems are ubiquitous. DSP algorithms are computationally intensive and test the limits of battery life in portable device such as cell phones, hearing aids, MP3 players, digital video recorders and so on. Multiplication is the main operation in many signal processing algorithms hence efficient parallel multipliers is desirable. A full-width digital n n bits multiplier computes the 2n bits output as a weighted sum of partial products. A multiplier with the output represented on n bits output is useful, as example, in DSP data paths which saves the output in the same n bits registers of the input. A truncated multiplier is an n n multiplier with n bits output. Since in a truncated multiplier the n less significant bits of the fullwidth product are discarded, some of the partial products are removed and replaced by a suitable compensation function, to trade-off accuracy with hardware cost. As more columns are eliminated, the area and power consumption of the arithmetic unit are significantly reduced, and in many cases the delay also decreases. II. TREE REDUCTION OF PARALLEL MULTIPLIERS A parallel tree multiplier design typically consists of three major steps, i.e., partial products generation, partial products reduction, and final carry propagate addition. Partial products generation will produce partial products bits from the multiplicand and the multiplier. The main goal of partial product reduction is to compact the number of partial products to two, and summed up by the final addition. The two most well-known reduction methods are Wallace tree and Dadda tree reductions. Wallace tree reduction manages to constrict the partial products as early as possible, whereas Dadda

2 reduction only performs compression if it is necessary without increasing the number of carry-save addition (CSA) levels. There are two reduction schemes that intend to minimize the use of half adders (HAs) in each column because the full adder (FA) cell has a higher compression rate compared with that of Half Adder cell. In tree reduction of parallel multipliers, hybrid Scheme-1 and Scheme-2 reductions were adopted for the truncated multiplier design in order to minimize the area cost. Fig. 1(a) and (b) shows the reduction procedures by Scheme 1 and Scheme 2 to each column of partial product bits, starting from least significant Colum. major concern here, were it plays a crucial role when output precision is concerned. Fig1(b).shows the reduction procedures by scheme 2 to each column of partial product bits, reduction starting from the least significant column. Scheme 1 having minimum CPA (carry propagate addition) bit width as twice reduction efficiency when compared to the Wallace method which produces the same result as that of RA method. Fig1 (b). Shows reduction procedure of scheme 2. Scheme 1 is only used to determine whether an HA is needed and how many FAs are required in the percolumn reduction that does not exceed the maximum number of Carry Save Additions in reduction levels. Fig1 (a) Scheme1 (38 FAs and 8 HAs). These methods mainly discuss about the cost compensation. By comparing the methods of Dadda, Wallace and RA with scheme1 and Scheme2, the reduction of bits are better, so the area can be saved higher than the former methods. From the literature survey it is clear that Various researchers are working in these areas to optimize the same. Compression ratio also takes up its Fig 1(b) Scheme2 (35 FAs and 7 HAs). III. Wallace Tree Multiplier The Wallace Tree multiplier proposed in. The reduction scheme published by Wallace begins by grouping the partial- product matrix into sets of three rows. Each set is reduced to two rows using halfapply m=3 full adder to that column. This tends to

3 adders on sets of two bits and full-adders on sets of three bits. Excess rows that do not belong to a set of three are passed to the next reduction stage unmodified. Each reduction stage is processed in a similar way until only two rows remain. Then a final CPA (Carry Propagate Adder) is used. Fig.2 shows the dot diagram illustrating Wallace reduction for an 8 8 multiplier. Dot diagrams, developed by Dadda, are a convenient means for visualizing the placement of full-adders and half adders. In such diagrams, dots represent bits, given by partial products. For example, the upper-right dot in the multiplication matrix is x8y8. The circle with three dots represents a Full-Adder (FA). Fig 3. Wallace reduction for an 8*8 multiplier. Full circle: Full Adder, Half circle: Half Adder. The operation of channel separation is applied on the watermarked color image to generate its sub images, and then 2-level discrete wavelet transform is applied on the sub images to generate the approximate coefficients and detail coefficients. In the next stage the circle is substituted by its outputs: a bit sum, a dot in the same column, and a bit carry, a dot in the column on the left. Same reasoning is valid for the half-adder, represented by a circle with dashed line. Summarizing in the Wallace tree the number of the operands is reduced at the earliest opportunity, so, if there are m dots in the column we immediately minimize the overall delay by making the final CPA as short as possible intensity that makes it sensitive to intensity variations in the illumination or the geometry of the object. IV. TRUNCATED MULTIPLIERS Parallel multipliers are typically implemented as either carry-save array or tree multipliers. In many computer systems, the (n+m)-bit products produced by parallel multipliers are rounded to r bits to avoid growth in word size. As presented in, truncated multiplication provides an efficient method for reducing the hardware requirements of rounded parallel multipliers. With truncated multiplication, only the r+k most-significant columns of the multiplication matrix are used to compute the product. The error produced by omitting the m+n r k least-significant columns and rounding the final result to r bits is estimated, and this estimate is added along with the r + k most-significant columns to produce the rounded product. Although this leads to additional error in the rounded product, various techniques have been developed to help limit this error. One method to compensate for truncation is Constant Correction Truncated (CCT) Multipliers. In this method a constant is added to columns n+m r 1 to n+m r k of the multiplication matrix. The constant helps compensate for the error introduced by omitting the n +m r k least-significant columns (called reduction error), and the error due to rounding the product to r bits (called rounding error). The expected value of the sum of this error E totalis computed by assuming that each bit in A, B and P has an equal probability of being one or zero. Consequently, the expected value of the total error is the sum of expected reduction error and the expected rounding error as Where S = m + n r [14]. The constant C total is obtained by rounding E total to r + k fractional bits, such that bias constant of ¼ ulp. The deletion error after the bias

4 Where round(x) indicates that x is rounded to the nearest integer. Although the value of k can be chosen to limit the maximum absolute error to a specific precision, this paper assumes the maximum absolute error is limited to one unit in the last place (i.e., 2 r). The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design. In a truncated multiplier, several of the least significant columns of bits in the partial product matrix are not formed. Fig.5 Show 8x8 truncated multiplication.(a) deletion, reduction and truncation. (b) deletion, reduction, truncation, and final addition. adjustment 1/4 ulp ED 1/4 ulp. In Fig. 5, the deletion of partial product bits starts from column 3 by skipping the first two of partial product bits. After the deletion of partial product bits, perform column-bycolumn reduction of scheme 2. After the reduction, perform the truncation, which will further removes the first row of (n-1) bits from column 1 to column (n-1). It will produces the truncation error which is in the range of 1/2 ulp ET 0. Hence introduction of another bias constant of ¼ ulp in truncation part. So the adjusted truncation error is 1/4 ulp ET 1/4 ulp. B. Rounding and Final Addition All the operations (deletion, reduction, and truncation) are done, finally the PP bits are added by using CPA (carry propagate addition) to generate final product of P bits. Before the final CPA, add a bias constant of ½ ulp for rounding. Rounding error is in the form of - 1/2 ulp ER 1/2 ulp. The faithfully truncated multiplier has the total error in the form of ulp<e=(ed+et+er) ulp. C. Proposed Algorithm Fig 4. 8x8truncated multiplication.(a) deletion, reduction and truncation. (b) deletion, reduction, truncation, and final addition. A. Deletion, Reduction, and Truncation of partial product bits In the first step deletion operation is performed, that removes all the avoidable partial product bits which are shown by the light gray dots (fig 4). In this deletion operation, delete as many partial product bits as possible. Deletion error ED should be in the range 1/2 ulp ED 0.Hereafter, the injection correction Fig.7 Synthesis results of proposed truncated multiplier

5 Fig 5. Shows Proposed Truncated Multiplier. In proposed architecture we can multiply 8x8 bits, and the bits are reduced in step by step manner. Deletion is the first operation performed in Stage 1 to remove the PP bits, as long as the magnitude of the total deletion error is no more than 2 P 1.Then number of stages to reduce the final bit width without increasing the error. In normal truncated multiplier design, the architecture produces the output with some truncation error. But in the proposed design of truncated multiplier the truncation error is not more than 1 ulp, so the precision of the final result is improved. Fig. 5 shows proposed truncated multiplier. This reduces the area and power consumption of the multiplier. It also reduces the delay of the multiplier in many cases, because the carry propagate adder producing the product can be shorter. V. RESULTS The simulation and synthesis result of improved faithfully rounded truncated multiplier design is shown in the Fig. 6 and Xilinx ISE software is used to simulate and synthesis the proposed design. Fig. 6 Simulation result of proposed faithfully rounded truncated multiplier VI. CONCLUSION There are many works proposed to reduce the truncation error by adding error compensation circuits so as to produce a précised output. In this approach jointly considers the tree reduction, truncation, and rounding of the PP bits during the design of fast parallel truncated multipliers, so that the final truncated product satisfies the precision requirement. In this approach truncation error is not more than 1ulp, so there is no need of error compensation circuits, and the final output will be précised. The scheme1, scheme2 and proposed multiplier architecture has been simulated and synthesized using XILINX ISE Design Suite REFERENCES [1] J. M. Jou, S. R. Kuang, and R. D. Chen, Design of lowerror fixedwidth multipliers for DSP applications, IEEE Trans. Circuits Syst. II, s Analog Digit. Signal Process., vol. 46, no. 6, pp , Jun [2] L.-D. Van and C.-C. Yang, Generalized low-error areaefficient fixed width multipliers, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8, pp , Aug [3] M. J. Schulte and E. E. Swartzlander, Jr., Truncated multiplication with correction constant, in VLSI Signal Processing VI. Piscataway, NJ:IEEE Press, 1993, pp [4] E. J. King and E. E. Swartzlander, Jr., Data-dependent truncation scheme for parallel multipliers, in Proc. 31st Asilomar Conf. Signals, Syst. Comput., 1997, pp [5] M. J. Schulte, J. G. Hansen, and J. E. Stine, Reduced power dissipation through truncated multiplication, in Proc. IEEE Alessandro Volta Memorial Int. Workshop Low Power Des., 1999, pp [6] T.-B. Juang and S.-F. Hsiao, Low-error carry-free fixedwidth multipliers with low-cost compensation circuits, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp , Jun [7] A.G.M. Strollo, N. Petra, and D. De Caro, Dual-tree error compensation for high-performance fixed-width multipliers, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.52, no. 8, pp , Aug