Zynq-7000 Extensible Processing Platform Press Backgrounder

Transcription

1 Press Backgrounder March 1, 2011 Zynq-7000 Extensible Processing Platform Press Backgrounder The first question you may ask about the new Extensible Processing Platform is what exactly was the thinking behind the name Zynq? Well, it s easily associated with zinc the compound element that is so ubiquitous that it can be found in everything from batteries, sun screen, brass and medicine. As an alloy, zinc combines with things to enhance them, often appearing in different colors, depending on what it is combined with. The most well known use of zinc is for the process of galvanization. So what s the connection? During the Embedded Systems Conference Silicon Valley on April 2010, Xilinx announced architectural details of its Extensible Processing Platform, an ARM (i.e. ubiquitous ) processor based SoC for complex embedded systems requiring high-performance, low power, and multi-core processing. The core essence of the Xilinx Extensible Processing Platform in terms of silicon hardware is the merging (i.e. combines with things ) of a base, generic dual ARM Cortex -A9 MPCore processor-based system as the master, paired with low-power 28nm process technology that offers high levels of flexibility, configurability and performance. Because the programmable logic portion of these new devices is based on Xilinx s 28nm, 7 Series FPGAs, 7000 was added to the family name to be somewhat consistent with the current generation of FPGAs as well as to have a convenient way of adding additional family members over time. Beyond the silicon, the Xilinx Zynq family is the basis for a platform that ultimately is the product. The galvanization of the tools for developing software and implementing hardware design, widely-adopted operating systems, debuggers, IP and other elements made by the

2 ecosystem of Xilinx Alliance Program and ARM Connected Community members is what makes the Extensible Processing Platform possible. A Processor Centric Development Flow The Zynq-7000 Extensible Processing Platform relies on a familiar tool flow that allows embedded software and hardware engineers to perform their respective development, debug and implementation tasks in a similar fashion to the embedded design methodologies already delivered through the Xilinx ISE Design Suite and third party tools. Software application engineers can use the same ARM development tools they have used for previous designs. Xilinx provides the Software Development Kit (SDK), an Eclipse based tool suite, for embedded software application projects. Other third party development environments, such as the ARM Development Studio 5 (DS-5 ) ARM RealView Development Suite (RVDS ), can also be used. The processing subsystem can be powered up and booted independently from the programmable logic fabric. Application software engineers can choose from a number of pre-configured processor system boot codes for uni-processor, asymmetric multi-processor (AMP), or symmetric multi-processor (SMP) CPU topologies. These pre-configured boot codes serve as example boot codes and have the appropriate peripheral, drivers, and APIs enabled for the chosen topology for a particular evaluation board. This will enable the software engineers to get started without any dependencies on hardware or firmware engineers. Bridging the gap between software applications and hardware design, firmware engineers will take advantage of a new capability delivered in the ISE Design Suite Embedded Edition, the Processor Configuration Tool (PCT). The PCT is used to graphically configure system level and peripheral registers in the processing subsystem. Once configured, the PCT outputs configuration files that are used in conjunction with the boot code, to create a customized boot environment. SDK can then be used to compile and debug the board support package. The hardware design flow is similar to the embedded processor design flow in the ISE Design Suite with a few new steps for the Extensible Processing Platform. The processing subsystem is a complete dual processor system with an extensive set of commonly used peripherals. A hardware designer can extend the processing power by attaching additional peripherals in the 2

3 programmable logic to the processing subsystem. The hardware development tool, Xilinx Platform Studio, automates many of the common hardware development steps. The PCT is also used to assist designers with optimized device pinouts. One Processing System - Four Devices Each of the Zynq-7000 family s four devices have the exact same ARM processing system, but the programmable logic resources vary for scalability and fit for different applications. The Cortex-A9 Multi-Processor core (MPCore) consists of a cluster of two CPUs. Each CPU is a Cortex A9 processor with dedicated NEON co-processor (a media and signal processing architecture that adds instructions targeted at audio, video, 3-D graphics, image and speech processing), and double precision floating point unit. The Cortex-A9 processor is a highperformance, low-power, ARM macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The processor implements the ARMv7tm architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte codes in Jazelle state. In addition, the processing system includes a Snoop Control Unit, a level-2 (L2) Cache Controller, on-chip SRAM, Timers/Counters, DMA, System Control Registers, Device Configuration and an ARM CoreSight system. For debug, it contains an Embedded Trace Buffer (ETB), an Instrumentation Trace Macrocell (ITM) and a Cross Trigger module (CTI) from ARM. In addition to these it also contains AXI Monitor (AXIM) and Fabric Trace (FTM) modules from Xilinx. The two larger devices, the Zynq-7030 and Zynq-7040 devices include high-speed, low-power serial connectivity with built-in multi-gigabit transceivers operating up to Gbps. Both these devices offer approximately 1.9 million and 3.5 million equivalent ASIC gates (125K and 235K logic cells) respectively and DSP resources that deliver 480 GMACs and 912 GMACs of peak performance. The two smaller devices, the Zynq-7010 and Zynq-7020 devices provide roughly 430,000 and 1.3 million ASIC gates (30K and 85K logic cells) respectively, with 58 GMACs and 158 GMACs of peak DSP performance. Each device contains a general-purpose analog-to-digital converter (XADC) interface, which contains two 12-bit, 1 Msps ADCs, on-chip sensors, and external analog input channels. The XADC offers enhanced functionality over the system monitor found in previous generations of Virtex FPGAs. These two 12-bit ADCs support sample rates of up to one million samples per 3

4 second and can sample up to 17 external-input analog channels. The ADCs support a diverse range of applications that need to process analog signals with bandwidths of less than 500 KHz. The programmable logic can be configured by the user and connected together through interconnect blocks to provide arbitrary, user-defined logic functions that can extend the performance and capabilities of the processor system. An array of interconnect blocks work together to route signals between logic blocks as required by the application. Xilinx programmable logic software tools compile application RTL into a bit file, which is loaded into the programmable logic to configure the functionality of the programmable logic. Applications can load a single static programmable logic configuration, or select a configuration as needed by the application dynamically. It is also possible to configure selected regions of the programmable logic through partial reconfiguration techniques. The interconnect operation between the two regions of the device is largely transparent to the user. Access between master and slave is routed through the AXI interconnect based on address range, i.e., each slave device is assigned an address range. Multiple masters can access multiple slaves simultaneously and each AXI interconnect uses a two-level arbitration scheme to resolve contention. With over 3000 internal interconnects amounting to roughly 100 Gb of bandwidth, the tight coupling of the processing system with the programmable logic give systems architects a processing platform that provides a high bandwidth and low-latency interface for unprecedented optimization of hardware/software partitioning for computationally intensive applications. The Industrial market, for example, requires small size, flexible partitioning, high performance, low cost and eco-system support for successful development and implementation of industrial control systems. The dual Cortex-A9 MPCore-based processing system, coupled with the parallelprocessing capabilities of the programmable logic deliver the compute power needed for deterministic performance required by today s factory automation and vision systems. In the automotive market, image processing and recognition for collision avoidance systems need single-chip platforms that deliver massive DSP acceleration on top of low system power and cost that comes with high integration. The dual Cortex-A9 MPCore-based processing system, coupled with the massive parallel-processing capabilities of the programmable logic deliver the compute power for image processing and advanced analytic functions necessary for intelligent systems for automotive as well as many other markets. 4

5 Summary The combination of ARM s dual-core Cortex-A9 MPCore processors and Xilinx s 28nm programmable logic presents a tremendous amount of serial and parallel processing performance for high-end embedded systems. With a unified design flow for software and hardware design and implementation, embedded design teams can work within their customary design environments for maximum productivity. However, the most compelling attribute of the Zynq Extensible Processing Platform family is the customer's ability to build a custom solution, with a low total-cost of ownership, that meets their unique needs and differentiates their products. 5