FPGA Acceleration using OpenCL & PCIe Accelerators MEW 25

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1 FPGA Acceleration using OpenCL & PCIe Accelerators MEW 25 December 2014

2 FPGAs in the news» Catapult» Accelerate BING» 2x search acceleration:» ½ the number of servers» <30% of added server TCO» ~10% increase in power» Intel Xeon + FPGA MCM» Announced by Diane Bryant» SVP & GM of Intel Datacenter Group (DCG)» 10x acceleration for certain tasks» QPI gives 2x speed up again» IBM POWER architecture now open» Coherent Accelerator Processor Interface (CAPI)» FPGA card now a processor peer» Coherent memory access (1TB)» PCIe latency reduced by 90%

3 Market Developments enabling adoption Altera Stratix 10: Intel 14nm 3D FinFet Clock speeds to exceed 1GHz Dedicated floating point silicon (10TF/s) FPGA + ARM (64-bit) SoCs Xeon with FPGA co-processor! Altera FPGA demo (booth #3821) First ever IEEE 754-compliant FPGA Up to 1.5 TFLOPS floating-point performance Demo of 20 nm Arria 10 FPGA running matrix multiply at a 1 TFLOP Programmability Altera SDK for OpenCL Xilinx OpenCL toolflow SC 14 Libraries and an eco-system!

4 Target Application Areas Network Security Sensor Processing Finance HPC Image Processing Oil & Gas Two fundamental use cases: 1. Intelligent networking and integrated low latency I/O processing 2. Co-processing / CPU off-load for energy-efficient heterogeneous HPC

5 Nallatech at a glance Server qualified accelerator cards featuring FPGAs, network I/O and an open architecture software/firmware framework Design Services/Application Optimisation» 21 years of FPGA heritage» Energy-efficient High Performance Heterogeneous Computing» Real-time, low latency network and I/O processing» Altera OpenCL partner» IBM ISR Partner» HP 3PO program member» Successfully deployed 1,000 FPGA accelerator cards on a HP Proliant cluster

6 FPGA Accelerator Cards» Server qualified, cost effective, deployment-ready» 385» 395 Low profile PCIe (NIC-size) Altera Stratix V FPGA: D5 or A7 PCIe Gen3 x 8 host interface (2) SFP+ network ports (2) banks of DDR3 SDRAM ¾ Length PCIe (GPU-size) Altera Stratix V FPGA: D8 or AB PCIe Gen3 x 8 host interface (4) SFP+ network ports (4) banks of DDR3 SDRAM (2) banks of QDR-II+ SRAM

7 Board Support Packages (BSPs)» Nallatech designs, qualifies, and supports BSPs for the Altera OpenCL Software Development Kit (SDK)

8 Bioinformatics - Smith-Waterman (integer)» Sequence Alignment» Scoring Matrix» Advantage FPGA» Integer arithmetic» SMT Streaming Platform Power (W) Performance (MCUPS) Efficiency (MCUPS/W) W3565 Xeon Processor nvidia K PCIe385 A7 Accelerator x416

9 Complex Fluid Simulation - Lattice Bolzmann (sp float)» Memory Bound problem: performance is limited by the Global Memory bandwidth» FPGA uses a Sliding Window technique with performance only limited by pipeline depth x8.3

10 Data Streaming AES Encryption (OpenCL v2.0 PoC)» Direct I/O processing» Two 40GbE network ports» Counter-based encryption/decryption» 256-bit key» Advantage FPGA» Integer arithmetic» Coarse grain bit operations Platform E5503 Xeon Processor Performance/W (GB/s per W) (single core) AMD Radeon HD PCIe385 A7 Accelerator x126

11 385A: PCIe FPGA Accelerator Card Arria GX / 1150GX FPGA OpenCL compatible FPGA accelerator card» Low Profile, Half Length PCIe form factor» Compatible with all popular server platforms» Altera Arria 10 FPGA (20nm)» Dual PCIe Gen3 x 8 in a PCIex16 host interface» (2) QSFP+ network ports supporting 2x 40G, 8x 10G SFP+» (2) banks of DDR4 2133MTPS, 32GB total 11

12 Summary» FPGA architecture» Exactly the logic you need (software programmable ASIC)» Performance/W advantage» Customization for datastreaming and memory subsystems» OpenCL for FPGAs» Provides both logic and data management» Time to market and productivity» Direct I/O processing allows system-level improvements» Breakthroughs» Barriers to adoption are now being addressed» High level tools» Silicon changes to target HPC and Datacenter applications» Benchmarking well underway worldwide» Early adopters are deploying 2015

13 Thank You

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