MPSoC Designs: Driving Memory and Storage Management IP to Critical Importance
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1 MPSoC Designs: Driving Storage Management IP to Critical Importance Design IP has become an essential part of SoC realization it is a powerful resource multiplier that allows SoC design teams to focus on differentiating their products rather than re-inventing the wheel. With the advent of multiple-processor SoCs (MPSoCs), design IP is entering a new frontier: memory and storage management. Contents SoC Realization and the Critical Importance of IP... 1 From IC to SoC to MPSoC...2 Data, Data Everywhere...4 SoC Storage Management Recommendations...4 SoC Realization and the Critical Importance of IP IP has become an essential part of nanometer system-on-chip (SoC) design it permits SoC design teams to focus valuable resources on product differentiation rather than wheel re-invention. For example, very few SoC design teams build their own processors anymore. That would be crazy. It s not that it s so hard to design a 32-bit RISC processor; an advanced student design team can create one over three or four days. Designing the processor isn t the hurdle; developing the robust ecosystem around it and supporting it is. Creating the software development tools compiler, assembler, linker, loader, debugger, etc. is a challenge. Keeping the tools current is another. Supporting their use in real designs is yet another. Professional quality, maintenance, and support are big drivers for the commercial design IP market, whatever the IP type. As more processors crowd into SoCs, managing their collective requests to off-chip memory and semiconductor-based storage (primarily in the form of NAND Flash and Hybrid HDD/NAND Flash devices) becomes increasingly critical to the success of the overall SoC design which brings memory and storage management IP to the fore. Late last year, Semico published a report, IP Subsystems: The Next IP Market Paradigm 1, which said: As the semiconductor industry enters the second decade of the 21st century, substantial changes to the System-on-a-Chip (SoC) design methodology are taking shape. These changes will create a new standard for how these very complex silicon solutions are conceptualized, designed, and implemented for at least this decade and possibly longer. The changes that are anticipated emphasize a rechanneling of effort away from merely implementing ever more-complex silicon solutions and towards dealing with complex applications from a system-level point of view. 1 IP Subsystems: The Next IP Market Paradigm, October 2010, Semico.
2 MPSoC Designs: Driving Storage Management IP to Critical Importance The growing use of commercial third-party design and verification IP is a fundamental part of the change to SoC design methodology noted in the Semico report. Design IP types fall into three main categories: processor, interface, and memory/storage management IP. From IC to SoC to MPSoC A new class of integrated circuit (IC) called the SoC appeared back in By definition, an SoC includes at least one processor. In the early days of SoCs, that literally meant one processor. SoC architectures of the day tended to mimic the board-level, processor-centric architectures developed in the 1980s, as shown in Figure 1. Any other IP needed was usually custom-developed internally to be placed around the purchased processor IP core. Application Processor Memory Requests Controller Drivers On-chip RAM Interface IP Figure 1: Simplified SoC architecture circa 1995 SoC design teams began to purchase third-party cores for standard interfaces such as USB and Ethernet because they had become check-box items. The interfaces themselves are now standardized, so there is incentive for design teams in creating something new with respect to most interface IP. Either the interface IP block meets the standard or it doesn t (as proven by the appropriate verification IP). It has therefore become more cost effective to use purchased third-party interface IP. Almost from the start, SoC designs started to incorporate processing elements. Perhaps a DSP for audio. Then a graphics processing unit (GPU) with first one and then two, four, or eight parallel rendering engines. As the number of on-chip processors and processing elements has grown to 6, 12, or more than 30, SoCs have evolved into multiple-processor SoCs (MPSoCs) with a distributed computing model. At the same time, individual on-chip processors have become more complex. Application Processor(s) S PHY Graphics Processor(s) Video Processor Memory- and Storage- Management Subsystem IP Audio DSP DMA Controller Flash PHY NAND Flash Figure 2: SoC architecture circa
3 MPSoC Designs: Driving Storage Management IP to Critical Importance An ARM7 processor core from the 1990s had one 8Kbyte unified instruction/data cache. A contemporary ARM Cortex -A15 MPCore processor includes four 32-bit RISC processors, each with separate 32Kbyte Level-1 (L1) instruction and data caches, plus a unified, coherent Level-2 (L2) cache that can be as large as 4Mbytes. There is a world of difference between keeping a single processor core supplied with data and keeping an MPSoC core fed with data, as shown in Figure 2. In Figure 2, many of the simple interface blocks have become entire subsystems with their own internal processing elements that place further demands on the MPSoC s memory and storage subsystems. The additional data traffic places heavier demands on the memory and storage, making intelligent management of these resources an essential requirement in the SoC s design. Although memory/storage management requirements for these packet-processing SoC designs reside in another universe compared to the memory/storage requirements of most SoC designs, SoCs with six or more on-chip processing elements are becoming very common. For example, Figure 3 shows the block diagram for a recently announced member of the Texas Instruments OMAP 5 family, the OMAP5430 SoC: Figure 3: TI OMAP 5 SoC architecture This device comprises several processing elements including two ARM Cortex-A15 MPCore processors, two ARM Cortex-M4 processor cores for real-time tasks, an Imagination Technologies POWERVR SGX544 graphics processor with multiple internal graphics pipelines, an HD video accelerator plus an additional image processor, a general-purpose DSP, a separate audio processor, and a multi-pipe display subsystem. In addition, there are more than 30 interface IP blocks on the chip. The on-chip OMAP 5 processing elements all require access to the external and NAND Flash memories connected to the OMAP 5 SoC, and these independent data streams must be managed and scheduled if the attached memory and storage devices are to be used efficiently, without wasting memory and storage bandwidth. Several vendors targeting the mobile applications market have introduced consumer-class SoCs with qualitatively similar architectures. MPSoC architecture is a design paradigm now in full force. The memory and storage management requirements for such designs are similarly complex. Sophisticated SoC architectures with many independent on-chip processing engines demand equally sophisticated approaches to on-chip memory and storage management. 3
4 MPSoC Designs: Driving Storage Management IP to Critical Importance Data, Data Everywhere The advent of MPSoCs has created a new frontier for design IP: memory and storage management. As more processors crowd onto the SoC, the management of their collective requests to off-chip memory and semiconductor-based storage (primarily in the form of NAND Flash devices) becomes increasingly critical. In the simple days when there was only one on-chip processor making memory and storage requests to (refer back to Figure 1), there really was little to manage SoC design teams could assign the task of developing memory and storage management IP to a couple of people. That s no longer the case. A system with multiple types of traffic from multiple requestors, each with different demands, in combination with a high-speed requires a memory controller with extremely advanced algorithms to schedule the traffic optimally while allowing for changes to the schedule based on real-time system priority. In addition, SoC applications have become far more data-driven than ever, which means that SoCs deal with orders of magnitude more data in the form of images, video, and audio. All of this data streams in from somewhere and spends time in intermediate storage before being processed and presented in audible or viewable form. Although mobile SoC applications set the pace here, the rising expectations for user interfaces in all types of products mean that most of today s SoC designs must be adept at moving and storing large media files. The memory and storage request scenarios have become much more complex with 10 to 20 processors, DSPs, and GPUs competing for memory and storage access. In addition, the external memories themselves, the DDR s and NAND Flash ICs, have become increasingly complex and their block-oriented communications protocols demand intelligent management to realize the full bandwidth abilities of these devices. Managing the flow and storage of this information affects the entire SoC design. If your SoC doesn t manage its memory and storage well, then it will be needlessly constrained. The effectiveness of your SoC s memory and storage management algorithms now directly influences the competitive position of your SoC against other chips. A memory and storage solution is needed that is proven, easily integrated into your design, and provides the performance, features, and fit you need. SoC Storage Management Recommendations Effective memory and storage management needs to leverage an EDA360 approach to design, which considers the application demands up front to drive system and SoC realization activities. There are many sophisticated management techniques to maximize the effective bandwidth of DDR s and Flash memory ICs. System development teams must balance component costs with the unique bandwidth requirements of their design to determine the right mix of memory and storage. It s a technical tradeoff It s a business tradeoff It s a time-to-market tradeoff You can ask an internal development team to learn these details and then incorporate the lessons learned into custom memory and storage controllers, or you can take the faster path to a competitive, working SoC by leveraging the considerable experience and expertise embodied in configurable Cadence Design IP for memory and storage management. Cadence works very closely with the major memory chip and processor IP vendors to ensure that the memory and storage needs of the most advanced processor IP cores are well met by Cadence memory and storage management IP. The technical needs of processor IP cores and memory/storage management IP are quite complementary, as is the working relationship between the leading processor IP vendors and Cadence. For example, if you look at processor IP evolution as embodied in the ARM Cortex-A15 MPCore, what s happening in the L2 cache and its cache-coherency unit drives what s needed in the overall memory architecture. Making these IP blocks integrate seamlessly requires a carefully coordinated and highly complementary collaboration between the development of the processor IP and the memory/storage management IP. 4
5 MPSoC Designs: Driving Storage Management IP to Critical Importance Our considerable experience and expertise springs from Denali Software being the acknowledged leader in memory and storage management IP, which Cadence acquired in Denali memory and storage management IP was well proven with a track record dating back to the earliest roots of commercial memory controllers. At its acquisition, Denali had a 10-year history in DDR controller IP, supporting all versions of the DDR memory interface protocol and delivering approximately 300 configured S controllers per year. Denali also had five years of experience with NAND Flash memory controller IP, delivering approximately 12 configured NAND Flash controllers per year with support for a variety Flash memory interfaces (asynchronous, synchronous, ONFi 2, and Togglemode). Add to this the 20 years of experience of the Cadence Design Services team on delivery of advanced physical interface IP (PHY and SerDes) and you have track record that is hard to beat. The selection of IP for memory and storage management is no longer a simple task, and the choices of IP to perform these tasks now require as much care and thought as does the selection of the processing elements that make use of the attached memory and storage devices. Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efficiently and profitably Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. ARM, ARM7, Cortex, and MPCore are registered trademarks and trademarks of ARM Ltd. Imagination Technologies and POWERVR are trademarks of Imagination Technologies Ltd. Texas Instruments, TI, and OMAP are trademarks of Texas Instruments /11 MV/DM/PDF
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