Design of Low Power High Performance Online Testable Multiplexers and Demultiplexers Using Reversible Logic

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1 Design of Low Power High Performance Online Testable Multiplexers and Demultiplexers Using Reversible Logic M.TECH (E.C.E), STUDENT, V.C.E ROHTAK, INDIA Abstract- Reversible logic is transpiring and encouraging as computational paradigm for applications such as low power VLSI design, quantum computing, nano technology and optical computing. Here, we will design, a new 4*4 reversible gate defined as OTG (Online Testable Gate), Peres (P), Fredkin (F), and Toffoli (T) gates. These are suitably used for the online testability in reversible logic circuits. OTG can also function as a reversible full adder with a bare minimum of two garbage outputs. OTG has shown better performance than the recently developed R1 gate (designed for providing online testability in reversible logic circuits), in terms of computational complexity. The recommended reversible gate is combined with the existing 4*4 Feynman gate for designing the online testable reversible adders such as ripple carry adder (RCA), carry skip adder (CSA) and BCD adder and 4*1 Multiplexers and 4*1 De Multiplexers. The testable reversible circuits recommended in this paper posses better performance than the recently recommended testable designs in terms of number of reversible gates, garbage outputs and unit delay. Keywords- Garbage outputs, Online Testable Gate, Power consumption, Reversible logic circuits, Reversible circuit design, Basic reversible gates, Multiplexer circuit, Online testability, High Speed. 35 I. INTRODUCTION The important consideration in a binary arithmetic circuit is energy loss, which is the problem of energy dissipation, that is. related to non-ideal property of the transistors and materials. Since development of higher from level of integration and the use of new fabrication processes, leads to the reduction in the heat loss over the last decades. However, from the Landauer s principles [1], logic computations which doesn t not possess the reversible logic, necessarily generate heat KTln2 for every bit of information which is lost, where K is the Boltzmann s constant and T is the temperature. Reversible logic circuits (gates) are one in which there exists the one-to-one mapping between vectors of inputs and outputs that is the reversible designs do not lose any information. From Bennett principle that is. KTln2 energy dissipation would not occur, if and only if a computation is carried out in a reversible way [2], as the amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation. Reversible circuits are that circuit that does not lose information. Reversible computation in a system can be performed only and only if the system comprises of reversible gates. These circuits have ability to

2 generate the unique output vector from each input vector, and vice versa, that is, there is a one-to-one mapping between input and output vectors. The reversible logic operations posses the property that they does not erase (lose) information and dissipates very less heat. Reversible logic circuits are of high interest in high-speed power aware circuits and are used in low power VLSI design, optical computing, quantum computing and nanotechnology. The most notable application of reversible logic lies in quantum computers. Under reversible logic, the testing is the major problem, as the levels of logic are much significantly higher than the standard logic [3, 4].In addition, the major goal in reversible logic design is to minimize the number of reversible gates used and garbage outputs generated (Garbage output is defined as the output which is not used as a primary output or as an input to other gate). Our main focus is on the generation of a new 4*4 reversible gate defined as OTG (Online Testable Gate), and its usage in designing the efficient design of Low Power High Performance Online Testable Multiplexers and Demultiplexers Using Reversible Logic online testable reversible adder circuits. The OTG can function as a reversible full adder.the used OTG gate is now combined with 4*4 FEYNMAN gates [5, 6] to add the online testability feature to this configuration. In addition, this testable 1-bit reversible full adder designed using the used reversible OTG gate, is found to be better than the recently developed testable full adder in terms of number of reversible gates, garbage outputs and unit delay. The 36 used OTG gate is used here to design online testable reversible adders such as ripple carry adder (RCA), carry skip adder (CSA) and BCD adder and 4*1 Multiplexers and 4*1 De Multiplexers is also demonstrated here first time in literature and it concentrates on design of online testable reversible circuits rather than the fault tolerant one [7,8]. These used online testable reversible adders designed are found to be better than the recently used testable designs, in terms of number of reversible gates, garbage outputs and unit delay. These online testable reversible circuits designed here forms the basis for a testable primitive reversible/quantum ALU. Here, we design a novel 4*4 reversible gate termed OTG (Online Testable gate) suitably for providing the online testability in reversible logic circuits. OTG can work single-handedly as a reversible full adder with bare minimum of two garbage outputs. Figure 1, defines the basic used OTG gate, which can also implement all Boolean functions. Figure 3(a), 3(b), 3(c) and 3(d) shows the implementation of OTG gate for realizing NAND, AND, NOR and OR functions. Since, NAND and NOR are universal gates, any Boolean function can be realized with OTG gate. This OTG gate is more efficient and powerful in computation complexity, in comparison with the recently used 4*4 R1 gate [9, 10] (R1 gate is shown in Figure 2, which is used for introducing online testability in reversible logic circuits). II. USED NEW GATE We have designed a novel 4*4 reversible gate termed as OTG (Online Testable gate) and CTSG (Combined Testable and Scalable

3 Sub-Grid Gate), which are suitably used for providing the online testability in reversible logic circuits. Figure 1: OTG GATE [11] Figure 3(c): OR IMPLEMENTATION [11] Figure 2: R1 GATE [11] Figure 3(a): NAND IMPLEMENTATION [11] Figure 3(d): NOR IMPLEMENTATION [11] OTG can work single handedly as a reversible full adder with bare minimum of two garbage outputs. and has an equal number of inputs and outputs. Generally, for n inputs, there exist (2n)! reversible gates. In addition 2*2 Feynman gate operates as a controlled NOT (CNOT) with property that if the control input of CNOT is set to 0, the gate acts as a BUFFER gate; and otherwise it acts as a NOT gate. This gate can also be used as fanout gate to copy a signal. Figure 4 depicts the 4*4 FEYNMAN GATE. Figure 3(b): AND IMPLEMENTATION [11] Figure 4: FEYNMAN GATE [11] 37

4 Fredkin gate (FG) is depicted in Figure 5 is 3x3 conservative reversible gate, having the mapping (A, B, C) to (P, Q, R), where A, B, C are the inputs and P, Q, R are the outputs. It is defined as 3x3 gate as it has three inputs and three outputs. Figure 6 depicts its quantum implementation. It must be noted that each dotted rectangle in Figure 6 is equivalent to a 2x2 Feynman gate and hence the quantum cost of each dotted rectangle is 1. Hence, the quantum cost of Fredkin gate consist of two dotted rectangles of which one V gate and other gate CNOT is 5. The following defined parameters play an important role in determining the complexity and performance of logic circuits, which are designed using reversible gates. These are i) Number of Reversible gates (N) used in the circuit. ii) Number of constant inputs (CI) which refers to the number of inputs which are needed to be maintained constant at that is either 0 or 1 in order to generate the given logical function. iii) Number of garbage outputs (GO), which refers to the number of unused outputs present in a reversible logic circuit. One must not avoid the garbage outputs, as these are very much essential for achieving the reversibility. iv) Quantum cost (QC), which refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated by knowing the number of primitive reversible logic gates (1x1 or 2x2) needed for realizing the circuit. 38 v) Quantum Depth (QD), which refers to the number of 1 1 or 2 2 reversible gates, which are in the longest path from input to output, and gives the quantum depth. vi) Gate levels (GL) which refers to the number of levels in the circuit, which are required for realizing the given logic functions. Reduction in any of these parameters involves the bulk of the work involved in designing a reversible circuit. Under this paper, we will synthesis the reversible multiplexer and demultiplexer using reversible gates. Figure 5: FREDKIN GATE [11] Figure 6: Quantum implementation of Fredkin gate [11] Peres gate (PG) is depicted in Figure 7 is a 3x3 reversible gate having the mapping (A, B, C) to (P, Q, R), where A, B, C are the inputs and P, Q, R are the outputs Figure 8 depicts its quantum implementation. The quantum cost of the Peres gate is 4 as it needs the two V+ gates, one V gate and one CNOT gate for its implementation. Under the existing

5 literature, among the 3x3 reversible gates, Peres gate posses the minimum quantum cost. If we made the third input C as 0, this gate can be used as an AND gate through the output R in addition to the XOR function from output Q. Figure 10: Quantum implementation of Peres gate [11] Figure 7: PERES GATE [11] Figure 8: Quantum implementation of Peres gate [11] Toffoli Gate (TG) is depicted in figure 9 is a 3x3 two-through reversible gate. Twothrough means two of its outputs are same as the inputs with the mapping (A, B, C) to (P, Q, R), where A, B, C are the inputs and P, Q, R are the outputs. If we make input C as 0, this gate can be used as an AND gate in terms of third output. Toffoli gate is one of the most popular reversible gates. Its quantum cost is 5 as depicted in Figure 10 as it requires two V gates, one V+ gate and two CNOT gates. Figure 9: TOFFOLI GATE [11] III. Design of Online Testable Reversible Adders The Figure 11 and Figure 12 depicts the basic realization of the used CTSG block as an online testable reversible full adder with the complementary R & W outputs (input E=0 in this case). Figure 11: CTSG GATE as Full Adder [11] The full adder acts as the basic building block in a ripple carry adder and the reversible online testable ripple carry adder can be designed by cascading the one-bit testable reversible full adder designed from CTSG block as depicted in Figure 8. Using this configuration, we are able to achieve the improvement ratio of 8, 1.5 and 8 in terms 39

6 of number of reversible gates, garbage outputs and unit delay, respectively. Figure 12: CTSG GATE as Full Adder [11] 40 IV. VHDL APPROACH FOR DESIGNING Under this section, we will present the number of concepts for the explanation of the design trajectory in the previous section, as clearly recognizable in VHDL. The most important trajectory is the behavior versus structure and hierarchy and abstraction. The behavioral description of a hardware building block, covers the overall design or only a part, strictly documents the relation between the input and output signals. It does not reveal anything about the division of the block into subblocks. For the existence of the such a division which must not only specifies the subblocks that make up the block, but also specifies the exact interface between the various blocks or in other words, whenever a division exists into subblocks, a description is required not only for the various input and output signals of each block, but also for the signal interaction between the various blocks gets effected. Hierarchy and abstraction, makes up a block, which has a structural description, can on their turn have their own structural description. This keeps on going recursively until we finally reaches to the elementary or atomic building blocks of the design under this lab course, these blocks are the elements from the cell library, which under different circumstances behaves as the individual transistors for the elementary building blocks. This recursive division of the building blocks results in a hierarchical description of the design that is concept, which is related to hierarchy, is abstraction, which uses the concept that at a given level in the hierarchy, not all details of the underlying levels, are important. Thus, by eliminating those details, abstraction enables us to define the calculations at a specific level in a meaningful way. Thus, it might be useful to express a calculation at a higher abstraction level in integers, while at a lower level the same calculation may be defined in terms of the bits in the binary representation of those numbers. On such design methodology is Topdown design which starts with a behavioral description of the overall system to be designed and then system is subdivided into a number of subblocks which is known as decomposition. The main advantage of using VHDL or another hardware description language in a top- down design methodology is that each decomposition step can be verified immediately and this is done by simulating the description by applying the same input signals and this approach is used as much as possible during the lab course. It must be noted that, while simulation is a common and useful tool for verifying designs, it does not provide any

7 guarantee of correctness. It is because the number of possible combinations of input patterns for circuits is hardly manageable (except for small and trivial circuits).an another approach for verification through simulation is formal verification. which proves mathematically that decomposition step preserves the behavior of the circuit. V. DESIGN OF ONLINE TESTABLE 4*1 MULTIPLEXER A Multiplexer is also known as data selector. A Multiplexer is a combinational circuit, which has given a certain number (usually a power of two) data inputs; let us say 2 n, where n address inputs are used as a binary number to select one of the data inputs. The Multiplexer has a single output, which has the same value as the selected data input. In other words, the Multiplexer works like the input selector of a home music system. Only one input is selected at a time, and the selected input is transmitted to the single output. While on the music system, the selection of the input is made manually, the Multiplexer chooses its input based on a binary number, the address input. Multiplexers are generally used for the conversion of parallel data lines into serial one. The truth table for a 4*1 Multiplexer and its corresponding logic diagram are depicted in Table 1 and Figure 13 below. EN S1 S0 Z I I I I3 0 x x 0 Table 1: Truth Table for 4*1 Multiplexer 41 Figure 13: 4*1 Multiplexer [12] In order to design a multiplexer circuit using reversible logic gates, few conditions of reversible circuit designing are to be considered which are (a) There must be no feedback. (b) There must be no fan-out. (c) Garbage outputs must be minimum. (d) Total number of gates must be minimum. The one such basic configuration is using OTG gates as shown in Figure 14. Figure 14: 4*1 Multiplexer using OTG

8 The another approach is using Type-I, which consists of 1 Peres (P), 4 Fredkin (F), and 1 Toffoli (T) gates as shown in Figure 15. its corresponding logic diagram are depicted in Table 2 and Figure 17 below. EN S1 S0 Y0 Y1 Y2 Y D D D D 0 x x Table 2: Truth Table for 1*4 Demultiplexer Figure 15: 4*1 Multiplexer using Type-I approach [12] Another approach is using Type- II, which consists of 1 Peres (P) and 3 Fredkin (F) gates as shown in Figure 16. Figure 16: 4*1 Multiplexer using Type-II approach [12] VI. DESIGN OF ONLINE TESTABLE 4*1 DEMULTIPLEXER A Demultiplexer is also known as data distributor. A Demultiplexer is the inverse of the Multiplexer that is it takes a single data input and n address inputs are used and has 2 n outputs. The address input helps us in determining which data output posses the same value as the data input while the other data outputs will have the value 0. Demultiplexers are generally used for the conversion of serial data into parallel lines. The truth table for a 1*4 Demultiplexer and Figure 17: 1*4 Demultiplexer [12] In order to design a demultiplexer circuit using reversible logic gates, few conditions of reversible circuit designing are to be considered which are (a) There must be no feedback. (b) There must be no fan-out. (c) Garbage outputs must be minimum. (d) Total number of gates must be minimum. Figure 18: 1*4 Demultiplexer using OTG The one such basic configuration is using OTG gates as shown in Figure 18. The another approach is using Type-I, which consists of 5 Peres (P) and 4 Toffoli (T) gates as shown in Figure

9 Figure 15: 1*4 Demultiplexer using Type-I approach [12] Another approach is using Type- II, which consists of 2 Peres (P) and 5 Toffoli (T) gates as shown in Figure 20. The above two types are compared in terms of four parameters viz., garbage outputs, quantum cost, quantum depth and number of gates used and are given in Table 3 and Table 4 below. CONFIG GO QC QD N URATIO N USED TYPE-I TYPE-II Table 3: Comparison of Performance Parameters of two Types of Reversible Multiplexer Circuits CONFIG GO QC QD N URATIO N USED TYPE-I TYPE-II Table 4: Comparison of Performance Parameters of two Types of Reversible Demultiplexer Circuits VII. CONCLUSION The basic parameters are discussed below for designing the multiplexer and demultiplexer is depicted in Table 5 below. PARAMET ER POWER CONSUMP TION (mw) MEMORY OCCUPIED (KB) COMBINA TIONAL TIME DELAY (ns) RC A CS A BC D MU X DE MU X Table 5: Discussion of Parameters Here, RCA refers to Ripple Carry Adder. CSA refers to Carry Skip Adder. BCD refers to BCD Adder. MUX refers to 4*1 multiplexer. DEMUX refers to 1*4 de multiplexer. The main focus of this paper is towards the Design of Low Power High Performance Online Testable Multiplexers and Demultiplexers Using Reversible Logic of online testable multiplexers and demultiplexers using a novel online testable reversible gate. The proposed gate is found to be better than the existing testable reversible gate in terms of the computational complexity. The recommended online testable reversible adders are defined in terms of number of reversible gates, garbage outputs and unit delay, in comparison with recently proposed work. In addition, design of online testable reversible BCD adder is 43

10 addressed first time in literature. The online testable reversible OTG gate and adders proposed in this paper will form the basic building block of testable quantum/reversible system. Presently, the work done using OTG gate is limited up to the design of fast adders, Multiplexer and de Multiplexer. In future, this will can be extended up to the design of an ALU, which also acts as online testable. The parameters such as power dissipation, power utilization, unit time delay and others will be optimized to a level so that it will replace the conventional ALU used presently. ACKNOWLEGMENT I would like to acknowledge and extend my heartfelt gratitude to Mr. Dhiraj Kapoor (Assistant Professor, Department of E.C.E) and Mr. Naveen Goel (Associate Professor & Head Department of E.C.E) who supported me to complete this paper with proper guidance. I am heartily thankful to college for facilitating various means like material, which helped to accomplish the task. REFERENCES [1] Landauer, R., Irreversibility and heat generation in the computing process. IBM J. Res. Develop., 5: [2] C.H. Bennett, Logical Reversibility of Computation, IBM J.Research and Development, 17, 525 (1973). [3] D.P. Vasudevan, P.K. Lala and J.P. Parkerson, Online Testable Reversible Logic Circuit Design using NAND Blocks, Proc,Symposium on Defect and Fault Tolerance, October 2004, pp [4] D. P. Vasudevan, P. K. Lala, J. P Parkerson, Reversible-Logic Design With Online Testability, IEEE Transactions on 44 Instrumentation and Measurement, VOL. 55, NO. 2, pp , APRIL [5] E. Fredkin, T Toffoli, Conservative Logic, International Journal of Theor. Physics, vol. 21, nos. 3-4, pp , [6] T. Toffoli., Reversible Computing, Tech memo MIT/LCS/TM-151,MIT Lab for Computer Science (1980). [7] K. N. Patel, J. P. Hayes, and I. L. Markov, ``Fault Testing for Reversible Circuits'', IEEE Trans. on CAD, 23(8), pp ,August [8] P.O. Boykin and V.P. Roychowdhury, "Reversible fault-tolerant logic" Proceedings International Conference on Dependable Systems and Networks, 2005 (DSN 2005), 28 June-1 July 2005, pp [9] D.P. Vasudevan, P.K. Lala and J.P. Parkerson, Online Testable Reversible Logic Circuit Design using NAND Blocks, Proc,Symposium on Defect and Fault Tolerance, October 2004, pp [10] D. P. Vasudevan, P. K. Lala, J. P Parkerson, Reversible-Logic Design With Online Testability, IEEE Transactions on Instrumentation and Measurement, VOL. 55, NO. 2, pp , APRIL [11] Lavanya Thunuguntla, Bindu Madhavi K, Pullaiah T Designing of Efficient Online Testable Reversible Multiplexers and DeMultiplexers with New Reversible Gate International Journal of Engineering Research and Applications (IJERA) ISSN: Vol. 2, Issue 2,Mar-Apr 2012, pp [12] Y.Syamala and A.V.N.Tilak Synthesis of Multiplexer and Demultiplexer Circuits using Reversible Logic Int. J. of Recent Trends in Engineering and Technology, Vol. 4, No. 3, Nov 2010.