Chapter 14. Control Unit Operation
|
|
- Spencer McKinney
- 7 years ago
- Views:
Transcription
1 Chapter 14 Control Unit Operation
2 Contents Micro-Operation Control of the Processor Hardwired Implementation 14-2
3 Micro-Operations Micro-Operations Micro refers to the fact that each step is very simple and accomplishes very little The execution of a program consists of the sequential execution of instructions Each instruction is executed during an instruction cycle made up of shorter subcycles The performance of each subcycle involves one or more shorter operations, that is, micro-operations 14-3
4 Constituent Element Micro-Operations 14-4
5 The Fetch Cycle Micro-Operations Four involved registers. Memory address register (MAR) : Is connected to the address lines of the system bus It specifies the address in memory for a read or write operation Memory buffer register (MBR) : Is connected to the data lines of the system bus It contains the value to be stored in memory or the last value read from memory Program counter (PC) : Holds the address of the next instruction to be fetched Instruction register (IR) : Holds the last instruction fetched 14-5
6 Sequence of Events, Fetch Cycle Micro-Operations (a) Beginning 14-6
7 Sequence of Events, Fetch Cycle Micro-Operations (b) First Step 14-7
8 Sequence of Events, Fetch Cycle Micro-Operations (c) Second Step 14-8
9 Sequence of Events, Fetch Cycle Micro-Operations (d) Third Step 14-9
10 The Fetch Cycle Sequence Micro-Operations (a) Beginning : the address of the next instruction to be executed is in the PC (b) First step : move that address to the MAR (c) Second step : bring in the instruction The desired address is placed on the address bus, the control unit issues a READ command on the control bus, and the result appears on the data bus and is copied into the MBR (d) Third step : move the contents of the MBR to the IR This free up the MBR for use during a possible indirect cycle 14-10
11 The Fetch Cycle Sequence Micro-Operations Symbolic presentation t 1 : MAR? (PC) t 2 : MBR? Memory PC? (PC) + I t 3 : IR? (MBR) Micro-operation grouping rules 1. The proper sequence of events must be followed 2. Conflicts must be avoided Micro-operation involve an addition - This addition could be performed by the ALU - The use of the ALU may involve additional micro-operations 14-11
12 The Indirect Cycle Micro-Operations Indirect addressing t 1 : MAR? (IR(Address)) t 2 : MBR? Memory t 3 : IR(Address)? (MBR(Address)) 14-12
13 The Interrupt Cycle Micro-Operations t 1 : MBR? (PC) t 2 : MAR? Save_Address PC? Routine_Address t 3 : Memory? (MBR) 14-13
14 The Execute Cycle Micro-Operations ADD R1, X t 1 : MAR? (IR(address)) t 2 : MBR? Memory t 3 : R1? (R1) + (MBR) ISZ X (increment and skip if zero) t 1 : MAR? (IR(address)) t 2 : MBR? Memory t 3 : MBR? (MBR) + 1 t 4 : Memory? (MBR) If((MBR) = 0) then (PC? (PC) +I) 14-14
15 The Execute Cycle Micro-Operations BSA X (branch and save address) t 1 : MAR? (IR(address)) MBR? (PC) t 2 : PC? (IR(address)) Memory? MBR t 3 : PC? (PC) + I 14-15
16 The Instruction Cycle Micro-Operations There is one sequence each for the fetch, indirect, and interrupt cycle, and, for the execute cycle, there is one sequence of micro-operation for each opcode Instruction cycle code(icc) 00: Fetch 01: Indirect 10: Execute 11: Interrupt 14-16
17 Flowchart for Instruction Cycle Micro-Operations 14-17
18 Functional Requirements Control Of The Processor The following three-step process leads to a characterization of the control unit: Define the basic elements of the processor Describe the micro-operations that the processor performs Determine the functions that the control unit must perform to cause the micro operations to be performed Basic functional elements ALU Register Internal data paths External data paths Control unit 14-18
19 Functional Requirements Control Of The Processor The reader should see that all microoperations fall into the following categories Transfer data from one register to another Transfer data from a register to an external interface Transfer data from an external interface to a register Perform an arithmetic or logic operation, using registers for input and output The control unit perform two basic tasks Sequencing Execution 14-19
20 Control Signals Control Of The Processor Inputs Clock Instruction register Flags Outputs Control signals within the processor Control signals to control bus 14-20
21 Model of Control Unit Control Of The Processor 14-21
22 Model of Control Unit Control Of The Processor 14-22
23 Control Signals Control Of The Processor A control signal that opens gates, allowing the contents of the MAR onto the address bus A memory read control signal on the control bus A control signal that opens the gates, allowing the contents of the data bus to be stored in the MBR Control signals to logic that add 1 to the contents of the PC and store the result back to the PC 14-23
24 A Control Signals Example Control Of The Processor Control signals go to three separate destinations Data paths ALU System bus 14-24
25 Data Paths and Control Signals Control Of The Processor 14-25
26 Micro-operation and Control Signals operation and Control Signals Control Of The Processor 14-26
27 Internal Processor Organization Control Of The Processor The ALU and all processor registers are connected by a single internal bus Gates and control signals are provided for movement of data onto and off the bus from each register Two new registers,labeled Y and Z, have been added to the organization 14-27
28 CPU with Internal Bus Control Of The Processor 14-28
29 Internal Processor Organization Control Of The Processor An operation to add a value from memory to the AC would have the following steps: t 1 : MAR<-(IR(address)) t 2 : MBR<-Memory t 3 : Y<-(MBR) t 4 : Z<-(AC) + (Y) t 5 :AC<-(Z) Register Y provide temporary storage for the other input Register Z provide temporary output storage 14-29
30 The Intel 8085 Control Of The Processor Incrementer/decrementer address latch Logic that can add 1 to or subtract 1 from the contents of the stack pointer or program counter Interrupt control This module handles multiple levels of interrupt signals Serial I/O control This module interfaces to devices that communicate 1 bit at a time 14-30
31 Intel 8085 CPU Block Diagram Control Of The Processor 14-31
32 Intel8085 External Signals Control Of The Processor 14-32
33 Intel 8085 External Signals Control Of The Processor 14-33
34 Intel 8085 Pin Configuration Control Of The Processor 14-34
35 Timing and control Control Of The Processor The control unit is identified as having two components labeled (1) instruction decoder and machine cycle encoding (2) Timing and control Timing and control accepts as inputs clock, current instruction and some external control signal Each instruction cycle is divided into from one to five machine cycles The number of machine cycles is fixed for a given instruction but varies from one instruction to another 14-35
36 Timing Diagram Control Of The Processor 14-36
37 Hardwired Implementation Control unit implementation Hardwired implementation Microprogrammed implementation Hardwired Implementation 14-37
38 Control Unit Inputs The key inputs are the instruction register, the clock, flags, and control bus signals To simplify the control unit logic, there should be a unique logic input for each opcode Decoder Takes an encoded input and produces a single output The clock portion of the control unit issues a repetitive sequence of pulses Hardwired Implementation 14-38
39 Decoder Hardwired Implementation 14-39
40 Control Unit with Decoded Inputs Hardwired Implementation 14-40
41 Control Unit Logic Derive a Boolean expression of that signal as a function of the inputs Define two new control signal, P and Q PQ = 00 PQ = 01 PQ = 10 PQ = 11 Fetch Cycle Indirect Cycle Execute Cycle Interrupt Cycle Hardwired Implementation 14-41
42 Control Unit Logic Hardwired Implementation The task of implementing a combinatorial circuit that satisfies all of these equations becomes extremely difficult The results is that a far simpler approach Microprogramming 14-42
Central Processing Unit (CPU)
Central Processing Unit (CPU) CPU is the heart and brain It interprets and executes machine level instructions Controls data transfer from/to Main Memory (MM) and CPU Detects any errors In the following
More informationBASIC COMPUTER ORGANIZATION AND DESIGN
1 BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete
More informationMICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1
MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmable
More informationChapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language
Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,
More information(Refer Slide Time: 00:01:16 min)
Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationAdvanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2
Lecture Handout Computer Architecture Lecture No. 2 Reading Material Vincent P. Heuring&Harry F. Jordan Chapter 2,Chapter3 Computer Systems Design and Architecture 2.1, 2.2, 3.2 Summary 1) A taxonomy of
More informationCHAPTER 7: The CPU and Memory
CHAPTER 7: The CPU and Memory The Architecture of Computer Hardware, Systems Software & Networking: An Information Technology Approach 4th Edition, Irv Englander John Wiley and Sons 2010 PowerPoint slides
More information150127-Microprocessor & Assembly Language
Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an
More informationMICROPROCESSOR AND MICROCOMPUTER BASICS
Introduction MICROPROCESSOR AND MICROCOMPUTER BASICS At present there are many types and sizes of computers available. These computers are designed and constructed based on digital and Integrated Circuit
More informationCPU Organisation and Operation
CPU Organisation and Operation The Fetch-Execute Cycle The operation of the CPU 1 is usually described in terms of the Fetch-Execute cycle. 2 Fetch-Execute Cycle Fetch the Instruction Increment the Program
More informationPART B QUESTIONS AND ANSWERS UNIT I
PART B QUESTIONS AND ANSWERS UNIT I 1. Explain the architecture of 8085 microprocessor? Logic pin out of 8085 microprocessor Address bus: unidirectional bus, used as high order bus Data bus: bi-directional
More informationCHAPTER 4 MARIE: An Introduction to a Simple Computer
CHAPTER 4 MARIE: An Introduction to a Simple Computer 4.1 Introduction 195 4.2 CPU Basics and Organization 195 4.2.1 The Registers 196 4.2.2 The ALU 197 4.2.3 The Control Unit 197 4.3 The Bus 197 4.4 Clocks
More informationComputer organization
Computer organization Computer design an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine inputs
More informationA s we saw in Chapter 4, a CPU contains three main sections: the register section,
6 CPU Design A s we saw in Chapter 4, a CPU contains three main sections: the register section, the arithmetic/logic unit (ALU), and the control unit. These sections work together to perform the sequences
More informationChapter 2 Basic Structure of Computers. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 Basic Structure of Computers Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Functional Units Basic Operational Concepts Bus Structures Software
More informationCentral Processing Unit
Chapter 4 Central Processing Unit 1. CPU organization and operation flowchart 1.1. General concepts The primary function of the Central Processing Unit is to execute sequences of instructions representing
More informationAn Overview of Stack Architecture and the PSC 1000 Microprocessor
An Overview of Stack Architecture and the PSC 1000 Microprocessor Introduction A stack is an important data handling structure used in computing. Specifically, a stack is a dynamic set of elements in which
More informationCSCI 4717 Computer Architecture. Function. Data Storage. Data Processing. Data movement to a peripheral. Data Movement
CSCI 4717/5717 Computer Architecture Topic: Functional View & History Reading: Sections 1.2, 2.1, & 2.3 Function All computer functions are comprised of four basic operations: Data processing Data storage
More informationLSN 2 Computer Processors
LSN 2 Computer Processors Department of Engineering Technology LSN 2 Computer Processors Microprocessors Design Instruction set Processor organization Processor performance Bandwidth Clock speed LSN 2
More informationComputer System: User s View. Computer System Components: High Level View. Input. Output. Computer. Computer System: Motherboard Level
System: User s View System Components: High Level View Input Output 1 System: Motherboard Level 2 Components: Interconnection I/O MEMORY 3 4 Organization Registers ALU CU 5 6 1 Input/Output I/O MEMORY
More informationMACHINE ARCHITECTURE & LANGUAGE
in the name of God the compassionate, the merciful notes on MACHINE ARCHITECTURE & LANGUAGE compiled by Jumong Chap. 9 Microprocessor Fundamentals A system designer should consider a microprocessor-based
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture : Microprogrammed Control Microprogramming The control unit is responsible for initiating the sequence of microoperations that comprise instructions.
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 9 - Register Transfer and Microoperations Microoperations Digital systems are modular in nature, with modules containing registers, decoders, arithmetic
More informationComputer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.
Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.tw Review Computers in mid 50 s Hardware was expensive
More informationChapter 1 Computer System Overview
Operating Systems: Internals and Design Principles Chapter 1 Computer System Overview Eighth Edition By William Stallings Operating System Exploits the hardware resources of one or more processors Provides
More informationUNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B Lab 7: MISP Processor Design Spring 1995
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180B Lab 7: MISP Processor Design Spring 1995 Objective: In this lab, you will complete the design of the MISP processor,
More informationInstruction Set Architecture. Datapath & Control. Instruction. LC-3 Overview: Memory and Registers. CIT 595 Spring 2010
Instruction Set Architecture Micro-architecture Datapath & Control CIT 595 Spring 2010 ISA =Programmer-visible components & operations Memory organization Address space -- how may locations can be addressed?
More informationSummary of the MARIE Assembly Language
Supplement for Assignment # (sections.8 -. of the textbook) Summary of the MARIE Assembly Language Type of Instructions Arithmetic Data Transfer I/O Branch Subroutine call and return Mnemonic ADD X SUBT
More informationl C-Programming l A real computer language l Data Representation l Everything goes down to bits and bytes l Machine representation Language
198:211 Computer Architecture Topics: Processor Design Where are we now? C-Programming A real computer language Data Representation Everything goes down to bits and bytes Machine representation Language
More informationChapter 01: Introduction. Lesson 02 Evolution of Computers Part 2 First generation Computers
Chapter 01: Introduction Lesson 02 Evolution of Computers Part 2 First generation Computers Objective Understand how electronic computers evolved during the first generation of computers First Generation
More informationTIMING DIAGRAM O 8085
5 TIMING DIAGRAM O 8085 5.1 INTRODUCTION Timing diagram is the display of initiation of read/write and transfer of data operations under the control of 3-status signals IO / M, S 1, and S 0. As the heartbeat
More informationThe 104 Duke_ACC Machine
The 104 Duke_ACC Machine The goal of the next two lessons is to design and simulate a simple accumulator-based processor. The specifications for this processor and some of the QuartusII design components
More information8-Bit Flash Microcontroller for Smart Cards. AT89SCXXXXA Summary. Features. Description. Complete datasheet available under NDA
Features Compatible with MCS-51 products On-chip Flash Program Memory Endurance: 1,000 Write/Erase Cycles On-chip EEPROM Data Memory Endurance: 100,000 Write/Erase Cycles 512 x 8-bit RAM ISO 7816 I/O Port
More informationBuilding a computer. Electronic Numerical Integrator and Computer (ENIAC)
Building a computer Electronic Numerical Integrator and Computer (ENIAC) CSCI 255: Introduc/on to Embedded Systems Keith Vertanen Copyright 2011 Layers of abstrac
More information2011, The McGraw-Hill Companies, Inc. Chapter 5
Chapter 5 5.1 Processor Memory Organization The memory structure for a PLC processor consists of several areas, some of these having specific roles. With rack-based memory structures addresses are derived
More informationHow It All Works. Other M68000 Updates. Basic Control Signals. Basic Control Signals
CPU Architectures Motorola 68000 Several CPU architectures exist currently: Motorola Intel AMD (Advanced Micro Devices) PowerPC Pick one to study; others will be variations on this. Arbitrary pick: Motorola
More informationPROBLEMS. which was discussed in Section 1.6.3.
22 CHAPTER 1 BASIC STRUCTURE OF COMPUTERS (Corrisponde al cap. 1 - Introduzione al calcolatore) PROBLEMS 1.1 List the steps needed to execute the machine instruction LOCA,R0 in terms of transfers between
More informationDEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC6504 - Microprocessor & Microcontroller Year/Sem : II/IV
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC6504 - Microprocessor & Microcontroller Year/Sem : II/IV UNIT I THE 8086 MICROPROCESSOR 1. What is the purpose of segment registers
More informationCentral Processing Unit Simulation Version v2.5 (July 2005) Charles André University Nice-Sophia Antipolis
Central Processing Unit Simulation Version v2.5 (July 2005) Charles André University Nice-Sophia Antipolis 1 1 Table of Contents 1 Table of Contents... 3 2 Overview... 5 3 Installation... 7 4 The CPU
More informationCPU Organization and Assembly Language
COS 140 Foundations of Computer Science School of Computing and Information Science University of Maine October 2, 2015 Outline 1 2 3 4 5 6 7 8 Homework and announcements Reading: Chapter 12 Homework:
More informationAddressing The problem. When & Where do we encounter Data? The concept of addressing data' in computations. The implications for our machine design(s)
Addressing The problem Objectives:- When & Where do we encounter Data? The concept of addressing data' in computations The implications for our machine design(s) Introducing the stack-machine concept Slide
More informationADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM 1 The ARM architecture processors popular in Mobile phone systems 2 ARM Features ARM has 32-bit architecture but supports 16 bit
More informationGUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT. COURSE CURRICULUM COURSE TITLE: COMPUTER ORGANIZATION AND ARCHITECTURE (Code: 3340705)
GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM COURSE TITLE: COMPUTER ORGANIZATION AND ARCHITECTURE (Code: 3340705) Diploma Programmes in which this course is offered Computer Engineering
More informationProgramming Logic controllers
Programming Logic controllers Programmable Logic Controller (PLC) is a microprocessor based system that uses programmable memory to store instructions and implement functions such as logic, sequencing,
More informationChapter 4 Lecture 5 The Microarchitecture Level Integer JAVA Virtual Machine
Chapter 4 Lecture 5 The Microarchitecture Level Integer JAVA Virtual Machine This is a limited version of a hardware implementation to execute the JAVA programming language. 1 of 23 Structured Computer
More information1 Classical Universal Computer 3
Chapter 6: Machine Language and Assembler Christian Jacob 1 Classical Universal Computer 3 1.1 Von Neumann Architecture 3 1.2 CPU and RAM 5 1.3 Arithmetic Logical Unit (ALU) 6 1.4 Arithmetic Logical Unit
More informationChapter 5 Instructor's Manual
The Essentials of Computer Organization and Architecture Linda Null and Julia Lobur Jones and Bartlett Publishers, 2003 Chapter 5 Instructor's Manual Chapter Objectives Chapter 5, A Closer Look at Instruction
More informationComputer Architecture
Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two
More informationInstruction Set Architecture (ISA)
Instruction Set Architecture (ISA) * Instruction set architecture of a machine fills the semantic gap between the user and the machine. * ISA serves as the starting point for the design of a new machine
More information1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
More informationChapter 02: Computer Organization. Lesson 04: Functional units and components in a computer organization Part 3 Bus Structures
Chapter 02: Computer Organization Lesson 04: Functional units and components in a computer organization Part 3 Bus Structures Objective: Understand the IO Subsystem and Understand Bus Structures Understand
More informationCS101 Lecture 26: Low Level Programming. John Magee 30 July 2013 Some material copyright Jones and Bartlett. Overview/Questions
CS101 Lecture 26: Low Level Programming John Magee 30 July 2013 Some material copyright Jones and Bartlett 1 Overview/Questions What did we do last time? How can we control the computer s circuits? How
More informationA3 Computer Architecture
A3 Computer Architecture Engineering Science 3rd year A3 Lectures Prof David Murray david.murray@eng.ox.ac.uk www.robots.ox.ac.uk/ dwm/courses/3co Michaelmas 2000 1 / 1 6. Stacks, Subroutines, and Memory
More informationCHAPTER 6: Computer System Organisation 1. The Computer System's Primary Functions
CHAPTER 6: Computer System Organisation 1. The Computer System's Primary Functions All computers, from the first room-sized mainframes, to today's powerful desktop, laptop and even hand-held PCs, perform
More informationMICROPROCESSOR BCA IV Sem MULTIPLE CHOICE QUESTIONS
MICROPROCESSOR BCA IV Sem MULTIPLE CHOICE QUESTIONS 1) Which is the microprocessor comprises: a. Register section b. One or more ALU c. Control unit 2) What is the store by register? a. data b. operands
More informationThe WIMP51: A Simple Processor and Visualization Tool to Introduce Undergraduates to Computer Organization
The WIMP51: A Simple Processor and Visualization Tool to Introduce Undergraduates to Computer Organization David Sullins, Dr. Hardy Pottinger, Dr. Daryl Beetner University of Missouri Rolla Session I.
More informationECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data
More informationLearning Outcomes. Simple CPU Operation and Buses. Composition of a CPU. A simple CPU design
Learning Outcomes Simple CPU Operation and Buses Dr Eddie Edwards eddie.edwards@imperial.ac.uk At the end of this lecture you will Understand how a CPU might be put together Be able to name the basic components
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More information8051 hardware summary
8051 hardware summary 8051 block diagram 8051 pinouts + 5V ports port 0 port 1 port 2 port 3 : dual-purpose (general-purpose, external memory address and data) : dedicated (interfacing to external devices)
More informationAdministrative Issues
CSC 3210 Computer Organization and Programming Introduction and Overview Dr. Anu Bourgeois (modified by Yuan Long) Administrative Issues Required Prerequisites CSc 2010 Intro to CSc CSc 2310 Java Programming
More informationManagement Challenge. Managing Hardware Assets. Central Processing Unit. What is a Computer System?
Management Challenge Managing Hardware Assets What computer processing and storage capability does our organization need to handle its information and business transactions? What arrangement of computers
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
More informationwhat operations can it perform? how does it perform them? on what kind of data? where are instructions and data stored?
Inside the CPU how does the CPU work? what operations can it perform? how does it perform them? on what kind of data? where are instructions and data stored? some short, boring programs to illustrate the
More informationUNIT 2 CLASSIFICATION OF PARALLEL COMPUTERS
UNIT 2 CLASSIFICATION OF PARALLEL COMPUTERS Structure Page Nos. 2.0 Introduction 27 2.1 Objectives 27 2.2 Types of Classification 28 2.3 Flynn s Classification 28 2.3.1 Instruction Cycle 2.3.2 Instruction
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationTYPES OF COMPUTERS AND THEIR PARTS MULTIPLE CHOICE QUESTIONS
MULTIPLE CHOICE QUESTIONS 1. What is a computer? a. A programmable electronic device that processes data via instructions to output information for future use. b. Raw facts and figures that has no meaning
More information8085 INSTRUCTION SET
DATA TRANSFER INSTRUCTIONS Opcode Operand Description 8085 INSTRUCTION SET INSTRUCTION DETAILS Copy from source to destination OV Rd, Rs This instruction copies the contents of the source, Rs register
More informationTEACHING COMPUTER ARCHITECTURE THROUGH SIMULATION (A BRIEF EVALUATION OF CPU SIMULATORS) *
TEACHING COMPUTER ARCHITECTURE THROUGH SIMULATION (A BRIEF EVALUATION OF CPU SIMULATORS) * Timothy Stanley, PhD Computer and Network Sciences, Utah Valley University, Orem, Utah 84058, 801 863-8978, TStanley@uvu.edu
More informationSerial Communications
Serial Communications 1 Serial Communication Introduction Serial communication buses Asynchronous and synchronous communication UART block diagram UART clock requirements Programming the UARTs Operation
More informationCOMPUTER ORGANIZATION AND ARCHITECTURE. Slides Courtesy of Carl Hamacher, Computer Organization, Fifth edition,mcgrawhill
COMPUTER ORGANIZATION AND ARCHITECTURE Slides Courtesy of Carl Hamacher, Computer Organization, Fifth edition,mcgrawhill COMPUTER ORGANISATION AND ARCHITECTURE The components from which computers are built,
More informationS7 for Windows S7-300/400
S7 for Windows S7-300/400 A Programming System for the Siemens S7 300 / 400 PLC s IBHsoftec has an efficient and straight-forward programming system for the Simatic S7-300 and ern controller concept can
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More informationİSTANBUL AYDIN UNIVERSITY
İSTANBUL AYDIN UNIVERSITY FACULTY OF ENGİNEERİNG SOFTWARE ENGINEERING THE PROJECT OF THE INSTRUCTION SET COMPUTER ORGANIZATION GÖZDE ARAS B1205.090015 Instructor: Prof. Dr. HASAN HÜSEYİN BALIK DECEMBER
More informationChapter 9 Computer Design Basics!
Logic and Computer Design Fundamentals Chapter 9 Computer Design Basics! Part 2 A Simple Computer! Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
More informationComputer Organization. and Instruction Execution. August 22
Computer Organization and Instruction Execution August 22 CSC201 Section 002 Fall, 2000 The Main Parts of a Computer CSC201 Section Copyright 2000, Douglas Reeves 2 I/O and Storage Devices (lots of devices,
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationZ80 Microprocessors Z80 CPU. User Manual UM008006-0714. Copyright 2014 Zilog, Inc. All rights reserved. www.zilog.com
Z80 Microprocessors Z80 CPU UM008006-0714 Copyright 2014 Zilog, Inc. All rights reserved. www.zilog.com ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG S PRODUCTS
More informationA+ Guide to Managing and Maintaining Your PC, 7e. Chapter 1 Introducing Hardware
A+ Guide to Managing and Maintaining Your PC, 7e Chapter 1 Introducing Hardware Objectives Learn that a computer requires both hardware and software to work Learn about the many different hardware components
More informationInstruction Set Design
Instruction Set Design Instruction Set Architecture: to what purpose? ISA provides the level of abstraction between the software and the hardware One of the most important abstraction in CS It s narrow,
More informationMicrotronics technologies Mobile: 99707 90092
For more Project details visit: http://www.projectsof8051.com/rfid-based-attendance-management-system/ Code Project Title 1500 RFid Based Attendance System Synopsis for RFid Based Attendance System 1.
More informationCOMPUTER ARCHITECTURE. Input/Output
HUMBOLDT-UNIVERSITÄT ZU BERLIN INSTITUT FÜR INFORMATIK COMPUTER ARCHITECTURE Lecture 17 Input/Output Sommersemester 2002 Leitung: Prof. Dr. Miroslaw Malek www.informatik.hu-berlin.de/rok/ca CA - XVII -
More informationComputer Organization and Components
Computer Organization and Components IS5, fall 25 Lecture : Pipelined Processors ssociate Professor, KTH Royal Institute of Technology ssistant Research ngineer, University of California, Berkeley Slides
More information================================================================
==== ==== ================================================================ DR 6502 AER 201S Engineering Design 6502 Execution Simulator ================================================================
More information1 Computer hardware. Peripheral Bus device "B" Peripheral device. controller. Memory. Central Processing Unit (CPU)
1 1 Computer hardware Most computers are organized as shown in Figure 1.1. A computer contains several major subsystems --- such as the Central Processing Unit (CPU), memory, and peripheral device controllers.
More informationLecture-3 MEMORY: Development of Memory:
Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
More informationComputer Organization and Architecture
Computer Organization and Architecture Chapter 11 Instruction Sets: Addressing Modes and Formats Instruction Set Design One goal of instruction set design is to minimize instruction length Another goal
More informationCSE 141L Computer Architecture Lab Fall 2003. Lecture 2
CSE 141L Computer Architecture Lab Fall 2003 Lecture 2 Pramod V. Argade CSE141L: Computer Architecture Lab Instructor: TA: Readers: Pramod V. Argade (p2argade@cs.ucsd.edu) Office Hour: Tue./Thu. 9:30-10:30
More informationAn Introduction to the ARM 7 Architecture
An Introduction to the ARM 7 Architecture Trevor Martin CEng, MIEE Technical Director This article gives an overview of the ARM 7 architecture and a description of its major features for a developer new
More informationFlip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationInstruction Set Architecture. or How to talk to computers if you aren t in Star Trek
Instruction Set Architecture or How to talk to computers if you aren t in Star Trek The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture
More informationOverview. CISC Developments. RISC Designs. CISC Designs. VAX: Addressing Modes. Digital VAX
Overview CISC Developments Over Twenty Years Classic CISC design: Digital VAX VAXÕs RISC successor: PRISM/Alpha IntelÕs ubiquitous 80x86 architecture Ð 8086 through the Pentium Pro (P6) RJS 2/3/97 Philosophy
More informationPROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1
UNIT 22: PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1 This work covers part of outcome 3 of the Edexcel standard module: Outcome 3 is the most demanding
More informationTopics. Introduction. Java History CS 146. Introduction to Programming and Algorithms Module 1. Module Objectives
Introduction to Programming and Algorithms Module 1 CS 146 Sam Houston State University Dr. Tim McGuire Module Objectives To understand: the necessity of programming, differences between hardware and software,
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More information