Computer Architecture and Organization

Transcription

1 Computer Architecture and Organization Topics of Interest o Internal structure of a CPU o Instruction execution o Addressing mode o Interrupt o Pipe lining o Parallel Processing o RISC and CSIC Power PC o Memory architecture Internal structure of a CPU The general structure of ISA (Instruction Set Architecture) computer (Von Neumann, 1952). It is the prototype of all general-purpose computers. Data Processing Unit Main Memory I/O Equipment Program Control Unit Central Processing Unit It suggest stored-program computer IT60101 Foundation of Computing Samanta 1

2 Extended version of IAS Computer Arithmetic Logic Unit (ALU) Central Processing Unit Performs all sorts of arithmetic operations Addition, subtraction, Multiplication, Division, Comparison etc. Accumulator (AC) and Multiplier Quotient (MQ) It temporarily hold operands and results of ALU operations. MQ stores the few least significant bits on multiplications. IT60101 Foundation of Computing Samanta 2

3 Memory Buffer Register (MBR) It contains a word to be stored in memory, or ID device or is used to receive a word from memory or IO device. Register Bank CPU maintains a number of register for some intermediate operations. Registers are stack pointer, Accumulator register, Index register, general purpose register, Base address register, Interrupt register, clock register etc. Memory address register (MAR) Specifies the address in memory of the words to be written from or read into the MBR. Instruction Buffer Register (IBR) Left Instruction Right instruction O p code Address O p Code Address Employed to temporarily hold the right-hand instruction from a word in memory. Instruction Register (IR) Contain the 8-bits O p code instruction being executed. Program Counter (PC) Contains the address of the next instruction-pair to be fetched from memory. Inter-connection structures A computer consists main three modules CPU, Memory and I/O. These modules are connected through a structure called interconnection structure. The interconnection structure in each module is described as below. IT60101 Foundation of Computing Samanta 3

4 Read Write Address bus Memory Data Data Read Write Address Internal data External data I/O Device Internal data External data Interrupt signals The interconnection structure support the following types of transfer. 1. Memory to CPU CPU reads an instruction or a unit of word from memory. 2. CPU to memory CPU writes a unit of word to main memory. 3. I/O to CPU CPU reads data from an I/O device via an I/O module 4. CPU to I/O CPU sends data to the I/O device 5. I/O to or from Memory I/O module is allowed to exchange data directly with memory, without going through the CPU, using direct memory access (DMA) IT60101 Foundation of Computing Samanta 4

5 CPU Memory I/O Device bits address bus bits data bus Bus interconnection in IAS Computer. 12 Control bus Some control lines are Memory write Memory read IO write IO read Transfer ACK Bus Request Bus Grant Interrupt request Interrupt ACK Clock Reset RESERVE for special use. IT60101 Foundation of Computing Samanta 5

6 Instruction Executions The basic function performed by a computer is program execution. The program to be executed consists of a set of instructions stored in memory. Instruction execution Note CPU reads (fetch) instructions from memory one at a time. Execution of instruction at ALU. Instruction cycle (Processing required for a single instruction) o Fetech cycle Execute cycle o o Basic instruction cycle (without interrupt) IT60101 Foundation of Computing Samanta 6

7 Start Fetch Instruction Fetch cycle Execute Instruction Halt Execute cycle Check for Interupt Process Interupt Interrupt cycle Basic instruction cycle (with interrupt) Instruction cycle 1. At the beginning of each instruction cycle, CPU fetches an instruction from memory. 2. A register called the program counter (PC) is used to keep track of the instruction to be fetched. PC always automatically is incremented after each instruction fetch, if not interrupt. 3. The fetched instruction is loaded into a register in the CPU (called Instruction register (IR)). 4. The CPU interprets the instruction and performs the required operation. CPU - Memory Data may be transferred from the CPU to memory or from memory to CPU. CPU IO Data may be transferred to or from between the CPU and IO-module. Data Processing CPU performs some arithmetic or logic operation on data. Control An instruction may specify that the sequence of execution be altered. IT60101 Foundation of Computing Samanta 7

8 Internal CPU operation CPU to memory or IO Instruction cycle state diagrams with Interrupt Data Path in Instruction Execution Memory M A R MBR Data bus AC MBR ALU OP code IR Operand PC Register Bank Control signals { Control block Address bus I/O Bus IO Device IT60101 Foundation of Computing Samanta 8

9 1. Instruction fetch (shown in red color) 2. IOD OAC OF (shown in violet color) 3. Data operation (shown in light color) 4. OS OAC (shown in Orange color) Addressing Modes A computer program is a sequence of instructions. Each instruction specifies the operations noted in the operation code field on the data specified by the operands in the operand field. Op code Operand Instruction format Computer provides different addressing capabilities in an instruction format. Different scheme for deriving the effective address in the operand field is termed as addressing modes. Different addressing modes are 1. Immediate 2. Direct memory 3. Indirect memory 4. Direct register 5. Indirect register 6. Relative Program counter relative Base address relative 7. Indexed addressing 8. Stack addressing 1. Immediate addressing Op Code Operand The operand data is directly specified in the operand field. Advantage - No memory/ register access - Execution is faster Disadvantage - The operand data setting restricted to the maximum value that can be fitted within the operation field. IT60101 Foundation of Computing Samanta 9

10 2. Direct memory addressing Op code Operand Address Operand The operand field in this case, a memory address where the data stored. Advantage - It requires only one memory references and no special calculation Disadvantage - It provides only a limited address space. Hence, suitable for a small computer system - The length of operand field is usually less than the word length, thus limiting the address range. 3. Indirect memory addressing In this scheme, the operand address specifies another memory location where the desired data is located. IT60101 Foundation of Computing Samanta 10

11 Op code Operand Address Operand add(x) x Advantage This scheme allow larger address space. For word length of N, an address space of 2 N is available. Note The number of different effective address that may be referenced in Direct memory address is 2 P where P is the number of bits in address field and P < N. Disadvantage Instruction execution requires two memory references to fetch the operand, one to get its address and second to get its value. 4. Direct register addressing All computer systems are usually provided with some addressable registers. If there are R number of registers, then log 2 R bits of the operand field denotes the specific register holding the data word. Op code Register number Register Bank IT60101 Foundation of Computing Samanta 11

12 Advantage - Only a small address field is required - Register reference is faster than the memory reference and hence high speed execution Disadvantage - Address space is very limited 5. Indirect Register addressing In this scheme, the operand field specifies the register R j ; the register R j contains the memory address where the operand data is located. Op code Register number Operand Data Memory Address of operand Register Advantage - Small address field - Uses one register and one memory reference. Better than Indirect memory addressing Disadvantage Address space limitation Two accesses for a reference. 6. Relative addressing In this scheme, the effective operand address is computed by adding a displacement value specified in the operand field with the value in (i) implicitly in a hardware register (such as program counter) or (ii) explicitly in a register specified in the operation field. IT60101 Foundation of Computing Samanta 12

13 Op code Displacement PC + Operand Program counter relative Memory Op code Base Reg Displacement Base Reg X + Operand Memory Base resiter relative Advantage A very powerful mode of address combines the capabilities of direct addressing and register indirect addressing - For a memory operand address referring to a memory with R- bit memory address register, the operand field requires R-bits (Base Reg). Let the segment of a memory size be 2 D, thus displacement field is D. Thus, address of an operand data can be specified with R + D bits. This is in contrast to N bits for a memory of 2 N with direct memory access. The value of R + D can be designed so that R + D < N. - Easy to implement Multiprogramming environment, where each register stores the base address of a memory location for a program. Disadvantage Disadvantage of computing the effective memory address by an addition operation resulting in additional delay. IT60101 Foundation of Computing Samanta 13

14 7. Indexed addressing Same as relative addressing except that the operand field contain an address to index register. Op code Index Reg Displacement Index + 8. Stack addressing For a memory based stack, the implied operand address for any stack operation is the Stack Pointer Register (SPR) which stores the address of the top data element of the stack. Hardware stack build with registers, although fast, limited to size of the stack. IO Accessing and Data Transfer Typically, there will be many I/O devices connected to the system. Each device is given a unique identifier or address. When the CPU issues an I/O command, the command contains the address of the desired device. Thus, each I/O module must interpret the address lines to determine if the command for itself. When the CPU, main memory and I/O share a common bus, two modes of addressing are possible 1. Memory-mapped I/O 2. I/O mapped I/O Memory-mapped I/O With memory-mapped I/O, I/O devices are connected as (virtual) memory locations. In other words, there is a single address space for memory locations and I/O devices. Each IT60101 Foundation of Computing Samanta 14

15 input device buffer is treated as a memory word providing data to the data bus and each output device buffer is also treated as a memory location where data can be written. CPU Memory Address but Data bus I/O I/O Memory- mapped I/O Advantage The memory-mapped I/O scheme does not require any special input-outpur instructions. Disadvantage The available memory space to store program and data get reduced since the total address space is shared between memory and I/O devices. I/O mapped I/O In I/O mapped I/O scheme, all I/O ports are independent of the main memory. The instruction set of CPU has special I/O instructions like Input and Output to transfer data to and from I/O devices. Note In view of separation of memory and I/O device and a memory location can have the same address. Advantage While memory-mapped I/O is simpler and cheaper to implement, its operation is likely to be slower than I/O mapped I/O scheme. In either of the above two addressing schemes, all I/O operations are classified into three basic modes I. Programmed IO II. Direct Memory Access III. Interrupt IO. IT60101 Foundation of Computing Samanta 15

16 Programmed IO In this mode of IO data transfer, the CPU controls entire I/O transaction by executing a sequence of IO instructions included in a program. The program executed by the CPU initiates, directs and terminates IO operations. Mechanism of the programmed I/O is shown below. Start Read Status register CPU IO No IO Device Ready? Yes Transfer word to or from buffer IO CPU Write (Read) character into (from) memory location. CPU Memory Update data counter & Pointer Registrer No Count = 0? End of data transfer The addition hardware necessary is the CPU to support such a programmed I/O data transfer consists of the following. IT60101 Foundation of Computing Samanta 16

17 1. Status register It is used to store current status of the I/O device. The bits of status register may indicate whether the device is ready for IO transfer, error indication, interrupt request etc. 2. Buffere register It is used to hold the data temporily till I/O device is ready to accept the data delivered by CPU or till CPU is ready to accept the data delivered by the I/O device. 3. Data counter It is loaded with the number of data bytes/words to be transferred. It is decremented automatically by one after the transfer of each word. A zero count indicates the transfer of data has been completed. 4. Pointer It is a register storing the current memory location into which the next word is to be written or from which the next word is to be read. It is updated after the transfer of each word. Interrupted IO The problem with programmed I/O is that the CPU has to wait a long time for the I/O module to be ready for either receiving or transmitting data. The CPU, while waiting, must repeatedly interrogate the status of the I/O module. As a result, the performance of the system is severally degraded. As an alternative to the programmed IO, in interrupted IO mode of data transfer, the CPU issue an I/O command to the I/O module and then go to do some other work. The I/O module will then interrupt the CPU to request service when it is ready to exchange data with CPU. The CPU, then executes data transfer, as before and then resumes its former processing. Direct Memory Access (DMA) Limitations in Programmed and interrupted IO nodes. Interrupt IO, though more efficient than simple programmed I/O, still requires the active intervention of the CPU to transfer data between memory and I/O modules, and any data transfer must traverse a path through the CPU. Thus, both these modes of I/O suffers from two inherent drawbacks 1. The I/O transfer rate is limited by the speed with which the CPU can test and service a device. 2. The CPU is tied up in managing an I/O transfer; infact, a number of instruction must be executed for each I/O transfer. IT60101 Foundation of Computing Samanta 17

18 When a large volumes of data are to be moved, the above two mode of data transfer is very inefficient. A more efficient technique called direct memory access (DMA) is known. DMA transfer requires an additional module on the system bus called the DMA controller. The DMA controller is capable of mimicking the CPU, and indeed, of taking over control of the system from the CPU. A typical block diagram of the DMA controller is shown below. CPU, Memory and I/O with DMA controller IT60101 Foundation of Computing Samanta 18

19 The DMA mode of data transfer takes place as follows. When the CPU wishes to read or write a block of data, it issues a command to the DMA controller, by sending to the DMA controller the following information. whether a Read or Write is requested The address of the I/O device involved The starting location in memory to read from or write to The number of words to be read or written. The CPU then continues with other work. The DMA controller will take care the request delegated to DMA controller. The DMA controller transfer the entire block of data, one word at a time, directly to or from memory, without going through the CPU. When the transfer is complete, the DMA controller sends an acknowledge signal to the CPU. Thus, in DMA mode of data transfer, CPU is involved only at the beginning and end of the transfer. Note It is important to note that DMA controller needs to take control of the bus in order to transfer data to and from memory. For this purpose, the DMA controller must use the bus only when the CPU does not need it. This technique is more commonly referred to as cycle-stealing. That is, the DMA controller in effect steals a bus. When the DMA controller is ready to transfer data, it activates the DMA request line input to the CPU. The CPU can respond to this request and release the system bus for use of DMA controller only at the DMA break points IT60101 Foundation of Computing Samanta 19

20 Interrupt Handling in CPU Interrupt is an asynchronous event in which other modules such as I/O, memory may change the sequence of executions of the instruction of the CPU. Instruction cycle and implication of interrupts Instruction cycle IF ID OF IE SR IC Interrupt check break point A module may send an interrupt to the CPU by setting an interrupt flag maintained in the CPU. In the instruction cycle, the CPU recognizes the ON status of the flag (at interrupt check break point) and switches over to execution of the procedure referred to as Interrupt Service Routine (ISR). In fact, the occurrence of an interrupt triggers a number of events, both in the processor hardware and in software. Transfer of control via interrupt IT60101 Foundation of Computing Samanta 20

21 Sources and type of interrupts Interrupt handling by CPU There are usually many sources of interrupts, each setting an interrupt flag ( or interrupt register). A specific ISR is associated with each interrupt. The sources and types of various interrupts are shown below. Type Program External Source Internal interrupts Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, and reference outside a user s allowed memory space. I/O An I/O device controller may request for data transfer or it may ask for CPU s attention after it has finished data transfer. Timer Timer is a device associated with a system to keep count of some elapsed time. It is set with a specified value by the program. The timer counter gets decremented as the time advances. On elapsing of the specified time slots as the counter reaches to zero, a timer interrupt may be initiated. IT60101 Foundation of Computing Samanta 21

22 Console switch To force certain specified action. Power sensing circuit If power fails or drops below a safe operating level etc. Hardware Software Machine check The CPU is usually equipped with a register which stores hardware errors, if any. For example, parity errors in any hardware register, error executing any input/output operation. Such occurrence of machine error demands execution of certain error recovery procedure. Machine check interrupts and the associated interrupt service routines enable the system to effectively handle machine errors. A software interrupt is initiated by executing an instruction of the type INT n in a program where n refers to the starting address of a procedure. I t can be used by the programmer to initiate a desired procedure coded as the interrupt service routine at nay desired point in the program, ROM BIOS etc. Interrupt Servicing Interrupts from different sources are usually posted in a single or multiple registers. Each bit of the register records the specific condition which caused the interrupt. For each type of interrupt, there is a corresponding interrupt service routine. Interrupt service rountines are usually stored in specification locations of main memory or ROM- BIOS. The CPU checks the interrupt flag register to decide what type of interrupt it is and get the location of interrupt service routine stored in some registers (special purpose) or some mechanism. Interrupt priorities Interrupts may be also classified into two groups maskable and non-maskable. Such grouping stems from the fact that at any point of time, CPU might be executing some instructions (usually related to operating system function) which are critical and cannot be deferred. Under this situation, it is necessary to mask the interrupts. There are some interrupts such as machine check or power failures are non-maskable and referred to as non-maskable interrupt (NMI). To accomplish this, there is special register is used called mask register, which sets some bit as 1 to indicate that they are mask. Further, at any instant multiple interrupts may occur, that is, more than one source can sent interrupt signals to the CPU simultaneously. Two approaches can be taken to dealing with multiple interrupts 1) The first approach is to disable interrupts while an interrupt is being processed. A disable interrupt simply means that the processor can and will ignore that interrupt request signal. If an interrupt occurs during this time,l it generally remains pending and will be checked by the processor after the processor has enables interrupts. Thus, when a user program is executing and an interrupt occurs, IT60101 Foundation of Computing Samanta 22

23 interrupts are immediately. After the interrupt handler routine completes, interrupts are enabled before resuming the user program, and the processor checks to see if additional interrupts have occurred. However, the draw back of the approach is that it does not take into account relative priority. 2) A second approach is to define priorities for interrupts and to allow an interrupt of higher priority to cause a lower priority interrupt handler to be itself interrupted. To handle IO interrupt situation, following issues need due consideration. 1. Selection of the interrupting device 2. Priority and masking of interrupt. 3. Generation of the starting address of the interrupt service routine corresponding to the interrupt signal generated by a specific IO device. Sequence of actions executed in response to an interrupt signal. Daisy Chaining Priority Scheme In order to identify the device which has raised the interrupt, the scheme similar to that of bus arbitration logic (where multiple devices may request access to the bus may be employed. Figure below represents an IO bus structure where one of the control bus is Interrupt Request. Any IO device at any point of time can make this line active. If the interrupt is not disabled masked, the IO interrupt flip-flop is set. The CPU at the end of its current instruction execution phase, checks the interrupt flip-flop and proceeds to IT60101 Foundation of Computing Samanta 23

24 identify the IO device and the starting address of the corresponding interrupt service routine. The simplest scheme, as noted in the above Figure below, is to resolve the arbitration by daisy chaining the Interrupt Acknowledge (Int Ack) signal from CPU. As per the fixed priority enforced by the physical interconnection of the Int Ack line, the interrupting device stops propagation of this control line and puts its address on the address bus. A table may store the interrupt service routine starting address for the interrupt generated by each of the IO devices. The CPU can look into the table (that may be stored in a ROM) to identify the starting address and proceed to execute the interrupt service routine. Instead of table look up, CPU may execute a program with the device address as an input parameter to compute the starting address of the interrupt service routine. Polling Scheme Daisy chained priority scheme to identify interrupting device. Instead of employing the fixed priority set by the daisy chaining, a polling scheme can be also implemented. If the interrupt FF is set, the CPU may execute a polling routine as noted in Figure below. Each of the IO devices is assumed to store a bit in its status register indicating the interrupt request status. The polling routine interrogates the status of each device (that is, the status is read and its interrupt bit is checked) in a predetermined order to identify the interrupting device and the corresponding interrupt service routine starting address from a table. The priority of selection can be programmed by changing the polling sequence. The interrupting device that comes first in the polling order gets serviced first. In order to have faster processing of interrupt, all the actions for identifying the interrupt service routine need to be hardwired which is implemented in the next scheme. Independent Interrupt Request Instead of using single IO interrupt flip-flop noted in earlier two schemes, the CPU, as noted in Figure below, may be equipped with an interrupt register. The register may have n number of bits if there are n number of IO interrupt sources. The ith source stores its interrupt signal on the ith bit of the register. Thus the source of the interrupt is immediately known to the CPU. To service the interrupt, the CPU now computes the starting address of the service routine or identifies the address by table look up. IT60101 Foundation of Computing Samanta 24

25 In each of the above schemes, CPU spends unproductive time for identifying the starting address of the interrupt service routine. This can be avoided by a scheme referred to as vectored interrupt. Vectored Interrupt Independent interrupt request scheme. In this scheme, the interrupting device provides the CPU over the data bus with a special code called Interrupt Vector which directly represents the starting address of the corresponding interrupt service routine. Figure below shows a typical vectored interrupt scheme with daisy chain method of resolving interrupt priority. Resolving the priority IT60101 Foundation of Computing Samanta 25

26 Vectored interrupt with daisy chaining. with the help of a priority encoder fed with independent interrupt request lines is noted in Figure below. A mask register is also included in order to provide the flexibility of disabling any interrupt. The output of the priority encoder directly provides the starting address of Vectored interrupt with priority encoding. the interrupt service routine. For example, for a system with 4 IO devices let the starting address of the interrupt service routines be A(0), A(1), A(2) and A(3). Then the priority encoder output 00, 01, 10, 11 can be concatenated to generate the addresses 00, 01, 10, 11 where denotes the high order address bits. Now the corresponding interrupt service routine addresses A(i) (i = 0, 1, 2, 3) can be specified as the branch address in the memory locations as noted in Figure below. Any active input to the priority encoder generates the Interrupt Pending signal. While CPU is ready to service the interrupt, the priority encoder can be enabled to generate the starting address of interrupt service routine. In order to reduce hardware cost while handling large number of IO devices, it may be desirable to combine priority encoder scheme along with daisy chain method. The devices can be combined into priority groups and are daisy chained within each group. A IT60101 Foundation of Computing Samanta 26

27 group is selected by the priority encoder and the IO devices within a group is serviced as per the fixed priority determined by the daisy chain. A variation of the above vectored interrupt scheme can be implemented by generating a transfer vector in the form of a CPU instruction. For example, the IO device may generate the vector Call A (i) on the data bus which is transferred to instruction register of the CPU. The CPU executes this instruction as a call subroutine instruction where A(i) denotes the starting address of the subroutine which is nothing but the interrupt service routine. IT60101 Foundation of Computing Samanta 27