Dual 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER
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1 PCM1700U PCM1700P Dual Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DUAL 18-BIT LOW-POWER MONOLITHIC AUDIO D/A CONVERTER VERY LOW MAX THD+N: 92dB Without External Adjust CO-PHASE, LOW-GLITCH ±3V OR ±670µA AUDIO OUTPUTS CAPABLE OF 16X PER CHANNEL OVERSAMPLING RATE COMPLETE WITH INTERNAL REFEREE SERIAL INPUT FORMAT 100% COMPAT- IBLE WITH INDUSTRY STD PCM56P RUNS ON ±5V SUPPLIES AND DISSIPATES 300mW MAX COMPACT 28-PIN PLASTIC DIP OR SOIC DESCRIPTION The PCM1700 is a low cost, high-performance, dual 18-bit digital-to-analog converter. The PCM1700 features low glitch, co-phase current and voltage outputs and only requires ±5V supplies. The PCM1700 comes complete with an internal reference and optional MSB adjustability for even greater THD performance. Total power dissipation is less than 400mW max. Low maximum Total Harmonic Distortion + Noise ( 92dB max; PCM1700P-K) is 100% tested. The very fast PCM1700 is also capable of 16X oversampling rates on both channels simultaneously, providing freedom in output filter selection. The PCM1700 comes in space-saving 28-pin plastic DIP and SOIC packages. PCM1700 accepts a serial data input format that is compatible with other Burr- Brown PCM products such as the industry standard PCM56P. MSB Adj Left I OUT Left SJ Data Left Serial-to-Parallel Shift Register I OUT DAC V OUT Left Clock Latch Enable Control Logic Reference Data Right Serial-to-Parallel Shift Register I OUT DAC V OUT Right MSB Adj Right I OUT Right SJ International Airport Industrial Park Mailing Address: PO Box Tucson, AZ Street Address: 6730 S. Tucson Blvd. Tucson, AZ Tel: (520) Twx: Cable: BBRCORP Telex: FAX: (520) Immediate Product Info: (800) Burr-Brown Corporation PDS-1035D Printed in U.S.A. August, 1993
2 SPECIFICATIONS ELECTRICAL At 25 C, and ±V CC = ±5.00V unless otherwise noted. Where relevant, specifications apply to both left and right input/output channels. PCM1700U/U-J/U-K, PCM1700P/P-J/P-K PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 18 Bits DYNAMIC RANGE +108 db INPUT DIGITAL INPUT Logic Family TTL Compatible Logic Level: V IH +2 +V DD V V IL V I IH V IH = +2.7V +1 µa I IL V IL = +0.4V 50 µa Data Format Serial BTC (1) Input Clock Frequency MHz DYNAMIC CHARACTERISTICS TOTAL HARMONIC DISTORTION + N (6) PCM1700_: f = 991kHz (0dB) f S = 352.8kHz (4) db f = 991kHz ( 20dB) f S = 352.8kHz db f IN = 991kHz ( 60dB) f S = 352.8kHz db PCM1700_-J: f = 991kHz (0dB) f S = 352.8kHz db f = 991kHz ( 20dB) f S = 352.8kHz db f = 991kHz ( 60dB) f S = 352.8kHz db PCM1700_-K: f = 991kHz (0dB) f S = 352.8kHz db f = 991kHz ( 20dB) f S = 352.8kHz db f = 991kHz ( 60dB) f S = 352.8kHz db CHANNEL SEPARATION db SIGNAL-TO-NOISE RATIO (5) 20Hz to 20kHz at BPZ (6) +108 db TRANSFER CHARACTERISTICS ACCURACY Gain Error ±1 ±3 % Gain Mismatch Channel to Channel ±1 ±3 % Bipolar Zero Error 10 mv BPZ Error Mismatch Channel to Channel 5 mv BPZ Differential Linearity Error (7) ±1 LSB Gain Drift 100 ppm/ C Bipolar Zero Drift 20 ppm of FSR/ C Warm-up Time 1 minute POWER SUPPLY REJECTION ±V CC to V OUT +86 db ANALOG OUTPUT Voltage: Output Range ±3 V Output Impedance 0.1 Ω Current Output ±2 ma Capacitive Load Drive R LOAD = 1.5kΩ TBD pf Short Circuit Duration Indefinite Settling Time Sufficient to Meet THD+N Specs Glitch Energ Meets All THD+N Specs Without External Output Deglitching Current: Output Range (±2%) ±670 µa Output Impedance (±2%) 1.67 kω POWER SUPPLY REQUIREMENTS ±V CC Supply Voltage V Supply Current: +I CC +V CC = +5.0V ma I CC V CC = 5.0V ma Power Dissipation ±V CC = ±5.0V mw TEMPERATURE RANGE Specification C Operating C Storage C NOTES: (1) Binary Two s Complement coding. (6) Ratio of (Distortion RMS + Noise RMS ) / Signal RMS. (3) D/A converter input frequency/signal level on both left and right channels. (4) D/A converter sample frequency (8 X 44.1kHz; 8X oversampling per channel). (5) Ratio of Noise RMS / Signal RMS. Measured using an A-weighted filter. (6) Bipolar zero. (7) Differential non-linearity at bipolar major carry input code. Measured in 16-bit LSBs. Adjustable to zero error. PCM1700 2
3 PIN ASSIGNMENTS (Plastic PKG) PIN DESCRIPTION MNEMONIC 1 5V Analog Supply V CC 2 Left Channel Servo-Amp Decoupling Point CAP 3 Left Channel MSB Adjustment MSB ADJ (L) 4 No Connect 5 Left Channel Bipolar Offset Decoupling Point CAP 6 Left Channel Current Output IOUT (L) 7 Left Channel Analog Common ACOM 8 Left Channel Summing Junction SJ (L) 9 Left Channel Voltage Output VOUT (L) 10 No Connect 11 +5V Digital Supply +V DD 12 Left Channel Data Input DATA 13 Clock Input CLOCK 14 5V Logic Supply V DD 15 Latch Enable Input LE 16 Right Channel Data Input DATA (R) 17 Digital Common DCOM 18 No Connect 19 Right Channel Voltage Output VOUT (R) 20 Right Channel Summing Junction SJ (R) 21 Right Channel Analog Common ACOM 22 Right Channel Current Output IOUT (R) 23 Right Channel Bipolar Offset Decoupling Point CAP 24 Right Channel MSB Adjustment MSB ADJ (R) 25 Right Channel Servo-Amp Decoupling Point CAP 26 MSB Adjustment Potentiometer Voltage Output VPOT 27 +5V Analog Supply +V CC 28 Digital Common DCOM ORDERING INFORMATION Basic Model Number P: Plastic U: SOIC Performance Grade Code ABSOLUTE MAXIMUM RATINGS PCM1700 DC Supply Voltages... ±7.5VDC Input Logic Voltage... 1V to +V CC Power Dissipation mW Operating Temperature C to +70 C Storage Temperature C to +100 C Lead Temperature (soldering, 10s) C ( ) ( ) PIN ASSIGNMENTS (SOIC PKG) PIN DESCRIPTION MNEMONIC 9 5V Analog Supply V CC 10 Left Channel Servo-Amp Decoupling Point CAP 11 Left Channel MSB Adjustment MSB ADJ (L) 19 No Connect 12 Left Channel Bipolar Offset Decoupling Point CAP 13 Left Channel Current Output I OUT (L) 14 Left Channel Analog Common ACOM 15 Left Channel Summing Junction SJ (L) 16 Left Channel Voltage Output V OUT (L) 17 No Connect 18 +5V Digital Supply +V DD 20 Left Channel Data Input DATA 21 Clock Input CLOCK 22 5V Logic Supply V DD 23 Latch Enable Input LE 24 Right Channel Data Input DATA (R) 25 Digital Common DCOM 26 No Connect 27 Right Channel Voltage Output V OUT (R) 28 Right Channel Summing Junction SJ (R) 1 Right Channel Analog Common ACOM 2 Right Channel Current Output I OUT (R) 3 Right Channel Bipolar Offset Decoupling Point CAP 4 Right Channel MSB Adjustment MSB ADJ (R) 5 Right Channel Servo-Amp Decoupling Point CAP 6 MSB Adjustment Potentiometer Voltage Output V POT 7 +5V Analog Supply +V DD 8 Digital Common DCOM NOTE: In the SOIC (PCM1700U) package, the die is rotated 90. Therefore, the pin assignments are different from the DIP. See pin assignments on page 4 for details. PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER (1) PCM1700U 28-Pin SOIC 217 PCM1700U-J 28-Pin SOIC 217 PCM1700U-K 28-Pin SOIC 217 PCM1700P 28-Pin Plastic DIP 126 PCM1700P-J 28-Pin Plastic DIP 126 PCM1700P-K 28-Pin Plastic DIP 126 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. 3 PCM1700
4 Data Input Clock In Latch Enable > 25ns LSB > 15ns > 15ns > 25ns > 25ns > 60ns > 5ns > 15ns MSB > One Clock Cycle > One Clock Cycle DIGITAL INPUT ANALOG OUTPUT Binary Two s Voltage (V) Current (ma) Complement (BTC) DAC Output V OUT Mode I OUT Mode 1FFFF Hex + FS Hex BPZ FFFF Hex BPZ 1LSB Hex FS TABLE I. PCM1700 Input/Output Relationships. FIGURE 1. PCM1700P Setup and Hold Timing Diagram. P13 (Clock) P12 Data (L) P16 Data (R) P15 (Latch Enable) MSB LSB MSB LSB FIGURE 2. Timing Diagram. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PCM1700 4
5 +5V 10µF µF 5V 10µF V CC DCOM CAP +V CC MSB Adj (Left) VPOT CAP CAP MSB Adj (Right) IOUT (Left) CAP µF Optional Bit Adjust Circuit 7 ACOM (Left) IOUT (Right) 22 8 SJ (Left) ACOM (Right) 21 9 VOUT (Left) SJ (Right) VOUT (Right) V DD DATA (Left) DCOM Clock DATA (Right) VDD LE 15 FIGURE 3. Voltage Output Connection Diagram (DIP Package Diagram.) +5V 10µF µF 5V 1 V CC DCOM 28 10µF 2 CAP +V 27 + CC 3 MSB Adj (Left) VPOT 26 (1) 4.5kΩ 4 CAP 25 Optional Bit 5 CAP MSB Adj (Right) µF Adjust Circuit V OUT (R) 6 IOUT (Left) CAP kΩ (1) 7 8 ACOM (Left) SJ (Left) IOUT (Right) ACOM (Right) V OUT (L) 1.22kΩ (1) BB OPA602BP VOUT (Left) +V DD SJ (Right) VOUT (Right) kΩ (1) BB OPA602BP 0.47µF 12 DATA (Left) DCOM Clock VDD DATA (Right) LE NOTES: (1) Low TCR resistors such as Vishay. FIGURE 4. Current Output Connection Diagram (DIP Package Diagram.) 5 PCM1700
6 This datasheet has been download from: Datasheets for electronics components.
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TS34119 Low Power Audio Amplifier
SOP-8 DIP-8 Pin assignment: 1. CD 8. VO2 2. FC2 7. Gnd 3. FC1 6. Vcc 4. Vin 5. VO1 General Description The TS34119 is a low power audio amplifier, it integrated circuit intended (primarily) for telephone
DM74LS157 DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers
September 1986 Revised April 2000 DM74LS157 DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers General Description These data selectors/multiplexers contain inverters and drivers to supply full
CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
MC33079. Low noise quad operational amplifier. Features. Description
Low noise quad operational amplifier Datasheet production data Features Low voltage noise: 4.5 nv/ Hz High gain bandwidth product: 15 MHz High slew rate: 7 V/µs Low distortion: 0.002% Large output voltage
LF412 Low Offset Low Drift Dual JFET Input Operational Amplifier
LF412 Low Offset Low Drift Dual JFET Input Operational Amplifier General Description These devices are low cost high speed JFET input operational amplifiers with very low input offset voltage and guaranteed
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features
DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
DAC1401D125. Dual 14-bit DAC, up to 125 Msps. The DAC1401D125 is pin compatible with the AD9767, DAC2904 and DAC5672.
Rev. 03 2 July 2012 Product data sheet 1. General description The is a dual port, high-speed, 2-channel CMOS Digital-to-Analog Converter (DAC), optimized for high dynamic performance with low power dissipation.
FEATURES DESCRIPTIO APPLICATIO S. LTC1451 LTC1452/LTC1453 12-Bit Rail-to-Rail Micropower DACs in SO-8 TYPICAL APPLICATIO
12-Bit Rail-to-Rail Micropower DACs in SO-8 FEATRES 12-Bit Resolution Buffered True Rail-to-Rail Voltage Output 3V Operation (LTC1453), I CC : 250µA Typ 5V Operation (), I CC : 400µA Typ 3V to 5V Operation
TDA2040. 20W Hi-Fi AUDIO POWER AMPLIFIER
20W Hi-Fi AUDIO POWER AMPLIFIER DESCRIPTION The TDA2040 is a monolithic integrated circuit in Pentawatt package, intended for use as an audio class AB amplifier. Typically it provides 22W output power
HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION
BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION QUIESCENT CURRENT SPECIF. UP TO 20V OPERATION OF LIQUID CRYSTALS WITH CMOS CIRCUITS PROVIDES ULTRA LOW POWER DISPLAY. EQUIVALENT AC OUTPUT DRIVE
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-
DATA SHEET. TDA1510AQ 24 W BTL or 2 x 12 W stereo car radio power amplifier INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET 24 W BTL or 2 x 12 W stereo car radio File under Integrated Circuits, IC01 January 1992 GENERAL DESCRIPTION The is a class-b integrated output amplifier encapsulated in a
Model AD558J AD558K AD558S 1 AD558T 1 Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
SPECIFICATIONS (@ T A = +25 C, V CC = +5 V to + V unless otherwise noted) Model J K S 1 T 1 Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION Bits RELATIVE ACCURACY 2 0 C to +70 C ±1/2 ±1/4
DS2187 Receive Line Interface
Receive Line Interface www.dalsemi.com FEATURES Line interface for T1 (1.544 MHz) and CEPT (2.048 MHz) primary rate networks Extracts clock and data from twisted pair or coax Meets requirements of PUB
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated
LM4992 420mW Stereo Cell Phone Audio Amplifier
420mW Stereo Cell Phone Audio Amplifier General Description The is a stereo audio power amplifier primarily designed for demanding applications in mobile phones and other portable communication device
PAM8403. Description. Pin Assignments. Features. Applications. Typical Applications Circuit. A Product Line of. Diodes Incorporated
FILTERLESS 3W CLASS-D STEREO AUDIO AMPLIFIER Description Pin Assignments The is a 3W, class-d audio amplifier. It offers low THD+N, allowing it to achieve high-quality sound reproduction. The new filterless
MUSES8920. High Quality Audio J-FET Input Dual Operational Amplifier - 1 -
MUSES89 High Quality Audio J-FET Input Dual Operational Amplifier GENERAL DESCRIPTION The MUSES89 is a high quality Audio J-FET input dual operational amplifier. This is a mass production model of MUSES
TL082 Wide Bandwidth Dual JFET Input Operational Amplifier
TL082 Wide Bandwidth Dual JFET Input Operational Amplifier General Description These devices are low cost high speed dual JFET input operational amplifiers with an internally trimmed input offset voltage
12-Bit Serial Daisy-Chain CMOS D/A Converter DAC8143
a FEATURES Fast, Flexible, Microprocessor Interfacing in Serially Controlled Systems Buffered Digital Output Pin for Daisy-Chaining Multiple DACs Minimizes Address-Decoding in Multiple DAC Systems Three-Wire
Features. Note Switches shown in digital high state
DAC1020 DAC1021 DAC1022 10-Bit Binary Multiplying D A Converter DAC1220 DAC1222 12-Bit Binary Multiplying D A Converter General Description The DAC1020 and the DAC1220 are respectively 10 and 12-bit binary
DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
TS321 Low Power Single Operational Amplifier
SOT-25 Pin Definition: 1. Input + 2. Ground 3. Input - 4. Output 5. Vcc General Description The TS321 brings performance and economy to low power systems. With high unity gain frequency and a guaranteed
AUDIO BALANCED LINE DRIVERS
DRV DRV DRV DRV DRV AUDIO BALAED LINE DRIVERS FEATURES BALAED OUTPUT LOW DISTORTION:.% at f = khz WIDE OUTPUT SWING: Vrms into Ω HIGH CAPACITIVE LOAD DRIVE HIGH SLEW RATE: V/µs WIDE SUPPLY RANGE: ±.V to
X9C102/103/104/503. Terminal Voltages ±5V, 100 Taps. Digitally-Controlled (XDCP) Potentiometer
APPLICATION NOTE A V A I L A B L E AN20 AN42 53 AN71 AN73 AN88 AN91 92 AN115 Terminal Voltages ±5V, 100 Taps X9C102/103/104/503 Digitally-Controlled (XDCP) Potentiometer FEATURES Solid-State Potentiometer
DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control
August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation
LM134-LM234-LM334. Three terminal adjustable current sources. Features. Description
Three terminal adjustable current sources Features Operates from 1V to 40V 0.02%/V current regulation Programmable from 1µA to 10mA ±3% initial accuracy Description The LM134/LM234/LM334 are 3-terminal
Features INSTRUCTION DECODER CONTROL LOGIC AND CLOCK GENERATORS COMPARATOR AND WRITE ENABLE EEPROM ARRAY READ/WRITE AMPS 16
July 2000 FM9346 (MICROWIRE Bus Interface) 1024- Serial EEPROM General Description FM9346 is a 1024-bit CMOS non-volatile EEPROM organized as 64 x 16-bit array. This device features MICROWIRE interface
DS1307ZN. 64 x 8 Serial Real-Time Clock
DS137 64 x 8 Serial Real-Time Clock www.maxim-ic.com FEATURES Real-time clock (RTC) counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap-year compensation valid
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 956 24-BIT DIFFERENTIAL ADC WITH I2C LTC2485 DESCRIPTION
LTC2485 DESCRIPTION Demonstration circuit 956 features the LTC2485, a 24-Bit high performance Σ analog-to-digital converter (ADC). The LTC2485 features 2ppm linearity, 0.5µV offset, and 600nV RMS noise.
PS25202 EPIC Ultra High Impedance ECG Sensor Advance Information
EPIC Ultra High Impedance ECG Sensor Advance Information Data Sheet 291498 issue 2 FEATURES Ultra high input resistance, typically 20GΩ. Dry-contact capacitive coupling. Input capacitance as low as 15pF.