Imager Process Review

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1 OmniVision OV Mp, 1.4 µm Pixel Pitch RGB Clear (RGBC) Color Filter Back Illuminated (BSI) CMOS Image Sensor from the Motorola Moto X Smartphone Imager Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

2 Imager Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. ipr DYLR Revision 1.0 Published: November 14, 2013

3 Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 OmniVision BSI Comparison 1.6 Device Summary 1.7 Process Summary 2 Device Overview 2.1 Downstream Product 2.2 Camera Module Package 2.3 Die Overview 2.4 Pixel Array Overview 2.5 Bond Pads 2.6 Standard Logic Cell 3 Process Analysis 3.1 Overview 3.2 General Device Structure 3.3 Image Sensor Substrate and Wells 3.4 Image Sensor Substrate Isolation 3.5 Peripheral Transistors and Poly 3.6 Front Dielectrics 3.7 Front Metallization 3.8 Vias and Contacts 3.9 Wafer Bonding and Carrier Wafer 3.10 Back of Die Processing (Dielectrics and Metals) 3.11 Bond Pads 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan-View Analysis 4.3 Pixel Cross-Sectional Analysis Parallel to Transfer Lines 4.4 Pixel Cross-Sectional Analysis Parallel to Column Out Line

4 Imager Process Review 5 Memory Cell Analysis 5.1 6T SRAM Plan-View Analysis 6 Critical Dimensions 6.1 Image Sensor Substrate and Wells 6.2 Image Sensor Substrate Isolation 6.3 Peripheral Transistors and Poly 6.4 Front Dielectrics 6.5 Front Metallization 6.6 Vias and Contacts 6.7 Back of Die Processing (Dielectrics and Metals) 6.8 Pixel Horizontal and Vertical Directions 7 References 8 Statement of Measurement Uncertainty and Scope Variation About Chipworks

5 Overview Overview 1.1 List of Figures 2 Device Overview Motorola Smartphone Front Motorola Smartphone Back Camera Module Mounted on the Smartphone Circuit Board Smartphone PCB with Mounted Camera Module Camera Module Front View Camera Module Back View Camera Module Side View Camera Module Planar Package X-Ray Camera Module X-Ray Side View A Camera Module X-Ray Side View B Camera Module X-Ray Close-Up Side View B Die Photograph Color Filters and Lenses Intact Die Photograph Width Dimension Measurements Back Die Photograph Color Filters and Lenses Removed Die Markings Annotated Polysilicon Die Photograph Analysis Sites Die Corner A Detail Die Corner B Detail Die Corner C Detail Die Corner D Detail Die Corner SEM Tilt View Active Pixel Array Corner Top Left Active Pixel Array Corner Bottom Right Active Pixel Array Corner Bottom Left Detailed View of Active Pixel Array Corner Top Left Detailed View of Active Pixel Array Corner Top Right Detailed View of Active Pixel Array Corner Bottom Right Detailed View of Active Pixel Array Corner Bottom Left SEM Tilt View of Active Pixel Array Corner Bottom Left SEM Image of Active Pixel Array Corner Tilt View Color Filter Array Pixel Pitch Minimum Pitch Bond Pads Bond Pad Die Bond Pad with Au Ball Bond Attached Tilt View Overview of Logic Circuitry Details of a Standard Logic Cell

6 Overview Process Analysis Die Thickness Die Edge Outer Die Seal General Structure Periphery General Structure Pixel Array SCM of Peripheral Logic N-Well and P-Well Periphery N-Well and P-Well Silicon Etch Overview SCM of Pixel Array SIMS Analysis Sites SIMS of Periphery SIMS of Pixel Array STI Partially Covered by Poly SEM STI Partially Covered by Poly SEM STI at Pixel Array SEM STI at the Transition from Pixel Array to Periphery SEM Logic MOS Transistor Overview Glass Etch NMOS Logic Transistors Si Etch SEM NMOS Logic Transistors Si Etch SEM PMOS Logic Transistors Si Etch SEM TEM of Logic Transistor TEM of Logic Gate Dielectric Edge of MOS Capacitor Gate TEM MOS Capacitor Gate Dielectric Lattice TEM Interlayer Dielectrics SEM TEM of PMD at Pixel Array TEM of PMD at Periphery TEM of ILD 2 and ILD Passivation Metal 1 Cross Section TEM Minimum Pitch Metal Minimum Pitch Metal TEM of Metal 3 Cross Section Metal 4 TEM Cross Section Minimum Observed Metal 4 Pitch SEM Minimum Pitch Contacts TEM of Contact to Substrate in Periphery Logic TEM of Bottom of Contact to Unsilicided Poly Gate in Pixel Array Minimum Width Via 1s SEM Minimum Pitch Via 1s and Via 2s SEM TEM of Via Minimum Pitch Via 3s and Via 2s SEM Detail of Wafer Bond Interface Back Dielectrics and Metals in Periphery SEM Overview Back Dielectrics and Metals in Periphery SEM Detail

7 Overview Light Shield Contact to Substrate SEM Edge of Light Shield Contact to Substrate General View of Backside Layers Over Pixel Array TEM TEM of Metal Grid, BPMD, and BILD TEM of Pixel Back Passivation on Microlenses Gold Ball Bond Overview Edge of Bond Pad Window SEM Edge of the Bond Pad Bond Pad Via Cross Section Bond Pad Via Edge 4 Pixel Analysis Circuit Schematic of Four Pixels Pixels at Metal 4 SEM Pixels at Metal 3 SEM Pixels at Via 2 SEM Pixels at Metal 2 SEM Pixels at Via 1 SEM Pixels at Metal 1 SEM Overlaid Colorized Image of Pixels at Metal 2 over Metal 1 Level Pixel Array at Poly Level SEM Overlaid Colorized Image of Pixel at Metal 1 over Poly Pixels at Diffusion Level SEM Overlaid Colorized Image of Pixel at Poly over Diffusion SCM of the Bevel Sample of the Pixel Array Metal Grid over Pixel Array Photodiode - SEM Planar View Periphery to Active Pixel Transition Overview Edge Pixels Microlens Shift Pixel Array Cross Section Across Transfer Gate SEM TEM of Transfer Gate Along the XFER Gate Contact TEM of Left Edge of Transfer Gate Pixel Transistor Gate Oxide Lattice TEM Row Select and Source Follower Transistors SEM Si-Etch Stained SEM Image of Source Follower and the Row Select Transistors Reset Transistor SEM Si-Etch Stained SEM Image of the FD Clear Color Filter and Microlens TEM Green Color Filter TEM Red or Blue Color Filter TEM Radius of Curvature of Microlens Under Clear Color Filter Dark Pixel Overview Dark Pixels To Active Pixels Transition

8 Overview Microlens Shift at the Bottom Edge of Pixel Array SEM Pixel Array Cross Section Parallel to Column Out Bus Lines Pixel Array Cross Section in Column Out Direction Close to the Center of the Pixels SCM of Pixel Cross Section Reset Transistor Gate Width Source Follower Transistor Gate Width Row Select Transistor Gate Width 5 Memory Cell Analysis T SRAM Layout at the Diffusion Level 1.2 List of Tables 1 Overview Device Identification OmniVision BSI Technology Comparison OV10820 Device Summary OV10820 Process Summary 2 Device Overview Die Sections Dimensions 3 Process Analysis Substrate and Well Vertical Dimensions STI Critical Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Measured Dielectric Thicknesses Front Metallization Thicknesses Front Metallization Width and Pitch Via and Contact Dimensions Back Dielectric and Metal Vertical Dimensions 6 Critical Dimensions Substrate and Well Vertical Dimensions STI Critical Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Measured Dielectric Thicknesses Front Metallization Thicknesses Front Metallization Width and Pitch Via and Contact Dimensions Back Dielectric and Metal Vertical Dimensions Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions

9 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

InvenSense MPU-6515 6-Axis Accelerometer Gyroscope MEMS Motion Sensor

InvenSense MPU-6515 6-Axis Accelerometer Gyroscope MEMS Motion Sensor 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com Some of the information in this report