Prototyping with ARM Cortex-M1 to Increase Software Development Productivity. Angela Sutton Synplicity

Transcription

1 Prototyping with ARM Cortex-M1 to Increase Software Development Productivity Angela Sutton Synplicity

2 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed

3 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed

4 Software is on the project critical path 70% 60% 50% 40% 30% 20% Early access to a hardware platform to develop and verify the software is vital Hardware Simulation times are exploding Hardware and software must be validated together % Software Engineers 10% 0% 130nm 90nm 65nm 45nm Source: Gary Smith EDA People are turning to FPGAs to prototype the System so that software development and test can begin earlier

5 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed

6 FPGA 101 Multi-purpose chip customized by programming Logic, dedicated memory resources and additional resources for performing fast DSP operations Can embed microprocessor and system bus implementation on the chip How FPGAs differ from ASICs: Faster turnaround time: synthesis+p&r->program chip Debug on the board right away Capacity -- Multimillion ASIC equivalent gates per chip, yet less than the largest ASICs on the market You may wish to partition your ASIC prototype across multiple FPGAs or implement just a critical portion of your design Power Consume much more power than ASICs Architecturally different building blocks Need FPGA-specific Synthesis & verification tools

7 FPGA Synthesis Synplify Pro Fast Compile Times High Capacity Best Fmax & Area Results Ease Of Learning & Use Graphical & Batch Modes Static Timing Analysis Debug And Analysis Tools THE Standard For Agilent, NXP, Sony, Siemens & Many Others > 70% EDA synthesis market share

8 Basic FPGA Design Flow P&R constraints Synplify DSP RTL Synthesis Synplify Pro Logic Synthesis Gate -level Netlist FPGA Vendor Place & Route.v.vhd Compiler.srs Mapper*.srm Libero Libero Technology-Independent RTL Netlist.SDC FPGA-Specific Technology Netlist Quartus Synthesis util.edn.tcl.vqm.ncf.edf ISE ISE Synopsys.sdc.SCF Vendor s own P&R * Separate Mapper for each FPGA family

9 FPGA Flow compared with ASIC Flow.v.vhd Simple Synopsys flow Analyze Elaborate Uniquify Compile Compiler.srs Mapper.srm Technology-Independent RTL Netlist FPGA-Specific Gate-level Netlist.SDC.SCF.sdc..edn.tcl.vqm.ncf.edf Libero Libero Quartus ISE ISE ASIC P&R FPGA P&R

10 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed

11 ARM Cortex-M1 FPGA Core Synthesizable Soft core Designed using Synplify Pro 2 year ARM-Synplicity collaborative effort Can now prototype ASIC Cortex-M3 processor designs in FPGAs using Synplify Pro Cortex-M1 Software compatible with ARM s ASIC Cortex-M3 core Earlier system software development and test Provides headstart on system software development

12 Cortex Embedded Solutions FPGA (Cortex-M1) ASIC (Cortex-M3)

13 The Cortex-M1 Reference flow Scripts and constraints for running Synplify Pro on M1 RTL Useful to ensure completeness The way many ASIC users expect to work Cortex-M1 built into Synplicity in-house regression test Ensuring success for mutual Synplicity and ARM users Working on improving flow for project/gui-based users The way many FPGA users expect to work Cortex-M1 is designed for use in Production FPGA Designs as well

14 FPGA-Optimized Core increases Fmax ARM s CortexM3 is designed for ASIC Moving RTL directly into FPGA yields a performance of around 25MHz CortexM1 is an ARM core optimised for FPGA Runs at over 200MHz in Virtex 5 Approx 8x faster than simply synthesizing ASIC RTL CortexM1 substitute CortexM3 Instance (may be Black Box) CortexM3 Instance in Design Wrapper logic

15 Compromises in Substituting M1 for M3 The M1 has a subset of the M3 instructions Carefully chosen so as to not reduce performance M1 does not have the same tightly-coupled-memory as M3 Design may not be able to use M3 s tightly-coupled memory Use external memory via AMBA (to match the top-level core pin out). Performance impact of doing this is 2x (200MHz reduces to 100MHz ) Contact ARM for performance estimates when choosing target FPGA The M1 software debug visibility is less than for M3 This will improve as tools catch up M3 design should have 32 exception/interrupts or less Probably not a limit for most M3 designs M1 cannot support multiprocessor usage Probably not a limit for most M3 designs

16 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed

17 Prototyping Issues Addressed By Synplicity Solutions 1) ASICs are BIGGER and FASTER than FPGAs 2) ASIC Designs are not FPGA-friendly 3) Running software at speed Portability and Targeting Issues Mapping ASIC gate level netlists ASIC cell instantiations DesignWare use IP block use Conversion of ASIC RAM Gated and Generated Clocks Performance and Debug Issues Difficult to create custom prototype boards ASIC Design not optimized for FPGA Sub-optimal DSP Implementation Multi-FPGA partition limits performance FPGA debug obstacles A lot of Synplicity s business comes from prototype designs

18 Prototyping Solutions with RTL RTL rewrites not required DesignWare Support Automatic Gated Clock conversion ASIC-style constraints SDC compatibility, including Timing exceptions Constraints checker FIND for advanced constraint application and analysis Scriptable (TCL) Single & multi-chip flows Fast Board Debug Turn around Incremental flows Visibility into internal signals ARM-specific HAPS board solution RTL Synplify Pro Synplify Premier FPGA Synthesis Single chip FPGA Place & Route Certify Automatic Partitioning & FPGA Synthesis HAPS RTL & constraints Multi chip ASIC flow

19 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed Verification on the board using HAPS

20 Prototyping without RTL: Mapping ASIC netlists 2 possible solutions: Translation of ASIC cells to equivalent FPGA cells Recreate RTL and re-synthesise for FPGA. Library issues Translation Cell equivalence is FPGA specific Recreate RTL Need RTL equivalent for each ASIC cell QoR depends on.. Library correlation Synthesis QoR Expected QoR Low Better

21 Mapping ASIC Netlists: lib2syn Automatic Library translation Recognizes instantiations of components from.lib files during compile Translator reads.lib file and generates RTL equivalent Automatically includes RTL translated components in Synplify project file DFFRPQL CK D Q RB state_reg\[5\] [5] [4] [5] NAN4M1DL A1 A2 Z A3 A4 next_state70_z NAN2M1DL A1 Z A2 un1_next_state7_2_0 NAN2DL A1 Z A2 un1_next_state70 Cells RTL

22 Mapping ASIC Netlists: (gtech translation) GTECH_FD1_5 [3] GTECH_AO22 [3] A GTECH_FD1 B [3] ZFDRE D Q CU31.un1_Z [3] D CP D[0] Q[0] D INV QN C.Q U31.Z Q addr_reg_reg\[3\].q I O U31 R CE un1_reg_cmd_i[3] Q [3] GTECH_AO22 [0] A GTECH_FD1 B [0] Z D Q CU31.un2_Z CP QN D [0] addr_reg_reg\[3\] U28 addr_reg_reg\[0\].q GTECH_FD1_2 3] [3] [3] [0] GTECH_AND_NOT FDRE A D Z BU28.un1_Z C U28.Z Q R U43 CE 0] [0] D[0] Q[0] [0] U28.un2_Z Q addr_reg_reg\[0\] INV addr_reg_reg\[0\].q I O un1_reg_cmd_i[0] U43.Z [0] Some sub-designs are available only as a netlist of generic gates. So there is no.lib available Use gtech.v library which is available within all Synplicity synthesis tools // // // // Title // : gtech.v // Design // Title : gtech.v GTECH // Author // Design : Harish : GTECH M K // Company // Author : Harish Synplicity M K Software Pvt. Ltd. // // Company : Synplicity Software Pvt. Ltd. // // // // // Description // : This generic technology library contains common logic elements. // // Description : This generic technology library contains common logic elements. // // `timescale // ns / 10ps `timescale 1ns / 10ps module GTECH_NOT ( A, Z ); module GTECH_NOT ( input A, Z ); A; output input Z; A; assign output Z Z; = ~A; endmodule assign Z = ~A; endmodule module GTECH_BUF ( A, Z ); module GTECH_BUF ( input A, Z ); A; output input Z; A; assign output Z Z; = A; endmodule assign Z = A; endmodule

23 Generic model for Internal RAMs Add one RTL file into design project for each RAM cell RAM inferred from generic RTL behaviour RTL Behaviour is its own model for simulation. FPGA Synthesis maps RAM into chosen FPGA resources Try different RAMs without changing RTL Does NOT require FPGA-specific RAM instantiations Allows Synthesis to infer correct RAM implementation in in target FPGA

24 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed

25 Multi-FPGA Partitioning With Certify Load ASIC RTL Code Into Certify Code conversion Partition Into Multiple FPGAs Automatic & Interactive I/O sharing Synthesize Each FPGA Onto Board Parallel Synthesis High-Performance Prototype ASIC RTL Compile and Convert Automatic Gated-Clock conversion Automatic DW &.lib to RTL Partition Automated and Manual Partitioning Synthesize FPGAs HAPS Or Board file supplied by board vendor Board Library Supports your board or off the shelf boards

26 The Confirma Platform For ASIC and ASSP Verification RTL Identify Pro RTL Instrumentor Synthesis Certify Partition-Driven Synthesis Synplify Premier Physical Synthesis FPGA Implementation Identify Pro RTL Debugger Replay in RTL Simulator Multi- FPGA HAPS Prototypes Single-FPGA HAPS Prototypes

27 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed

28 Configurable debug boards HAPS (Confirma) System Verification Single point for hardware and software support Single & Multi-chip solutions Lego-Like Configurability Adaptable to a changing design Re-use for multiple projects Over 30 daughter boards High Performance Better than custom boards High-Performance ASIC Prototyping System Copyright 2005 Synplicity, Inc.

29 Interface between HAPS and ARM Coretile CTI_2x2 ARM Core Tile Interface (Versatile family) Compatible with... CT7TDMI, CT7TDMI-S, CT926EJ-S, CT1136JF-S, CT1156T2F-S, CT11MPCore and more Allows ARM Peripherals to be implemented using HAPS Includes Debug and configuration headers for programming the ARM tile JTAG debug interface for the ARM RealView Multi-ICE cable CLK_GLOBAL and CLK_DN_THRU available in micro coax connectors 10 GPIO signals Programmable clock generator CTI_2x2 + CT926EJ-S

30 HAPS-34 + CTI_2x2 + CT926EJ-S ARM CT926EJ-S (daughtercard) CTI_2x2 (Interface) HAPS-34 Motherboard

31 Introducing Identify Pro with TotalRecall Technology TotalRecall Technology Verification at FPGA hardware/prototype speed Debug using familiar standard simulation environment Full visibility into the design under test Automatic test bench generation for debug at the RTL source level Enhances Existing Verification Tools & Methods Use assertions to define complex trigger conditions Can Analyse and debug design when trigger condition achieved Use standard simulator Find bugs in realtime by capturing full design state before problem event Use standard simulation environment to debug Verify changes in live running FPGA hardware

32 Identify Pro with TotalRecall technology Captures/Replays Design State And Test Bench Debug design when assertion triggered Full Visibility Replay sequence leading up to trigger over again in standard Simulator Finds Sporadic Problems That appear inconsistently Live Stimulus Design Trigger FPGA That are hard to reproduce That are dependent upon initial condition & stimulus Explore how issue could have been avoided Stimulus Buffer Testbench Replicated Design RTL Simulator Initial State Copyright 2005 Synplicity, Inc.

33 Agenda Growing software content of SoC FPGA Background Cortex M1 background Optimizing for Performance ARM Reference Methodology Implementing the Prototype With RTL Without RTL Partitioning if you need it Build and debug your Prototype Running Software at Speed

34 When are FPGA Prototypes used? SW Driver Test Architecture Exploration Block Verification Module Verification Chip Verification SW & System Integration RTL Relative Relative usage usage of of Simulation Simulation Relative Relative usage usage of of Emulation Emulation RTL Relative Relative usage usage of of Prototyping Prototyping

35 No substitute to running Software at speed Running At-Speed is the ideal scenario Up to 200MHz clock speed on the FPGA is possible Running near-speed is still a benefit Boot sequence modeled in moments, not in days Real World physical effect on/of Software can be explored Running at less than 1 MHz (e.g. on Emulator) is not helpful At-Speed software is most valuable late in the project Inter-operation of code previously modeled in isolation Last chance to catch hardware/software dependency before tape-out Last chance to catch major problems before customer acceptance

36 Summary Cortex M1 can be used to develop ASIC prototypes using FPGAs with speeds up to 200MHz Reference methodologies using Synplify, and Certify help you achieve FPGA performance Confirma off the shelf hardware platform with ARM daughter card enables you to run software at speed and debug your system on the board

37 For more info Synplicity: Booth 509 Product Marketing Angela Sutton based in Sunnyvale, CA, USA Product information and Synplicity Field offices tml

38 Thank You