Outline. Introduction to Computer Science. Outline. Computer Architecture. Dr. Lonnie Cheney. Data Manipulation

Transcription

1 Outline Introduction to Computer Science Data Manipulation Dr. Lonnie Cheney Computer Architecture Machine Language Program Execution Arithmetic/Logic Instructions Communication with other Devices Other Architectures Slide 2 Outline Computer Architecture Computer Architecture Machine Language Program Execution Arithmetic/Logic Instructions Communication with other Devices Other Architectures Slide 3 Slide 4 1

2 von Neumann Architecture Registers data and instructions kept in memory CPU fetches and executes instructions CPU connected to memory via data and address bus one instruction executed at a time special processor memory for temporary storage of results very fast access time compared to primary memory example: add two numbers from memory one register holds first number another holds second number third holds the answer special registers: program counter, instruction Slide 5 Slide 6 Outline Computer Architecture Machine Language Program Execution Arithmetic/Logic Instructions Communication with other Devices Other Architectures Machine Instructions CPU has several circuits which perform different functions identify each function (command, instruction) with a unique bit pattern, just as ASCII code represents each character with a unique bit pattern types of instructions: data transfer arithmetic/logic control/branching Slide 7 Slide 8 2

3 Data Transfer Load vs. Store copy data from memory to registers or vice versa STORE copy data from input devices to memory transfer is described relative to CPU LOAD means copy from memory to register STORE means copy from register to memory LOAD Slide 9 Slide 10 Arithmetic/Logic Control/branching add, subtract, multiply, divide AND, OR, exclusive or (XOR) shift, rotate instructions are executed in sequence: fetch first instruction, execute it. fetch second instruction, execute it. fetch third instruction, execute it... and so on finally, stop execution. instructions, which modify this sequence are control instructions stop is a control instruction jump or branch to another instruction (go to) Slide 11 Slide 12 3

4 Example of control flow How it works inside the PC sample program to add two numbers 1. load register one with first number from memory 2. load register two with second number from memory 3. add contents of registers one and two, leave answer in register 3 4. if contents of register 3 are negative, jump to step 6 5. store contents of register 3 to a location in memory 6. stop identify the data transfer, arithmetic/logic, and control instructions above CPU MEMORY load R1 from M7 load R2 from M8 add R1, R2 R3 if neg jmp M6 store R3 to M9 stop Slide 13 Slide 14 Stored program... Opcodes & Operands instructions can be represented by bit patterns bit patterns can be stored in memory instead of building in programs in CPU, store programs in memory CPU then interprets patterns as instructions or data opcode: bit pattern representing instruction operand: bit pattern representing object of instruction example: LOAD REG1 ADDR instruction = load, objects of instruction = reg1 and addr complete instruction = opcode and operand Slide 15 Slide 16 4

5 Opcode examples CISC vs. RISC the LOAD instruction has opcode 0001 (appendix C) computer will load a specified register with contents of some memory location need to indicate which register to load, and what memory location to access use more bits after the 0001 to indicate this info CISC: Complex Instruction Set Computer many powerful instructions, ex: expon, sqrt more CPU silicon devoted to instruction circuits programs are shorter RISC: Reduced Instruction Set Computer few simple instructions, ex: add, mov more registers on CPU, rather than instruction circuits programs are longer Slide 17 Slide 18 A simple machine Architecture of simple machine CPU has 16 registers, each 8 bit wide registers identified as 0 to F memory has 256 cells (words), each 8 bits wide memory address ranges from 00 to FF each instruction is 16 bits (two words) with first 4 bits the opcode and remaining 12 the operand Slide 19 Slide 20 5

6 LOAD example What does it mean? load register 0 with the contents of address A7 is represented by the instruction 10A7 (hex) opcode operands A 7 1 is the opcode for the load instruction the next hex digit (0) represents which register to load the next 2 hex digits (A7) represent memory location to access Slide 21 Slide 22 What does it mean? What does it mean? Slide 23 Slide 24 6

7 And this? And this? Slide 25 Slide 26 Outline Program Execution Computer Architecture Machine Language Program Execution Arithmetic/Logic Instructions Communication with other Devices Other Architectures Fetch-decode-execute cycle Program counter (PC) register points to next instruction in memory to execute Instruction register holds instruction to be decoded and executed Slide 27 Slide 28 7

8 Fetch-decode-execute cycle Fetch-decode-execute cycle set the PC to the location of the first instruction copy instruction from memory to the instruction register. PC register states which memory location to copy from. increment PC to point to next instruction in memory decode and execute bit pattern in instruction register when instruction is done, start from step 2 above Slide 29 Slide 30 Example Example Slide 31 Slide 32 8

9 Example Characteristics computer does not get tired or bored mechanical pumping of data and instructions change PC to modify sequence of instructions can JUMP to data can modify programs: viruses, AI Slide 33 Slide 34 Outline Example for Rotate Computer Architecture Machine Language Program Execution Arithmetic/Logic Instructions Communication with other Devices Other Architectures Slide 35 Slide 36 9

10 Outline Peripherals Computer Architecture Machine Language Program Execution Arithmetic/Logic Instructions Communication with other Devices Other Architectures communication with external devices via controllers example: printers, disk drivers, monitors, modems different devices have different processing speeds need to synchronize communications should not keep CPU waiting for I/O to finish serial/parallel communication Slide 37 Slide 38 Peripherals Peripherals source: Slide 39 Slide 40 10

11 Memory Mapped I/O Direct Memory Access (DMA) replace a memory cell with a port, send data to device by storing data to that memory cell no need for special I/O instructions lose a memory cell for every port simple specialized computer to control peripherals (controller, channel) share memory with CPU Basic method (output) CPU stores data in memory at given location CPU signals controller to start I/O Controller reads memory at the given location Controller performs I/O CPU doesn t wait for I/O Specialized I/O instructions required Slide 41 Slide 42 CPU stores data... CPU signals controller... printer printer CPU MEMORY CPU MEMORY controller controller Slide 43 Slide 44 11

12 Controller reads data... Controller outputs data... printer printer CPU MEMORY CPU MEMORY controller controller Slide 45 Slide 46 Buffers and Caches memory reserved for data transfer across systems of different speeds example: CPU and printer CPU can generate data much faster than printer can print it CPU writes to buffer, printer reads from buffer also used in secondary storage systems Serial vs. Parallel Serial: one wire, one bit at a time Parallel: several wires, several bits at a time Slide 47 Slide 48 12

13 Outline Speed Computer Architecture Machine Language Program Execution Arithmetic/Logic Instructions Communication with other Devices Other Architectures clock allows synchronization of processes directly affects rate of fetch-execute cycle word size data bus width von Neumann Bottleneck benchmarks Slide 49 Slide 50 Speed of Light Limit Pipeline 300,000 km/sec = 30 cm/nanosecond 1 ns = 10-9 sec electrons cannot travel faster than this directly affects rate of fetch-execute cycle electrons must travel through the address and data busses, memory circuits, etc. Throughput: measure of work done Execution speed: time to execute an instruction machine cycle has 3 phases: fetch-decode-execute consider this as a pipe with 3 segments each segment can hold one instruction when pipe is full, there are 3 instructions in various phases of execution also known as pre-fetch Slide 51 Slide 52 13

14 Pipeline Illustration Pipeline vs. non-pipeline TIME fetch decode exec. non-pipeline pipeline 1 10AF MEM B AF 11B AF 11B0 10AF 11B < done done > Slide 53 Slide 54 Multiprocessing use more than one processor (parallel) shared memory inter-processor communication Single Instruction, Multiple Data Multiple Instruction, Multiple Data Distributed processing Neural Nets Slide 55 14