Major CPU Design Steps
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1 Major CPU Design Steps Using independent RTN, write the microoperations required for all target ISA instructions. 2 Construct the datapath required by the microoperations identified in step. 3 Identify and define the function of all control signals needed by the datapath. 3 Control unit design, based on micro-operation timing and control signals identified: - Hard-Wired: Finite-state machine implementation. - Microprogrammed. EECC55 - Shaaban # Lec # 4 Winter
2 Datapath Design Steps Write the micro-operation sequences required for a number of representative instructions using independent RTN. From the above, create an initial datapath by determining possible destinations for each data source (i.e registers, ALU). This establishes the connectivity requirements (data paths, or connections) for datapath components. Whenever multiple sources are connected to a single input, a multipleer of appropriate size is added. Find the worst-time propagation delay in the datapath to determine the datapath clock cycle. Complete the micro-operation sequences for all remaining instructions adding connections/multipleers as needed. EECC55 - Shaaban #2 Lec # 4 Winter
3 MIPS Instruction Formats I-Type: R-Type ALU Load/Store, Branch J-Type: Jumps op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 26 op target address 6 bits 26 bits op: Opcode, operation of the instruction. rs, rt, rd: The source and destination register specifiers. shamt: Shift amount. funct: selects the variant of the operation in the op field. address / immediate: Address offset or immediate value. target address: Target address of the jump instruction. EECC55 - Shaaban #3 Lec # 4 Winter
4 MIPS R-Type (ALU) Instruction Fields R-Type: All ALU instructions that use three registers OP rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op: Opcode, basic operation of the instruction. For R-Type op = rs: The first register source operand. rt: The second register source operand. rd: The register destination operand. shamt: Shift amount used in constant shift operations. funct: Function, selects the specific variant of operation in the op field. Destination register in rd Operand register in rs Operand register in rt Eamples: add $,$2,$3 sub $,$2,$3 and $,$2,$3 or $,$2,$3 EECC55 - Shaaban #4 Lec # 4 Winter
5 MIPS ALU I-Type Instruction Fields I-Type ALU instructions that use two registers and an immediate value Loads/stores, conditional branches. op: Opcode, operation of the instruction. rs: The register source operand. rt: The result destination register. immediate: Constant second operand for ALU instruction. Eamples: OP rs rt immediate 6 bits 5 bits 5 bits 6 bits Result register in rt add immediate: addi $,$2, and immediate andi $,$2, Source operand register in rs Constant operand in immediate EECC55 - Shaaban #5 Lec # 4 Winter
6 MIPS Load/Store I-Type Instruction Fields Eamples: OP rs rt address 6 bits 5 bits 5 bits 6 bits op: Opcode, operation of the instruction. For load op = 35, for store op = 43. rs: The register containing memory base address. rt: For loads, the destination register. For stores, the source register of value to be stored. address: 6-bit memory address offset in bytes added to base register. Offset Store word: sw 5($4), $3 Load word: lw $, 3($2) base register in rs source register in rt Destination register in rt Offset base register in rs EECC55 - Shaaban #6 Lec # 4 Winter
7 MIPS Branch I-Type Instruction Fields OP rs rt address 6 bits 5 bits 5 bits 6 bits op: Opcode, operation of the instruction. rs: The first register being compared rt: The second register being compared. address: 6-bit memory address branch target offset in words added to PC to form branch address. Register in rs Register in rt offset in bytes equal to instruction field address 4 Eamples: Branch on equal beq $,$2, Branch on not equal bne $,$2, EECC55 - Shaaban #7 Lec # 4 Winter
8 MIPS J-Type Instruction Fields J-Type: Include jump j, jump and link jal OP jump target 6 bits 26 bits op: Opcode, operation of the instruction. Jump j op = 2 Jump and link jal op = 3 jump target: jump memory address in words. Jump memory address in bytes equal to instruction field jump target 4 Eamples: Branch on equal j Branch on not equal jal EECC55 - Shaaban #8 Lec # 4 Winter
9 A Subset of MIPS Instructions ADD and SUB: addu rd, rs, rt subu rd, rs, rt op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits OR Immediate: ori rt, rs, imm op rs rt immediate 6 6 bits 5 bits 5 bits 6 bits LOAD and STORE Word lw rt, rs, imm6 sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 BRANCH: beq rs, rt, imm6 op rs rt immediate 6 bits 5 bits 5 bits 6 bits EECC55 - Shaaban #9 Lec # 4 Winter
10 Instruction Processing Steps Instruction Fetch Net Instruction Obtain instruction from program storage Update program counter to address of net instruction }Common steps for all instructions Instruction Decode Determine instruction type Obtain operands from registers Eecute Compute result value or status Result Store Store result in register/memory if needed (usually called Write Back). EECC55 - Shaaban # Lec # 4 Winter
11 Overview of MIPS Instruction Micro-operations All instructions go through these two steps: Send program counter to instruction memory and fetch the instruction. (fetch) Read one or two registers, using instruction fields. (decode) Load reads one register only. Additional instruction eecution actions (eecution) depend on the instruction in question, but similarities eist: All instruction classes use the ALU after reading the registers: Memory reference instructions use it for address calculation. Arithmetic and logic instructions (R-Type), use it for the specified operation. Branches use it for comparison. Additional eecution steps where instruction classes differ: Memory reference instructions: Access memory for a load or store. Arithmetic and logic instructions: Write ALU result back in register. Branch instructions: Change net instruction address based on comparison. EECC55 - Shaaban # Lec # 4 Winter
12 A Single Cycle Implementation Design target : A single-cycle instruction implementation All micro-operations of an instruction are to be carried out in a single system clock cycle. EECC55 - Shaaban #2 Lec # 4 Winter
13 Datapath Components Instruction Word Two state elements needed to store and access instructions: Instruction memory: Only read access. No read control signal. 2 Program counter: -bit register. Written at end of every clock cycle: No write control signal. -bit Adder: To compute the the net instruction address. EECC55 - Shaaban #3 Lec # 4 Winter
14 Register File More Datapath Components Main ALU Register File: Contains all registers. Two read ports and one write port. Register writes by asserting write control signal Writes are edge-triggered. Can read and write to the same register in the same clock cycle. EECC55 - Shaaban #4 Lec # 4 Winter
15 Register File Details Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: Write Enable busw Clk RW RA RB bit Registers RA (number) selects the register to put on busa (data): busa = R[RA] RB (number) selects the register to put on busb (data): busb = R[RB] RW (number) selects the register to be written via busw (data) when Write Enable is Write Enable: R[RW] busw Clock input (CLK) The CLK input is a factor ONLY during write operations. During read operation, it behaves as a combinational logic block: RA or RB valid => busa or busb valid after access time. busa busb EECC55 - Shaaban #5 Lec # 4 Winter
16 Idealized Memory Write Enable Address Memory (idealized) One input bus: Data In. One output bus: Data Out. Memory word is selected by: Address selects the word to put on Data Out bus. Write Enable = : address selects the memory word to be written via the Data In bus. Clock input (CLK): Data In DataOut Clk The CLK input is a factor ONLY during write operation, During read operation, this memory behaves as a combinational logic block: Address valid => Data Out valid after access time. EECC55 - Shaaban #6 Lec # 4 Winter
17 R-Type Eample: Micro-Operation Sequence For ADDU addu rd, rs, rt OP rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Instruction Word Mem[PC] PC PC + 4 R[rd] R[rs] + R[rt] Fetch the instruction Increment PC Add register rs to register rt result in register rd EECC55 - Shaaban #7 Lec # 4 Winter
18 Building The Datapath Instruction Fetch & PC Update: Portion of the datapath used for fetching instructions and incrementing the program counter. EECC55 - Shaaban #8 Lec # 4 Winter
19 Simplified Datapath For R-Type Instructions EECC55 - Shaaban #9 Lec # 4 Winter
20 More Detailed Datapath For R-Type Instructions With Control Points Identified RegWr Rd Rs Rt ALUctr busw Clk Rw Ra Rb -bit Registers busa busb ALU Result EECC55 - Shaaban #2 Lec # 4 Winter
21 R-Type Register-Register Timing Clk PC Old Value Rs, Rt, Rd, Op, Func ALUctr RegWr busa, B busw busw Clk RegWr Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Rd Rs Rt Rw Ra Rb -bit Registers Instruction Memory Access Time New Value busa busb Delay through Control Logic New Value New Value ALUct r ALU Register File Access Time New Value Result ALU Delay New Value Register Write Occurs Here EECC55 - Shaaban #2 Lec # 4 Winter
22 Logical Operations with Immediate Eample: Micro-Operation Sequence For ORI ori rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 Instruction Word Mem[PC] PC PC + 4 R[rt] R[rs] OR ZeroEt[imm6] Fetch the instruction Increment PC OR register rs with immediate field zero etended to bits, result in register rt EECC55 - Shaaban #22 Lec # 4 Winter
23 Datapath For Logical Instructions With Immediate RegDst Rd Rt Mu Rs RegWr ALUctr busw Clk Rw Ra Rb -bit Registers busa busb ALU Result imm6 6 ZeroEt Mu ALUSrc EECC55 - Shaaban #23 Lec # 4 Winter
24 Load Operations Eample: Micro-Operation Sequence For LW lw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 Instruction Word Mem[PC] PC PC + 4 R[rt] Mem[R[rs] + SignEt[imm6]] Fetch the instruction Increment PC Immediate field sign etended to bits and added to register rs to form memory load address, word at load address to register rt EECC55 - Shaaban #24 Lec # 4 Winter
25 Additional Datapath Components For Loads & Stores Inputs for address and write (store) data Output for read (load) result 6-bit input sign-etended into a -bit value at the output EECC55 - Shaaban #25 Lec # 4 Winter
26 Datapath For Loads RegDst busw Clk Rd RegWr Mu imm6 Rt Rs Rw Ra Rb -bit Registers 6 busb Etender busa Mu ALUSrc ALUctr ALU Data In Clk MemWr WrEn Adr Data Memory W_Src Mu EtOp EECC55 - Shaaban #26 Lec # 4 Winter
27 Store Operations Eample: Micro-Operation Sequence For SW sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 Instruction Word Mem[PC] PC PC + 4 Mem[R[rs] + SignEt[imm6]] R[rt] Fetch the instruction Increment PC Immediate field sign etended to bits and added to register rs to form memory store address, register rt written to memory at store address. EECC55 - Shaaban #27 Lec # 4 Winter
28 Datapath For Stores RegDst busw Clk Rd RegWr Mu imm6 Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busb Etender busa Mu ALUctr ALU Data In Clk MemWr WrEn Adr Data Memory W_Src Mu EtOp ALUSrc EECC55 - Shaaban #28 Lec # 4 Winter
29 Conditional Branch Eample: Micro-Operation Sequence For BEQ beq rs, rt, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 Instruction Word Mem[PC] PC PC + 4 Equal R[rs] == R[rt] Fetch the instruction Increment PC Calculate the branch condition if (COND eq ) PC PC ( SignEt(imm6) 4 ) Calculate the net instruction s PC else address PC PC + 4 EECC55 - Shaaban #29 Lec # 4 Winter
30 ALU to evaluate branch condition Adder to compute branch target: Sum of incremented PC and the sign-etended lower 6-bits on the instruction. Datapath For Branch Instructions EECC55 - Shaaban #3 Lec # 4 Winter
31 More Detailed Datapath For Branch Operations Instruction Address Cond 4 imm6 PC Et npc_sel Mu Adder Adder PC Clk busw Clk RegWr Rs Rw Ra Rb -bit Registers Rt busa busb Equal? EECC55 - Shaaban #3 Lec # 4 Winter
32 Combining The Datapaths For Memory Instructions and R-Type Instructions Highlighted mulipleors and connections added to combine the datapaths of memory and R-Type instructions into one datapath EECC55 - Shaaban # Lec # 4 Winter
33 Instruction Fetch Datapath Added to ALU R-Type and Memory Instructions Datapath EECC55 - Shaaban #33 Lec # 4 Winter
34 A Simple Datapath For The MIPS Architecture Datapath of branches and a program counter multipleor are added. Resulting datapath can eecute in a single cycle the basic MIPS instruction: - load/store word - ALU operations - Branches EECC55 - Shaaban #34 Lec # 4 Winter
35 Single Cycle MIPS Datapath Necessary multipleors and control lines are identified here: EECC55 - Shaaban #35 Lec # 4 Winter
36 Putting It All Together: A Single Cycle Datapath Inst Memory Adr Rs <2:25> Rt <6:2> Rd <:5> <:5> Imm6 Instruction<3:> imm6 4 PC Et Adder Adder npc_sel PC Mu Clk RegDst RegWr busw Clk imm6 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busa busb Etender Equal Mu ALUctr = ALU MemWr WrEn Adr Data In Data Memory Clk MemtoReg Mu EtOp ALUSrc EECC55 - Shaaban #36 Lec # 4 Winter
37 Adding Support For Jump: Micro-Operation Sequence For Jump: J j jump_target OP Jump_target 6 bits 26 bits Instruction Word Mem[PC] PC PC + 4 Fetch the instruction Increment PC PC PC(3-28),jump_target, Update PC with jump address EECC55 - Shaaban #37 Lec # 4 Winter
38 Datapath For Jump Net Instruction Address 4 npc_sel JUMP Adder Mu Mu PC Instruction(5-) imm6 PC Et Adder 4 Clk Instruction(25-) jump_target 26 Shift left 2 28 PC+4(3-28) EECC55 - Shaaban #38 Lec # 4 Winter
39 Instruction Memory Adr Instruction<3:> <:5> <:5> <6:2> <2:25> <2:25> <:25> Op Fun Rt Rs Rd Imm6 Jump_target Control Unit npc_sel RegWr RegDst EtOp ALUSrc ALUctr MemWr MemtoReg Jump Equal DATA PATH EECC55 - Shaaban #39 Lec # 4 Winter
40 Single Cycle MIPS Datapath Etended To Handle Jump with Control Unit Added EECC55 - Shaaban #4 Lec # 4 Winter
41 Control Signal Generation See func Don t Care Appendi A op add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump EtOp ALUctr<2:> Add Subtract Or Add Add Subtract EECC55 - Shaaban #4 Lec # 4 Winter
42 The Concept of Local Decoding RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump EtOp ALUop<N:> op 6 op R-type ori lw sw beq jump R-type Main Control Or func 6 ALUop N Add ALU Control (Local) Add Subtract ALUctr 3 ALU EECC55 - Shaaban #42 Lec # 4 Winter
43 Local Decoding of func func Field op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 R-type ori lw sw beq jump ALUop (Symbolic) R-type Or Add Add Subtract ALUop<2:> funct<5:> Instruction Operation add subtract and or set-on-less-than ALUctr ALU ALUctr<2:> ALU Operation Add Subtract And Or Set-on-less-than EECC55 - Shaaban #43 Lec # 4 Winter
44 The Truth Table for ALUctr ALUop R-type ori lw sw beq (Symbolic) R-type Or Add Add Subtract ALUop<2:> funct<3:> Instruction Op. add subtract and or set-on-less-than ALUop bit<2> bit<> bit<> bit<3> func bit<2> bit<> bit<> ALU Operation ALUctr bit<2> bit<> bit<> Add Subtract Or Add Subtract And Or Set on < EECC55 - Shaaban #44 Lec # 4 Winter
45 The Truth Table For The Main Control op R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump EtOp ALUop (Symbolic) R-type Or Add Add Subtract ALUop <2> ALUop <> ALUop <> EECC55 - Shaaban #45 Lec # 4 Winter
46 Eample: RegWrite Logic Equation op R-type ori lw sw beq jump RegWrite RegWrite = R-type + ori + lw =!op<5> &!op<4> &!op<3> &!op<2> &!op<> &!op<> (R-type) +!op<5> &!op<4> & op<3> & op<2> &!op<> & op<> (ori) + op<5> &!op<4> &!op<3> &!op<2> & op<> & op<> (lw) op<5>.. op<5>.. op<5>.. <> <> <> op<5>.. op<5>.. op<5>.. <> <> op<> R-type ori lw sw beq jump RegWrite EECC55 - Shaaban #46 Lec # 4 Winter
47 PLA Implementation of the Main Control op<5>.. <> op<5>.. <> op<5>.. <> op<5>.. <> op<5>.. <> op<5>.. op<> R-type ori lw sw beq jump RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump EtOp ALUop<2> ALUop<> ALUop<> EECC55 - Shaaban #47 Lec # 4 Winter
48 Clk PC Old Value Rs, Rt, Rd, Op, Func ALUctr Worst Case Timing (Load) Clk-to-Q New Value Old Value Old Value Instruction Memoey Access Time New Value Delay through Control Logic New Value EtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value RegWr Old Value New Value busa busb Old Value Delay through Etender & Mu Old Value Register Write Occurs Register File Access Time New Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busw Old Value New EECC55 - Shaaban #48 Lec # 4 Winter
49 Instruction Timing Comparison Arithmetic & Logical PC Inst Memory Reg File mu ALU mu setup Load PC Inst Memory Reg File mu ALU Data Mem mu Critical Path Store PC Inst Memory Reg File mu ALU Data Mem Branch PC Inst Memory Reg File cmp mu setup EECC55 - Shaaban #49 Lec # 4 Winter
50 Drawback of Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: PC s Clock -to-q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew All instructions must take as much time as the slowest Cycle time for load is longer than needed for all other instructions. Real memory is not as well-behaved as idealized memory Cannot always complete data access in one (short) cycle. EECC55 - Shaaban #5 Lec # 4 Winter
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