EE247 Lecture 11. EECS 247 Lecture 11: Introduction to Data Converters 2008 H. K. Page 1. Material Covered in EE247 Where are We?

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1 EE47 Lecture Data converters Areas of application Data converter transfer characteristics Sampling, aliasing, reconstruction Amplitude quantization Static converter error sources Offset Full-scale error Differential non-linearity (DNL) Integral non-linearity (INL) EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page Material Covered in EE47 Where are We? Filters Continuous-time filters Biquads & ladder type filters Opamp-RC, Opamp-MOSFET-C, gm-c filters Automatic frequency tuning Switched capacitor (SC) filters Data Converters D/A converter architectures A/D converter Nyquist rate ADC- Flash, Pipeline ADCs,. Oversampled converters Self-calibration techniques Systems utilizing analog/digital interfaces EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page

2 Converter Applications EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 3 Data Converter Basics DSPs benefited from device scaling However, real world signals are still analog: Continuous time Continuous amplitude DSP can only process: Discrete time Discrete amplitude Need for data conversion from analog to digital and digital to analog Analog Input Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Analog Output Filters?...? Filters EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 4

3 A/D & D/A Conversion A/D Conversion D/A Conversion EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 5 Data Converters Stand alone data converters Used in variety of systems Example: Analog Devices AD935 bit/ 65Ms/s ADC- Applications: Ultrasound equipment IF sampling in wireless receivers Various hand-held measurement equipment Low cost digital oscilloscopes EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 6

4 Data Converters Embedded data converters Integration of data conversion interfaces along with DSPs and/or RF circuits Cost, reliability, and performance Main issues Feasibility of integrating sensitive analog functions in a technology typically optimized for digital performance Down scaling of supply voltage as a result of downscaling of feature sizes Interference & spurious signal pick-up from on-chip digital circuitry and/or high frequency RF circuits Portable applications dictate low power consumption EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 7 Embedded Converters Example: Typical Cell Phone Contains in integrated form: 4 Rx filters 4 Tx filters 4 Rx ADCs 4 Tx DACs 3 Auxiliary ADCs 8 Auxiliary DACs Total: Filters 8 ADCs 7 DACs Dual Standard, I/Q Audio, Tx/Rx power control, Battery charge control, display,... EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 8

5 D/A Converter Transfer Characteristics An ideal digital-toanalog converter: Accepts digital inputs b -b n Produces either an analog output voltage or current Assumption (will be revisited) Uniform, binary digital encoding Unipolar output ranging from to V FS MSB b b LSB. b N D/A V o or I o Nomenclature: N = # of bits VFS = full scale output Δ= min. step size LSB VFS Δ= N VFS or N = log resolution Δ EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 9 D/A Converter Transfer Characteristics V N = #of bits FS = full scale output Δ= min. step size LSB MSB b b. D/A V o or I o V Δ= FS N LSB b N V = V N FS i i= N i= bi N i =Δ bi, bi= or ( =,alli) Note:D bi max Vo = VFS Δ max Vo = VFS N binary-weighted EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page

6 D/A Converter Exampe: D/A with 3-bit Resolution Example: for N=3 and V FS =.8V input code Find the output value V ( ) V =Δ b + b + b 3 Then: Δ= V / =.V FS 3 V =.V ( + + ) = V =.5V Note:MSB V / & LSB V / FS FS N MSB LSB b b b 3 D/A V EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page Ideal DAC introduces no error! Ideal 3-Bit D/A Transfer Characteristic V FS Analog Output Ideal Response One-to-one mapping from input to output V FS / Step Height (LSB =Δ) V FS /8 Digital Input Code EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page

7 A/D Converter Transfer Characteristics An ideal analog-to-digital converter: Accepts analog input in the form of either voltage or current Produces digital output either in serial or parallel form Assumption (will be revisited) Unipolar input ranging from to V FS Uniform, binary digital encoding V in V N = # of bits FS A/D = full scale output MSB b b. b N LSB Δ= min. resolvable input LSB VFS Δ= N VFS or N = log resolution Δ EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 3 Ideal ADC introduces error with max peakto-peak: (+-/ Δ) Δ = V FS / N N= # of bits This error is called ``quantization error`` Ideal A/D Transfer Characteristic Example: 3Bit A/D Converter Digital Output LSB Δ Δ 3Δ 4Δ 5Δ 6Δ 7Δ Analog input V FS EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 4

8 Non-Linear Data Converters So far data converter characterisitics studied are with uniform, binary digital encoding For some applications to maximize dynamic range non-linear coding is used e.g. Voiceband telephony, Small signals larger # of codes Large signals smaler # of codes EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 5 Example: Non-Linear A/D Converter For Voice-Band Telephony Applications Non-linear ADC and DAC used in voice-band CODECs To maximize dynamic range without need for large # of bits Non-linear Coding scheme called A-law & μ-law is used Also called companding Ref: P. R. Gray, et al. "Companded pulse-code modulation voice codec using monolithic weighted capacitor arrays," IEEE Journal of Solid-State Circuits, vol., pp , December 975. Coder Output (DIGITAL) -V FS -V FS / -V FS /4 SIGN BIT SEGMENT # Coder Input (ANALOG) STEP # EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 6

9 Data Converter Performance Metrics Data Converters are typically characterized by static, time-domain, & frequency domain performance metrics : Static Offset Full-scale error Differential nonlinearity (DNL) Integral nonlinearity (INL) Monotonicity Dynamic Delay, settling time Aperture uncertainty Distortion- harmonic content Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR) Idle channel noise Dynamic range & spurious-free dynamic range (SFDR) EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 7 Typical Sampling Process C.T. S.D. D.T. Continuous Time Sampled Data (e.g. T/H signal) time Physical Signals Clock Discrete Time "Memory Content" EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 8

10 Discrete Time Signals A sequence of numbers (or vector) with discrete index time instants Intermediate signal values not defined (not the same as equal to zero!) Mathematically convenient, non-physical We will use the term "sampled data" for related signals that occur in real, physical interface circuits EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 9 Uniform Sampling y(kt)=y(k) t= T T 3T 4T 5T 6T... k= Samples spaced T seconds in time Sampling Period T Sampling Frequency f s =/T Problem: Multiple continuous time signals can yield exactly the same discrete time signal (aliasing) EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page

11 Data Converters ADC/DACs need to sample/reconstruct to convert from continuous-time to discrete-time signals and back Purely mathematical discrete-time signals are different from "sampled-data signals" that carry information in actual circuits Question: How do we ensure that sampling/reconstruction fully preserve information? EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page Aliasing The frequencies f x and nf s ±f x, n integer, are indistinguishable in the discrete time domain Undesired frequency interaction and translation due to sampling is called aliasing If aliasing occurs, no signal processing operation downstream of the sampling process can recover the original continuous time signal! EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page

12 Frequency Domain Interpretation Signal scenario before sampling Amplitude f in f s / Continuous Time f s f s.. f Signal scenario after sampling DT Amplitude.5 Discrete Time f/f s nf S ±f max signal fold back into band of interest Aliasing EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 3 Brick Wall Anti-Aliasing Filter Amplitude Filter Continuous Time f s f s... f Discrete Time.5 f/f s Sampling at Nyquist rate (f s =f signal ) required brick-wall anti-aliasing filters EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 4

13 Practical Anti-Aliasing Filter Desired Signal Parasitic Tone Continuous Time Attenuation B f s / f s -B f s... f Discrete Time B/f s.5 f/f s Practical filter: Nonzero "transition band" In order to make this work, we need to sample faster than x the signal bandwidth "Oversampling" EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 5 Data Converter Classification f s > f max Nyquist Sampling "Nyquist Converters" Actually always slightly oversampled (e.g. CODEC f sig max =3.4kHz & ADC sampling 8kHz f s /f max =.35) Requires anti-aliasing filtering prior to A-to-D conversion f s >> f max Oversampling "Oversampled Converters" Anti-alias filtering is often trivial Oversampling is also used to reduce quantization noise, see later in the course... f s < f max Undersampling (sub-sampling) EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 6

14 Continuous Time Sub-Sampling Amplitude BP Filter f s... f Discrete Time.5 f/f s Sub-sampling sampling at a rate less than Nyquist rate aliasing For signals an intermediate frequency Not destructive! Sub-sampling can be exploited to mix a narrowband RF or IF signal down to lower frequencies EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 7 Nyquist Data Converter Topics Basic operation of data converters Uniform sampling and reconstruction Uniform amplitude quantization Characterization and testing Common ADC/DAC architectures Selected topics in converter design Practical implementations Compensation & calibration for analog circuit non-idealities Figures of merit and performance trends EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 8

15 Where Are We Now? Analog Input We now know how to preserve signal information in CT DT transition Analog Preprocessing A/D Conversion DSP Anti-Aliasing Filter Sampling (+Quantization)... How do we go back from DT CT? D/A Conversion Analog Postprocessing? Analog Output EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 9 Ideal Reconstruction x(k) x(t) The DSP books tell us: k = x ( t) = x( k) g( t kt ) sin(πbt) g( t) = πbt Unfortunately not all that practical... EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 3

16 Zero-Order Hold Reconstruction Amplitude sampled data - after ZOH 3 Time [μs] How about just creating a staircase, i.e. hold each discrete time value until new information becomes available? What does this do to the frequency content of the signal? Let's analyze this in two steps... EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 3 DT CT: Infinite Zero Padding Time Domain Frequency Domain DT sequence f /f s Infinite Zero padded Interpolation: CT Signal f s.5f s.5f s f /f s Next step: pass the samples through a sample & hold stage (ZOH) EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 3

17 Hold Pulse T p =T s Transfer Function abs(h(f)) sin( Tπ f T p sin(π s ) H( f ) = ftp ) H ( f ) = π f T T s πft s p f /f s EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 33 ZOH Spectral Shaping Continuous Time Pulse Train Spectrum ZOH Transfer Function ("Sinc Shaping") ZOH output, Spectrum of Staircase Approximation X(k) ZOH f / f s EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 34

18 Smoothing Filter Filter out the high frequency content associated with staircase shape of the signal Order of the filter required is a function of oversampling ratio High oversampling helps reduce filter order requirement f / f s EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 35 Summary Sampling theorem f s > f max, usually dictates anti-aliasing filter If theorem is met, CT signal can be recovered from DT without loss of information ZOH and smoothing filter reconstruct CT signal from DT vector Oversampling helps reduce order & complexity of anti-aliasing & smoothing filters EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 36

19 Next Topic Analog Input Done with "Quantization in time" Next: Quantization in amplitude Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Anti-Aliasing Filter Sampling (+Quantization)... D/A+ZOH Smoothing Filter Analog Output EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 37 Ideal ADC ("Quantizer") Accepts & analog input & generates it s digital representation Quantization step: Δ (= LSB) Full-scale input range: -.5Δ ( N -.5)Δ E.g. N = 3 Bits V FS = -.5Δ to 7.5Δ Digital Output Code Ideal converter with infinite # of bits ADC characteristics V FS ADC Input Voltage [ Δ] EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 38

20 Quantization Error Quantization error Difference between analog input and digital output of the ADC converted to analog via an ideal DAC Called: Quantization error Residue Quantization noise V in ADC. Ideal DAC Residue - Σ ε q (V in ) + EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 39 Quantization Error For an ideal ADC: Quantization error is bounded by Δ/ +Δ/ for inputs within full-scale range V in ADC Model D + out ε q (V in ) Digital Output Code Quantization error [LSB] ideal converter with infinite bits ADC characteristics ADC Input Voltage [Δ] EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 4

21 ADC Dynamic Range Assuming quantization noise is much larger compared to circuit generated noise: D.R. Maximum Full Scale Signal Power = log Quantization Noise Power Crude assumption: Same peak/rms ratio for signal and quantization noise! D.R. Maximum Peak Full Scale = log Peak Quantization Noise VFS N = log = log = 6. N [ db ] Δ Question: What is the quantization noise power? EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 4 Quantization Error Assume V in is a slow ramp signal with amplitude equal to ADC full-scale V in _Ramp V FS Quantization error [LSB] Δ/ Δ/ Time Time Note: Ideal ADC quantization error waveform periodic and also ramp EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 4

22 Quantization Error Derivation Need to find the rms value for quantization error waveform: + T/ + Δ /k Quantization Δ εeq = ( k t) dt ( k t) = dt error T k Δ k = k T/ Δ/k + Δ /k t dt Δ /k Δ/ Δ ε Δ/k eq = Independent of k Δ Δ/ εeq = In general above equation applies if: Input signal much larger than LSB Input signal busy No signal clipping ε q =k.t Δ/k Time EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 43 Quantization Error PDF Probability density function (PDF) Uniformly distributed from Δ/ +Δ/ provided that: Busy input Amplitude is many LSBs No overload Not Gaussian! Zero mean Variance +Δ / Δ / e Δ e = de= Δ PDF /Δ Ref: W. R. Bennett, Spectra of quantized signals, Bell Syst. Tech. J., vol. 7, pp , July Δ/ +Δ/ error B. Widrow, A study of rough amplitude quantization by means of Nyquist sampling theory, IRE Trans. Circuit Theory, vol. CT-3, pp , 956. EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 44

23 Signal-to-Quantization Noise Ratio If certain conditions the quantization error can be viewed as being "random", and is often referred to as noise In this case, we can define a peak signal-to-quantization noise ratio, SQNR, for sinusoidal inputs: N Δ e.g. N SQNR 8 5 db N SQNR= =.5 74 db Δ 6 98 db db = 6.N +.76 db Accurate for N>3 Real converters do not quite achieve this performance due to other sources of error: Electronic noise Deviations from the ideal quantization levels EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 45 ADC SNR Measurement log(snr) SQNRpeak = 6.N +.76 db Ideal 6dB/octave Realistic db Dynamic Range Vin [db] EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 46

24 Static Ideal Macro Models DAC D in V out V in ADC + ε q D out +-.5LSB ambiguity EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 47 Cascade of Data Converters q ADC DAC V in + ε V out D in DAC ADC + εq D out EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 48

25 Static Converter Errors Deviation of converter characteristics from ideal: Offset Full-scale error Differential nonlinearity DNL Integral nonlinearity INL EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 49 ADC Offset Error DAC Ref: Understanding Data Converters, Texas Instruments Application Report SLAA3, Mixed-Signal Products, 995. EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 5

26 Full-Scale Error ADC Actual full-scale point Ideal full-scale point DAC Ideal full-scale point Full-scale error Full-scale error Actual full-scale point EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 5 Offset and Full-Scale Error Note: For further measurements (DNL, INL) connecting the endpoints & deriving ideal codes based on the non-ideal endpoints eliminates offset and fullscale error Digital Output Code ADC characteristics ideal converter Offset error Full-scale error ADC Input Voltage [LSB] EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 5

27 Offset and Full-Scale Errors Alternative specification in % Full-Scale = % * (# of LSB value)/ N Gain error can be extracted from offset & full-scale error Non-trivial to build a converter with extremely good full-scale/offset specs Typically full-scale/offset error is most easily compensated by the digital pre/post-processor More critical: Linearity measures DNL, INL EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 53 ADC Differential Nonlinearity DNL = deviation of code width from Δ (LSB). Endpoints connected. Ideal characteristics derived eliminating offset & full-scale error 3. DNL measured Digital Output Code ADC Transfer Curve Real Ideal -.4 LSB DNL error LSB DNL error +.4 LSB DNL error ADC Input Voltage [Δ] EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 54

28 ADC Differential Nonlinearity Ideal ADC transitions point equally spaced by LSB For DNL measurement, offset and full-scale error is eliminated DNL [k] (a vector) measures the deviation of each code from its ideal width Typically, the vector for the entire code is reported If only one DNL # is reported that would be the worst case EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 55 Example Offset, Full-Scale Error, Gain,& DNL A 3bit ADC is designed to have an ideal: LSB=.V V FS =.8V The measured transitions levels for the end product is shown in the table, compute offset, fullscale, gain error, & DNL Transition # Ideal transition point [V].5 Real transition point [V]. - Offset: (real transition-ideal)= -.3V, in LSB -.3/.= -.3LSB - Full-scale error (real last transition-ideal) = =.3V in LSB.3/.=+.3LSB LSB after correcting for offset & full-scale error: LSB= (Last transition-first transition)/( N -) LSB= (.68-.)/6=.V EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 56

29 ADC Differential Nonlinearity Example V FS = N x.v=.88v 4-Gain relative to ideal Gain=.8/.88=.9 Code # Code Width [V] - Width [LSB] - DNL [LSB] Find all code widths Width[k]=Transition[k+]- Transition[k] -Divide code width by LSB W[k] Find DNL: DNL[k]=W[k]-LSB EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 57 ADC Differential Nonlinearity Example DNL [LSB].5 Max. DNL 3 Code # DNL [LSB] Code # 7 - EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 58

30 ADC Differential Nonlinearity Examples Digital Output Code ADC characteristics Ideal Converter Missing code (+.5/- LSB DNL) Digital Output Code Note: As input increases at a point output decreases instead of increase: Non-monotonic Non-monotonic (> LSB DNL) ADC Input Voltage [Δ] ADC Input Voltage [Δ] EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 59 ADC DNL DNL=- implies missing code For an ADC DNL < - not possible undefined Can show: all i DNL[i] = For a DAC possible to have DNL < - EECS 47 Lecture : Introduction to Data Converters 8 H. K. Page 6