Unbalanced Wilkinson Power Divider

Transcription

1 1 Unbalanced Wilkinson Power Divider Curtis Mayberry, Student Member, IEEE Abstract A Wilinson power divider for use in a direct TV receiver at 10.4 GHz with a power divider ratio of 2:1 has been designed and simulated. The design achieves a power division ratio of 1.992:0.99 with an average return loss of db and an isolation of 49.5 db between the two output ports. I. INTRODUCTION The Wilkinson Power divider is a three port network capable of being matched at all ports and isolated between the two output ports. Although it may not be lossless due to a resistor used in its design, the power divider does appear to be lossless when output ports are matched. A Wilkinson divider with an unbalanced power split of 2:1 will be designed for a direct TV receiver at 10.4 GHz using microstrip transmission lines on a Duroid substrate. The specifications of the divider are: Parameter Value Technology Microstrip Substrate Duroid Power Split Ratio (k 2 ) 2:1 (2) Operating Frequency, f GHz System Impedance 50Ω Available Resistors 100Ω Return Loss As Low as Possible Layout Size < 6" x6" The Duroid substrate available has the following properties: Parameter Value PCB Dielectric Duroid Rel. Permitivity 2.2 Loss Tangent tan δ = Board thickness h = 31 [mil] Metal thickness t = 1 [mil] The design will first be designed using theory and then these parameters will be verified using simulation. Next the design will be implemented using microstrip transmission lines A. Theoretical Design II. INITIAL DESIGN The power divider was initially designed using the theoretical equations [1] to find the characteristic impedances necessary for a 2:1 power divider. The design of a wilkinson power divider with unequal power division is shown in fig. 1. The Characteristic Impedances for the design can be calculated as shown below: R = Z 0 (k + 1 k ) Z 0 = R (k + 1 k ) = 100Ω ( ) = 47.14Ω Fig. 1. Wilkinson power divider with unequal power division [1] Z 03 = Z k 2 k 3 3 = (47.14Ω) = 48.55Ω 23/2 Z 02 = k 2 Z 03 = 2(48.55Ω) = 97.1Ω The lengths of the port 2 and port 3 transmission lines with characteristic impedances of Z 02 and Z 03 are both λ/4. Each port must be matched to 50Ω system impedance however as shown in fig. 1 each port has a different input impedance In order to match to each port quarter wave transformers at each port transform the input impedance of each port to the system impedance of 50Ω. The characteristic impedance of each quarter wave transformer is calculated as: Z in1 = Z 0 = 47.14Ω Z in2 = kz 0 = 2(47.14Ω) = 66.67Ω Z in3 = Z 0 k = 47.14Ω 2 = 33.33Ω Z 0T 1 = Z in1 Z L = (47.14Ω)(50Ω) = 48.55Ω Z 0T 2 = Z in2 Z L = (66.67Ω)(50Ω) = 57.74Ω Z 0T 3 = Z in3 Z L = (33.33Ω)(50Ω) = 40.82Ω B. Ideal Simulation Next a simulation utilizing ideal transmission lines was performed to verify the ideal model and the calculated parameters. The schematic of the ideal simulation uses the characteristic impedances calculated in the theoretical design section. The electrical lengths of all transmission lines are λ/4. The schematic of the ideal simulation is shown in fig. 2. The ideal simulation results show the ideal characteristics of an unbalanced Wilkinson divider and confirm the parameters calculated in the theoretical calculations section. The power

2 2 III. MICROSTRIP DESIGN A. Initial Microstrip Simulation Fig. 2. Schematic of the ideal simulation The inital mocrostrip design was created using LineCalc to calculate the lengths and widths of each section to implement it as a microstrip line. The schematic of the inital microstrip design is shown in fig. 2. division results shown in fig. 3 show a perfect 2:1 power division. The return loss results in fig. 4 show an ideal return loss of -100 db at 10.4 GHz. The isolation results in fig. 5 show ideal isolation between ouput ports 2 and 3. Fig. 6. Initial microstrip implementation schematic Fig. 3. Ideal simulation power division Results As seen in fig. 7, 8, and 9 the initial microstip implementation had only a very small degradation in performance from the ideal characteristics. Fig. 7. Initial microstrip power division results Fig. 4. Ideal simulation return loss Results Fig. 5. Ideal simulation isolation Results Fig. 8. Initial microstrip return loss results

3 3 Fig. 9. Initial microstrip isolation results Fig. 11. First realistic microstrip power division results B. Realistic Microstrip Simulation Although the simulation results for the initial microstrip implementation were close to ideal, layout and fabrication considerations add additional complexity to the design and this requires further modelling of the design. First the splitting that occurs before the resistor has been modeled as a tee-section. The curve for each section of line must also be considered. This can be considered as an extension of the transmission line following it with a length of (π/2)*radius. The minimum radius was selected for a compact design and to reduce the length of the resistor stubs. The schematic with these changes is shown in fig. 10. Fig. 12. First realistic return loss results Fig. 13. First realistic isolation results Fig. 10. Realistic Schematic Iteration 1 The power division can be measured by S 2 21 for the percentage of power going to port 2 and S 2 12 for the percentage of power going to port 2 as seen in fig. 11. The percent power going to port 2 shifted by 1.4% The tee section shifted many of the matching frequencies away from the required 10.4GHz as shown in the return loss results of fig. 12. It also degraded the return loss significantly. This frequency shift is also shown in the isolation plot of fig. 13. C. Final Design Next the resistor must have a pad in order to be properly soldered in place. The easiest way to do this is to makse sure that the horizontal length of the port 1 and port 2 transmission lines between the curve and the resistor soldering node are the same length. In order to achieve this the longer of the two transmission lines is lengthened between the spltting tee and its curve. An 0805 size chip resistor [2] was selected to act as the isolation resistor for the design. The manufacturer s suggested pad layout was used to help design the pad layout and sizing for the resistor. The ports were then exteded to the edge of the board using 50Ω lines. The final schematic is shown in fig. 14.

4 4 Fig. 14. Final Schematic After the design was updated with the resistor pads the main port lines before the resistor were then optimized to achieve the correct power division and the transformer network on each network was tuned to match to 50 ohms and achieve a low return loss. The final layout is shown in fig. 15. D. Final Design Characterization The final design performance summary is shown in the table below: Parameter Value Technology Microstrip Substrate Duroid Power Split Ratio (k 2 ) 1.992:0.99 (2) Operating Frequency, f GHz System Impedance 50Ω Available Resistors 100Ω (0805) Return Loss port db Return Loss port db Return Loss port db Isolation 49.5 db Layout Size 0.915" 0.605" The power split can be seen in fig. 16. Both the port 2 and port 3 power split percentages are 0.3% lower than ideal, though this can be attributed to the losses due to the small mismatches at the output ports. The return losses can be seen in fig. 17. The design achieves an average return loss of db at 10.4 GHz. The isolation can be seen in fig. 18. The design achieves an isolation of 49.5dB at 10.4 GHz. All specifications were meet. Fig. 16. Fig. 17. Final design power split Final design return losses

5 5 Fig. 15. Final Layout [2] Panasonic, Think Film Chip Resistors, Fig. 18. Final design port2 - port 3 isolation IV. CONCLUSIONS A unbalamced Wilkinson power divider has been designed and implemented using microstrip technology on a Duroid substrate. The divider exhibits excellent power division within 0.3% of ideal at each port. The average return loss is only dB, and isolation between output ports at 10.4 GHz is 49.5 db. The entire design fits an aea less than one square inch and utilizes a common 0805 chip resistor for the isolation resistor. The design achieved all design objectives while using little area and a common resistor. REFERENCES [1] David M. Pozar, Microwave Engineering, 3rd Edition, 2005.