1. Introduction to SOPC Builder

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1 1. Introduction to SOPC Builder QII Quick Start Guide For a quick introduction on how to use SOPC Builder, ollow these general steps: Install the Quartus II sotware, which includes SOPC Builder. This is available at Take advantage o the one-hour online course, Using SOPC Builder. Download and run the checksum sample design described in the SOPC Builder Memory Subsystem Development Walkthrough chapter in volume 4 o the Quartus II Handbook. Overview SOPC Builder is a powerul system development tool. SOPC Builder enables you to deine and generate a complete system-on-a-programmable-chip (SOPC) in much less time than using traditional, manual integration methods. SOPC Builder is included as part o the Quartus II sotware. You may have used SOPC Builder to create systems based on the Nios II processor. However, SOPC Builder is more than a Nios II system builder; it is a general-purpose tool or creating systems that may or may not contain a processor and may include a sot processor other than the Nios II processor. SOPC Builder automates the task o integrating hardware components. Using traditional design methods, you must manually write HDL modules to wire together the pieces o the system. Using SOPC Builder, you speciy the system components in a GUI and SOPC Builder generates the interconnect logic automatically. SOPC Builder generates HDL iles that deine all components o the system, and a top-level HDL ile that connects all the components together. SOPC Builder generates either Verilog HDL or VHDL equally. In addition to its role as a system generation tool, SOPC Builder provides eatures to ease writing sotware and to accelerate system simulation. This chapter includes the ollowing sections: Architecture o SOPC Builder Systems on page 1 2 Functions o SOPC Builder on page 1 5 Operating System Support on page 1 6 Talkback Support on page 1 7 March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 4: SOPC Builder

2 1 2 Chapter 1: Introduction to SOPC Builder Architecture o SOPC Builder Systems Architecture o SOPC Builder Systems SOPC Builder Modules An SOPC Builder component is a design module that SOPC Builder recognizes and can automatically integrate into a system. You can also deine and add custom components or select rom a list o provided components. SOPC Builder connects multiple modules together to create a top-level HDL ile called the SOPC Builder system. SOPC Builder generates system interconnect abric that contains logic to manage the connectivity o all modules in the system. 1 This document reers to components as the class deinition or a module, while module is the instance o the component class. SOPC Builder modules are the building blocks or creating an SOPC Builder system. SOPC Builder modules use Avalon interaces, such as memory-mapped, streaming, and IRQ, or the physical connection o components. You can use SOPC Builder to connect any logical device (either on-chip or o-chip) that has an Avalon interace. There are dierent types o Avalon interaces, as described in the Avalon Interace Speciications. For details on the Avalon-MM interace reer to System Interconnect Fabric or Memory-Mapped Interaces in chapter in volume 4 o the Quartus II Handbook. For details on the Avalon-ST interace, reer to the System Interconnect Fabric or Streaming Interaces chapter in volume 4 o the Quartus II Handbook. For details about the Avalon-ST interace protocol, reer to Avalon Interace Speciications. Example System Figure 1 1 shows an FPGA design that includes an SOPC Builder system and custom logic modules. You can integrate custom logic inside or outside the SOPC Builder system. In this example, the custom component inside the SOPC Builder system communicates with other modules through an Avalon-MM master interace. The custom logic outside o the SOPC Builder system is connected to the SOPC Builder system through a PIO interace. The SOPC Builder system includes two SOPC Builder components with Avalon-ST source and sink interaces. The system interconnect abric connects all o the SOPC Builder components using the Avalon-MM or Avalon-ST system interconnect as appropriate. Quartus II Handbook Version 9.0 Volume 4: SOPC Builder March 2009 Altera Corporation

3 Chapter 1: Introduction to SOPC Builder 1 3 Architecture o SOPC Builder Systems Figure 1 1. Example o an FPGA with a SOPC Builder System Generated by SOPC Builder Printed Circuit Board FPGA System Module Custom Component Processor (32-bit Master) Streaming Data Sink M M SNK Custom Logic System Interconnect Fabric S S SRC PIO (8-bit slave) DDR2 Memory Controller Streaming Data Source Bus Bridge DDR2 Memory Co-Processor DDR2 2 Memory M S Avalon-MM Master Port Avalon-MM Slave Port SRC Avalon-ST Source Port SNK Avalon-ST Sink Port A component can be a logical device that is entirely contained within the SOPC Builder system, such as the processor component shown in Figure 1 1. Alternately, a component can act as an interace to an o-chip device, such as the DDR2 interace component in Figure 1 1. In addition to the Avalon interace, a component can have other signals that connect to logic outside the SOPC Builder system. Non-Avalon signals can provide a special-purpose interace to the SOPC Builder system, such as the PIO in Figure 1 1. These non-avalon signals are described in Conduit Interace chapter in the Avalon Interace Speciications. Available Components Altera and third-party developers provide ready-to-use SOPC Builder components, including: Microprocessors, such as the Nios II processor March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 4: SOPC Builder

4 1 4 Chapter 1: Introduction to SOPC Builder Architecture o SOPC Builder Systems Microcontroller peripherals, such as a Scatter-Gather DMA Controller and timer Serial communication interaces, such as a UART and a serial peripheral interace (SPI) General purpose I/O Communications peripherals, such as a 10/100/1000 Ethernet MAC Interaces to o-chip devices Custom Components You can import HDL modules and entities that you write using Verilog HDL or VHDL into SOPC builder as custom components. You use the ollowing design low to integrate custom logic into an SOPC Builder system: 1. Determine the interaces used to interact with your custom component. 2. Create the component logic using either Verilog HDL or VHDL. 3. Use the SOPC Builder component editor to create an SOPC Builder component with your HDL iles. 4. Instantiate your component in the system. Once you have created an SOPC Builder component, you can use the component in other SOPC Builder systems, and share the component with other design teams. For instructions on developing a custom SOPC Builder component, the details about the ile structure o a component, or the component editor, reer to the SOPC Builder Components chapter in volume 4 o the Quartus II Handbook. For urther details, reer to the System Interconnect Fabric or Memory-Mapped Interaces and System Interconnect Fabric or Streaming Interaces chapters in volume 4 o the Quartus II Handbook. Third-Party Components You can also use SOPC-ready components that were developed by third-parties. Altera awards the SOPC Builder Ready certiication to IP unctions that are ready to integrate with the Nios II embedded processor or the system interconnect abric via SOPC Builder. These cores support the Avalon-MM interace or the Avalon Streaming (Avalon-ST) interace and include constraints, sotware drivers, and simulation models when applicable. To ind third-party components that you can purchase and use in SOPC Builder systems, complete the ollowing steps: 1. On the Tools menu in SOPC Builder, click Download Components. 2. On the Intellectual Property Solutions web page, type SOPC Builder ready r in the box labeled Search or IP, Development Kits and Reerence Designs. Quartus II Handbook Version 9.0 Volume 4: SOPC Builder March 2009 Altera Corporation

5 Chapter 1: Introduction to SOPC Builder 1 5 Functions o SOPC Builder Functions o SOPC Builder This section describes the unctions o SOPC Builder. Deining and Generating the System Hardware SOPC Builder allows you to design the structure o a hardware system. The GUI allows you to add components to a system, conigure the components, and speciy connectivity. Ater you add and parameterize components, SOPC Builder generates the system interconnect abric, and outputs HDL iles to your project directory. During system generation, SOPC Builder creates the ollowing items: An HDL ile or the top-level SOPC Builder system and or each component in the system. The top-level HDL ile is named <system_name>v or Verilog HDL designs and <system_name>.vhd or VHDL designs. Synopsis Design Constraints ile (.sdc) or timing analysis. A Block Symbol File (.bs) representation o the top-level SOPC Builder system or use in Quartus II Block Diagram Files (.bd). An example o an instance o the top-level HDL ile, <SOPC_project_name_inst>.v or <SOPC_project_name_inst>.vhd, which demonstrates how to instantiate the top-level HDL ile in your code. A data sheet called <system_name>.html that provides a system overview including the ollowing inormation: All external connections or the system A memory map showing the address o each Avalon-MM slave with respect to each Avalon-MM master to which it is connected All parameter assignments or each component A unctional test bench or the SOPC Builder system and ModelSim simulation project iles SOPC Builder inormation ile (.sopcino) that describes all o the components and connections in your system. This ile is a complete system description, and is used by downstream tools such as the Nios II tool chain. It also describes the parameterization o each component in the system; consequently, you can parse its contents to get requirements when developing sotware drivers or SOPC Builder components. A Quartus II IP File (.qip) that provides the Quartus II sotware with all required inormation about your SOPC Builder system. The.qip ile includes reerences to the ollowing inormation: HDL iles used in the SOPC Builder system TimeQuest Timing Analyzer Synopsys Design Constraint (.sdc) iles Component deinition iles or archiving purposes Ater you generate the SOPC Builder system, you can compile it with the Quartus II sotware, or you can instantiate it in a larger FPGA design. March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 4: SOPC Builder

6 1 6 Chapter 1: Introduction to SOPC Builder Visualization o Large SOPC Builder Systems Creating a Memory Map or Sotware Development When your SOPC Builder system includes a Nios II processor, SOPC Builder generates a header ile, cpu.h, that provides the base address o each Avalon-MM slave component. In addition, each slave component can provide sotware drivers and other sotware unctions and libraries or the processor. You can create C header iles or your system using the sopc-create-header-iles utility. For details type sopc-create-header-iles --help in a Nios II Command shell. For more details about how to provide Nios II sotware drivers or components, reer to the Developing Device Drivers or the Hardware Abstraction Layer chapter o the Nios II Sotware Developer s Handbook. The Nios II EDS is separate rom SOPC Builder, but it uses the output o SOPC Builder as the oundation or sotware development. Creating a Simulation Model and Test Bench You can simulate your system ater generating it with SOPC Builder. During system generation, SOPC Builder outputs a simulation test bench and a ModelSim setup script that eases the system simulation eort. The test bench does the ollowing: Instantiates the SOPC Builder system Drives all clocks and resets Instantiates simulation models or o-chip devices when available Visualization o Large SOPC Builder Systems Operating System Support For large systems, you can use the Filters dialog box to customize the display o your system in the connections panel. You can ilter the display o your system by interace type, module name, interace type, or using custom tags. For example, you can use iltering to view only components that include an Avalon-MM interace or components that are connected to a particular Nios II processor. For more inormation, reer to Quartus II online Help. SOPC Builder supports all o the operating systems that the Quartus II sotware supports. For more inormation reer to Quartus II Installation & Licensing or Windows and Linux Workstations. Quartus II Handbook Version 9.0 Volume 4: SOPC Builder March 2009 Altera Corporation

7 Chapter 1: Introduction to SOPC Builder 1 7 Talkback Support Talkback Support Reerenced Documents Talkback is a Quartus II sotware eature that provides eedback to Altera on tool and IP eature usage. Altera uses the data to help guide uture product planning eorts. Talkback sends Altera inormation on the components used, interace types, interace properties, parameter names and values, clocking, and sotware assignments. The Talkback ile does not include inormation about system connectivity, interrupts or the memory map seen by each master in the system. When problems arise in the Quartus II sotware, Talkback data also helps Altera ind and ix the cause. The Talkback eature is enabled by deault. You can disable Talkback i you do not wish to share your tool usage data with Altera. This chapter reerences the ollowing documents: Avalon Interace Speciications Component Editor chapter in volume 4 o the Quartus II Handbook Conduit Interace chapter in the Avalon Interace Speciication Developing Device Drivers or the Hardware Abstraction Layer chapter o the Nios II Sotware Developer s Handbook Nios II Hardware Development Tutorial SOPC Builder Components chapter in volume 4 o the Quartus II Handbook System Interconnect Fabric or Memory-Mapped Interaces chapter in volume 4 o the Quartus II Handbook System Interconnect Fabric or Streaming Interaces chapter in volume 4 o the Quartus II Handbook March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 4: SOPC Builder

8 1 8 Chapter 1: Introduction to SOPC Builder Document Revision History Document Revision History Table 1 1. Document Revision History Table 1 1 shows the revision history or this chapter. Date and Document Version Changes Made Summary o Changes March 2009, v9.0.0 November 2008, v8.1.0 Added sopc-create-header-iles command Added description o Generate HTML Data Sheet Added instructions or downloading third-party IP. Named top-level HDL system iles that SOPC Builder generates. Added paragraph introducing the iltering or visualization o large systems. Expanded description o.sopcino ile Changed page size to 8.5 x 11 inches May 2008, v8.0.0 Updated reerences to Avalon Memory-Mapped and Streaming Interace Speciications and changed to Avalon Interace Speciications. Add Quick Start Guide. Add list o OS support. Updated to relect new unctionality in the 9.0 release. The two speciications have been combined into one or all Avalon interaces. For previous versions o the Quartus II Handbook, reer to the Quartus II Handbook Archive. Quartus II Handbook Version 9.0 Volume 4: SOPC Builder March 2009 Altera Corporation