1 ALTADVSEU Subscribe The Altera Advanced SEU Detection IP core contains the following features: Hierarchy tagging Enables tagging of logical hierarchies and specifying their criticality relative to SEU. Sensitivity processing Determines the criticality of an SEU detected and located by error detection cyclical redundancy check (EDCRC) hard IP. This feature includes on and off-chip sensitivity processing. Table 1: Features Device Family Support Feature Hierarchy tagging Sensitivity processing Supported Device Stratix IV, Arria V, Arria V GZ, Cyclone V, Stratix V and later. Arria V, Arria V GZ,Cyclone V, Stratix V and later. You can select and configure the Altera Advanced SEU Detection IP core through the IP Catalog and parameter editor in the Quartus II software. Related Information Introduction to Altera IP Cores Functional Description Stratix IV devices contain a 16-bit cyclic redundancy check (CRC) value per CRAM frame, and Arria V, Cyclone V, Stratix V, and later device families contain a 32-bit CRC value per CRAM frame. The CRC value allows the configuration engine to determine the SEU location. The Quartus II software can generate a Sensitivity Map Header File (.smh) of the configuration regions of your design that are sensitive to SEU. You can instantiate the Altera Advanced SEU Detection IP core with the following configurations: On-Chip Lookup Sensitivity Processing Error location reporting and lookup performed by the FPGA. Off-Chip Lookup Sensitivity Processing Error location lookup determined by an external unit (such as a microprocessor). On-Chip Lookup Sensitivity Processing All device families that support SEU detection include a hard error detection block that detects soft errors and provides the location of single-bit errors, and double-bit adjacent errors for supported devices. The All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered 101 Innovation Drive, San Jose, CA 95134
2 2 On-Chip Lookup Sensitivity Processing Altera Advanced SEU Detection IP core interprets the error detection register of the error detection block, and then compares single-bit error locations with a sensitivity map. This check determines whether or not the failure affects the device operation. Figure 1: System Overview for On-Chip Lookup Sensitivity Processing ALTADVSEU FPGA EMR Unloader IP Core Error Messages Register Interface Advanced SEU Detection IP Core CRAM CRC Error Detected Memory Interface User-Supplied Memory Access Logic critical_error noncritical_error regions_report Sensitivity Lookup Information (SMH) Stored in External Memory CRC_ERROR The Altera Advanced SEU Detection IP core accepts the content of the error message register (EMR) and issues a query to an external memory containing the sensitivity map. The system designer is responsible for the memory access logic and external memory. Altera recommends that you implement an SEU detection circuit that tolerates a soft error in its logic by instantiating two instances of the Altera Advanced SEU Detection IP core in your design. In this case, one instance of the IP core flags errors that occur in the other instance of the IP core as critical. Related Information Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Provides more information about the design security for Stratix IV devices. Configuration, Design Security, and Remote System Upgrades in Arria V Devices Provides more information about the design security for Arria V devices. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Provides more information about the design security for Cyclone V devices. Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Provides more information about the design security for Stratix V devices.
3 ALTADVSEU On-Chip Processing Signals 3 On-Chip Processing Signals Figure 2: Altera Advanced SEU Detection Core Signals for On-Chip Processing my_asd address mem_addr[31:0] clk clk read mem_rd byteenable mem_bytesel[3:0] reset reset waitrequest mem_wait readdata mem_data[31:0] cache_comparison_off cache_comparison_off readdatavalid mem_datavalid emr[66:0] emr_valid emr_error data valid error critical_error noncritical_error regions_report critical_error noncritical_error regions_report Altera Advanced SEU Detection IP Core Table 2: Altera Advanced SEU Detection Core Signals for On-Chip Processing Interface Signals Type Width Description Clock and reset Cache Configuration Avalon-ST (Streaming) Sink Interface Signals (1) clk Input 1 Clock input. Recommended frequency is 100 MHz or higher. reset Input 1 Active-high reset. cache_comparison_off Input 1 Static input signal. Commands the IP core to bypass cache comparison. You can use this signal with the internal scrubbing feature for custom design. emr Input 67 Error Message Register data input from the Altera Error Message Register Unloader IP core. emr_valid Input 1 Indicates when emr data input is valid. emr_error Input 1 Indicates when emr data will be ignored due to an error. This may occur when there is a data overrun from the Altera EMR Unloader IP core. (1) The Avalon (ST) Streaming Sink Interface should be connected to the corresponding Avalon-ST Source Interface of the EMR Uploader IP Core.
4 4 On-Chip Processing Signals ALTADVSEU Interface Signals Type Width Description Errors Output noncritical_error critical_error regions_report Outpu t Outpu t Outpu t 1 Indicates that an SMH lookup determined that the EDCRC error is in a non-critical region. 1 Indicates that an SMH lookup determined that the EDCRC error is in a critical region. 1 The ASD region for the error, as reported by the SMH lookup. The width of this port comes from the setting for the parameter Largest ASD region ID used. mem_addr mem_rd Outpu t Outpu t Output to the user logic. Byte address of the 32-bit word to be read. Output to the user logic. Signals to the user logic to request a read operation. External Memory Avalon-MM Master mem_bytesel Outpu t Output to the user logic. A four-bit signal that selects the bytes needed by the IP core. Use of this signal allows 16-bit or 8-bit memories to optimize the number of reads in cases where the IP does not need all 32 bits. If bit 0 of mem_ bytesel is 0, then the IP core ignores bits 0 to 7 of mem_data, and similarly for bits 1 to 3 of mem_bytesel. mem_wait Input Input from the user logic. Signals to the memory interface that the read operation is still running. Must be high by the first rising clock after mem_rd is asserted to hold the IP core in a wait state. mem_data Input Input from the user logic. 32-bit data bus. Data must be present if mem_wait goes high and if mem_rd returns low. mem_datavalid Input Input from the user logic. Signals that the mem_data signal contains valid data in response to a previous mem_rd request. Related Information Altera Error Message Register Unloader IP Core User Guide
5 ALTADVSEU Off-Chip Lookup Sensitivity Processing 5 Off-Chip Lookup Sensitivity Processing The Altera Advanced SEU Detection IP core interprets the content of the error detection block s EMR and presents information to a system processor, which determines whether the failure affects the device operation. The system processor implements the algorithm to perform a lookup against the.smh. The off-chip lookup sensitivity processing consists of two components: Design logic to interpret content of the EMR of the CRC block and present the information to a processor interface. Cache to store off-loaded content of the EMR. Figure 3: System Overview for Off-Chip Lookup Sensitivity Processing FPGA Sensitivity Lookup Information (SMH) Stored in System Memory EMR Unloader IP Core Error Message Register Interface CRAM CRC Error Detected Advanced SEU Detection IP Core Error Message Cache Interface Sensitivity Processor (e.g., System CPU) CRC_ERROR The EMR processing unit interprets the content of EMR offloaded from the CRC block by the EMR Uploader IP core upon an SEU. The EMR processing unit writes each unique EMR value into cache, until the cache is full. After the cache is full, it asserts a cache overflow flag to the system interface. For each new value written into cache, the EMR processing unit asserts an interrupt to the processor. The system processor reads the EMR value and performs a lookup against the.smh to determine the criticality of a CRAM location. After the system processor services the interrupt, the EMR processing unit advances the cache line and generates additional interrupt assertions, provided that there is an EMR value in cache that has not been processed. After SMH lookup, the system processor determines the required corrective response. Related Information Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Provides more information about the design security for Stratix IV devices. Configuration, Design Security, and Remote System Upgrades in Arria V Devices Provides more information about the design security for Arria V devices. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Provides more information about the design security for Cyclone V devices. Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Provides more information about the design security for Stratix V devices.
6 6 Off-Chip Lookup Sensitivity Processing Operation Flow Off-Chip Lookup Sensitivity Processing Operation Flow Figure 4: Off-Chip Lookup Sensitivity Processing Operation Flow ALTADVSEU EMR Processing Unit Wait for SEU CRC Error Writes a Value into EMR Logic Caches EMR; Asserts Interupt to CPU SMH File CPU Reads SMH Log Event Bit Critical? no yes Corrective Action Needed? no yes System-Level Response Reset System Related Information SMH Lookup on page 8 Off-Chip Processing Signals Off-chip sensitivity processing has similar signals with on-chip sensitivity processing, with the exception of the external memory interface; the off-chip sensitivity processing has EMR cache interface instead.
7 ALTADVSEU Off-Chip Processing Signals 7 Figure 5: Altera Advanced SEU Detection Core Signals for Off-Chip Processing my_asd clk clk data cache_data[34:0] valid cache_valid reset reset ready error cache_ready cache_error cache_comparison_off cache_comparison_off cache_fill_level cache_fill_level[3:0] emr[66:0] emr_valid emr_error data valid error critical_error critical_error Altera Advanced SEU Detection IP Core Table 3: Altera Advanced SEU Detection Core Signals for Off-Chip Processing Interface Signals Type Width Description Clock and reset Cache Configuration Avalon-ST (Streaming) Sink Interface Signals (2) clk Input 1 Clock input. Recommended frequency is 100 MHz or higher. reset Input 1 Active-high reset. cache_comparison_off Input 1 Static input signal. Commands the IP core to bypass cache comparison. You can use this signal with the internal scrubbing feature for custom design. emr Input 67 Error Message Register data input from the Altera Error Message Register Unloader IP core. emr_valid Input 1 Indicates when emr data input is valid. emr_error Input 1 Indicates when emr data will be ignored due to an error. This may occur when there is a data overrun from the Altera EMR Unloader IP core. Errors Output critical_error Outpu t 1 Indicates that an SMH lookup determined that the EDCRC error is in a critical region. (2) The Avalon (ST) Streaming Sink Interface should be connected to the corresponding Avalon-ST Source Interface of the EMR Uploader IP Core.
8 8 SMH Lookup ALTADVSEU Interface Signals Type Width Description External Memory Avalon-MM Master cache_data cache_valid Outpu t Outpu t 34 Error cache data. This is the location information for an EMR cache entry. 1 Indicates when the cache_data contents are valid. cache_ready Input 1 Indicates that the reader of the Avalon Stream interface is ready. cache_error Outpu t Cache Status cache_fill_level Outpu t SMH Lookup Related Information Altera Error Message Register Unloader IP Core User Guide 1 This Avalon stream control signal indicates the current transfer is in error and should be ignored. 4 Indicates how many entries are in the cache. The.smh file represents a hash of the CRAM bit settings on a design. Related groups of CRAM are mapped to a signal bit in the sensitivity array. During an SEU event, a design can perform a lookup against the.smh to determine if a bit is used. By using the information about the location of a bit, you can reduce the effective soft error rate in a running system. The following criteria determine the criticality of a CRAM location in your design: Routing All bits that control a utilized routing line. Adaptive logic modules (ALMs) If you configure an ALM, then the megafunction considers all CRAM bits related to that ALM sensitive. Logic array block (LAB) control lines If you use an ALM in a LAB, then the megafunction considers all bits related to the control signals feeding that LAB sensitive. M20K memory blocks and digital signal processing (DSP) blocks If you use a block, then the megafunction considers all CRAM bits related to that block sensitive. Related Information Off-Chip Lookup Sensitivity Processing Operation Flow on page 6 Types of SMH Files The.smh is an Intel-format Hexadecimal file. You can generate two revisions of.smh files: Revision 1 Generated for Stratix IV family devices. This revision does not support hierarchy tagging, and does not contain tag size or region map information. Revision 2 Generated for Arria V, Cyclone V, and Stratix V, and later device families. The generated.smh contains tag size and region map information.
9 ALTADVSEU Revision 1 SMH 9 Revision 1 SMH Figure 6: Revision 1 SMH Sensitivity Data Array Offset Maps Frame Information Array 0x single_offset_map_length sensitivity_data_array Base Address Header Information offset_map Base Address frame_info Base Address 32-bit ID: 0x x In revision 1 files, the sensitivity map header starts from 160-bit header information that provides basic information about the.smh format. This includes the base addresses for the frame information, offset maps and length of the single offset map, and the sensitivity data array. Frame information array contains a 32-bit string for each frame in the device. The frame number serves as the index for the frame information string. Each frame information string provides the following information: offset_map_array_index (Bits 7:0) the index for the offset map array that this frame uses. frame_info_data_offset (Bits 31:8) a 24-bit address offset into the sensitivity array for this frame. Offset map array The offset map information array is a set of arrays containing 16-bit offset maps. Each offset map value represents an additional offset into the sensitivity array for a frame group. Each offset map value is 16 bits. The offset_map_length string in the header information defines the size of each offset map array. Sensitivity data array The sensitivity data array is a flat-bit vector where 1 specifies a sensitive bit and 0 specifies an insensitive bit.
10 10 Revision 2 SMH Revision 2 SMH Figure 7: Revision 2 SMH ALTADVSEU Region Map Sensitivity Data Array Offset Maps Frame Info Header Information Reserved SOF 32 bit CRC Signature region_map Base Adress sensitivity_data_tag_size single_offset_map_length sensitivity_data_array Base Address offset_map Base Address frame_info Base Address 32 bit ID: 0xXX x In revision 2 files, the sensitivity map header is an extension of revision 1 header format. The header information provides basic information about the.smh revision 2, and includes all the revision 1 header information fields. The additional fields include size of the sensitivity data tag size in bits, base addresses for the region map, and 32-bit CRC signature of the corresponding.sof file. The 32-bits ID of the sensitivity map header revision 2 is defined as follows: Bits 23:0 Altera sensitivity map header ID 0x Bits 24:31 a bit mask for the header information with bit 24 reserved Bit 25 indicates the presence of sensitivity tag information in the.smh Bits 27:26 reserved Bit 28 indicates the presence of 32-bit CRC signature of corresponding.sof Bits 29:31 reserved
11 ALTADVSEU Getting Started with Altera Altera Advanced SEU Detection IP Core 11 Frame information array contains a 32-bit string for each frame in the device. The frame number serves as the index for the frame information string. Each frame information string provides the following information: offset_map_array_index (Bits 7:0) the index for the offset map array that this frame uses. frame_info_data_offset (Bits 31:8) a 24-bit address offset into the sensitivity array for this frame. Offset map array The offset map information array is a set of arrays containing 16 bit offset maps. Each offset map value represents an additional offset into the sensitivity array for a frame group. Each offset map value is 16 bits. The size of each offset map array is defined by the offset_map_length string contained in the header information. Sensitivity data array The size of the single sensitivity data entry or tag (sensitivity_data_tag_size) is in bits and aligned to power of 2. The sensitivity data array is a flat sensitivity tag vector where a sensitive tag of 0 specifies a bit insensitive for all regions, and non-zero tag specifies an offset into region map. Region map information array The region map information array contains a 16-bit string for each non-zero sensitivity tag. The sensitivity data tag serves as the index-1 for the region map array. The string is a bitmask of the regions, the bit is sensitive for. Each region can be identified in the bitmask by mask 1 << (Region ID - 1). Table 4: Revision 2 SMH File Size and ASD Regions Based on Sensitivity Tag These SMH sizes are for Stratix V 5SGXEA7 device with a SOF size of 31,731,193 bytes. Number of ASD Regions Sensitivity Tag Size (bits) SMH Size (bytes) 1 1 2,296, ,984, ,361, ,114,024 Getting Started with Altera Altera Advanced SEU Detection IP Core The Altera Advanced SEU Detection IP core must be used along with the Altera EMR Unloader IP core. The Altera EMR Unloader IP core provides Error Message Register (EMR) contents whenever it detects an EDCRC error. Connect the EMR, EMR_valid and EMR_error signals from your Altera EMR Unloader IP variation to the corresponding inputs of your Altera Advanced SEU Detection IP variation. Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore IP functions require that you purchase a separate license for production use. However, the OpenCore feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software. After you are satisfied with functionality and perfformance, visit the Self Service Licensing Center to obtain a license number for any Altera product.
12 12 Customizing and Generating IP Cores ALTADVSEU Figure 8: IP Core Installation Path acds quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores altera - Contains the Altera IP Library source code <IP core name> - Contains the IP core source files Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is <home directory>/altera/ <version number>. Related Information Altera Licensing Site Altera Software Installation and Licensing Manual Customizing and Generating IP Cores You can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog and parameter editor allow you to quickly select and configure IP core ports, features, and output files. IP Catalog and Parameter Editor The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation. Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard Plug-In Manager for IP selection and parameterization, beginning in Quartus II software version Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores. The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. You can also parameterize an IP variation without an open project. Use the following features to help you quickly locate and select an IP core: Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog. Type in the Search field to locate any full or partial IP core name in IP Catalog. Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation. Click Search for Partner IP, to access partner IP information on the Altera website.
13 ALTADVSEU Using the Parameter Editor 13 Figure 9: Quartus II IP Catalog Search for installed IP cores Show IP only for target device Double-click to customize, right-click for detailed information Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer to Creating a System with Qsys in the Quartus II Handbook. Using the Parameter Editor The parameter editor helps you to configure IP core ports, parameters, and output file generation options. Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values for specific applications. View port and parameter descriptions, and links to documentation. Generate testbench systems or example designs (where provided).
14 14 Specifying IP Core Parameters and Options Figure 10: IP Parameter Editors ALTADVSEU View IP port and parameter details Legacy parameter editors Specify your IP variation name and target device Apply preset parameters for specific applications Specifying IP Core Parameters and Options Follow these steps to specify IP core parameters and options. 1. In the Qsys IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears. 2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Altera device family and output file HDL preference. Click OK. 3. Specify parameters and options for your IP variation: Optionally select preset parameter values. Presets specify all initial parameter values for specific applications (where provided). Specify parameters defining the IP core functionality, port configurations, and device-specific features. Specify options for generation of a timing netlist, simulation model, testbench, or example design (where applicable). Specify options for processing the IP core files in other EDA tools. 4. Click Finish to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level.qsys IP variation file and HDL files for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing. 5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate Testbench System is not available for some IP cores that do not provide a simulation testbench. 6. To generate a top-level HDL example for hardware verification, click Generate > HDL Example. Generate > HDL Example is not available for some IP cores. The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in Project to manually add a.qsys file to a project. Make appropriate pin assignments to connect ports.
15 ALTADVSEU Files Generated for Altera IP Cores 15 Files Generated for Altera IP Cores The Quartus II software generates the following IP core output file structure: Figure 11: IP Core Generated Files <project directory> <your_ip>.qsys - System or IP integration file <your_ip>.sopcinfo - Software tool-chain integration file <your_ip> <your_ip> n IP variation files IP variation files <your_ip>.cmp - VHDL component declaration file <your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or.vhd - Sample instantiation template <your_ip>.ppf - XML I/O pin information file <your_ip>.qip - Lists IP synthesis files <your_ip>.sip - Contains assingments for IP simulation files <your_ip>_generation.rpt - IP generation report <your_ip>.debuginfo - Contains post-generation information <your_ip>.html - Connection and memory map data <your_ip>.bsf - Block symbol schematic <your_ip>.spd - Combines simulation scripts for multiple cores <testbench>_tb testbench system <testbench>_tb testbench files sim simulation files <EDA tool setup scripts> <your_ip>_tb.qsys Testbench system file <your_testbench>_tb.csv <your_testbench>_tb.spd sim Simulation files synth IP synthesis files <ip subcores> n Subcore libraries <EDA tool name> Simulator scripts <your_ip>.v or.vhd Top-level simulation file <simulator_setup_scripts> <your_ip>.v or.vhd Top-level IP synthesis file synth Subcore synthesis files <HDL files> sim Subcore Simulation files <HDL files> Table 5: IP Core Generated Files File Name Description <my_ip>.qsys The Qsys system or top-level IP variation file. <my_ip> is the name that you give your IP variation.
16 16 Files Generated for Altera IP Cores ALTADVSEU File Name <system>.sopcinfo <my_ip>.cmp <my_ip>.html <my_ip>_generation.rpt <my_ip>.debuginfo <my_ip>.qip <my_ip>.csv <my_ip>.bsf <my_ip>.spd <my_ip>.ppf <my_ip>_bb.v <my_ip>.sip <my_ip>_inst.v or _inst.vhd Description Describes the connections and IP component parameterizations in your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components. Downstream tools such as the Nios II tool chain use this file. The.sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component. The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files. A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments. IP or Qsys generation log file. A summary of the messages during IP generation. Contains post-generation information. Used to pass System Console and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect. Contains all the required information about the IP component to integrate and compile the IP component in the Quartus II software. Contains information about the upgrade status of the IP component. A Block Symbol File (.bsf) representation of the IP variation for use in Quartus II Block Diagram Files (.bdf). Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The.spd file contains a list of files generated for simulation, along with information about memories that you can initialize. The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner. You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box. Contains information required for NativeLink simulation of IP components. You must add the.sip file to your Quartus project. HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.
17 ALTADVSEU Files Generated for Altera IP Cores 17 File Name <my_ip>.regmap <my_ip>.svd <my_ip>.v or Description If the IP contains register information, the.regmap file generates. The.regmap file describes the register map information of master and slave interfaces. This file complements the.sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in System Console. Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system. During synthesis, the.svd files for slave interfaces visible to System Console masters are stored in the.sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name. HDL files that instantiate each submodule or child IP core for synthesis or simulation. <my_ip>.vhd mentor/ aldec/ /synopsys/vcs /synopsys/vcsmx /cadence Contains a ModelSim script msim_setup.tcl to set up and run a simulation. Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation. Contains a shell script vcs_setup.sh to set up and run a VCS simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX simulation. Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation. /submodules Contains HDL files for the IP core submodule. <child IP cores>/ For each generated child IP core directory, Qsys generates /synth and / sim sub-directories.
18 18 Altera Advanced SEU Detection IP Core Parameters ALTADVSEU Altera Advanced SEU Detection IP Core Parameters Parameter Group Name Parameter Legal Value CRC error cache depth 2, 4, 8,16, 32, 64 Description Specifies how many non-critical cyclic redundancy check (CRC) error to ignore. Default value is 8. General Largest ASD region ID 1 to 16 Indicates the largest ASD SEU detection region ID in your design. Configures the width of the regions_report port. Default value is 1. Sensitivity Data Access Use on-chip sensitivity processing Memory interface address width Sensitivity data start address ON, OFF Configures the IP core to use on-chip sensitivity processing or off-chip sensitivity processing. When enabled, implements an external memory interface in the IP. Specifies width of the address bus connected to the external memory interface. Default value is 32. Specifies the offset added to all addresses the external memory interface generates. Default value is 0x0. SEU Mitigation on CRAM Array Critical applications require an SEU recovery strategy. The Quartus II software provides SEU detection, and allows you to design a recovery response to reduce SEU disruption. Enabling the Advanced SEU Detection Feature in the Quartus II Software To enable the Advanced SEU Detection feature in the Quartus II software and generate an.smh, turn on Generate SEU sensitivity map file (.smh) in the Device and Pin Options dialog box (Assignments > Device > Device and Pin Options). Hierarchy Tagging The Quartus II hierarchy tagging feature enables customized soft error classification by indicating design logic susceptible to soft errors. Hierarchy tagging improves design-effective FIT rate by tagging only the critical logic for device operation. You also define the system recovery procedure based on knowledge of logic impaired by SEU. This technique reduces downtime for the FPGA and the system in which the FPGA resides. Hierarchy tagging is available only for Arria V, Cyclone V, Stratix V, and later device families.
19 ALTADVSEU Using Partitions to Specify Logic Sensitivity ID 19 The.smh contains a mask for design sensitive bits in a compressed format. The sensitivity mask is generated for the entire design. Hierarchy tagging provides the following benefits: Hierarchy tagging provides the following benefits: Increases system stability by avoiding disruptive recovery procedures for inconsequential errors. Allows diverse corrective action for different design logic. Using Partitions to Specify Logic Sensitivity ID In the Quartus II software, you can designate a design block as a design partition. You can then assign a sensitivity value to the partition. The PARTITION_ASD_REGION_ID global assignment specifies the numeric value from 0 to 16. The value represents the sensitivity tag associated with this partition: set_global_assignment -name PARTITION_ASD_REGION_ID <asd_id> -section_id <partition_name> A sensitivity tag of 1 is the same as no PARTITION_ASD_REGION_ID assignment, specifying basic sensitivity level: "region used in design". If a soft error occurs in this partition, the error is reported back as a critical error in the sensitivity region 1. A sensitivity tag of 0 is reserved, as indication that CRAM bits are not used in your design. You can explicitly set it to indicate that partition is not-critical, and force the partition to be completely excluded from the sensitivity mapping. Note: You can create multiple partitions with the same sensitivity tag in a design. Design Partitions Properties Specify the sensitivity ID assigned to the partition in the ASD Region column in the Design Partition window. Figure 12: ASD Region Column in the Design Partition Window Sensitivity Map Header File Lookup The.smh contains critical bit information about the design. The sensitivity data is generated as a standard Intel hex (big-endian).smh file during.sof generation.
20 20 Programming a Sensitivity Map Header File into a Memory Programming a Sensitivity Map Header File into a Memory You can program a.smh into any type of memory. For example, to use CFI flash memory, follow these steps: 1. Rename the.smh to <file_name>.hex, or convert it to little-endian <file_name>.hex if required. 2. In the Quartus II software, click File > Convert Programming Files. 3. In the Convert Programming Files window under Output programming file, select the desired options. 4. To add hex data, follow these steps: Figure 13: Add Hex Data Dialog Box ALTADVSEU a. Click Add Hex Data. b. In the Add Hex Data dialog box, turn on Set start address and enter a start address. c. In the Hex file box, click browse to select the.hex file, and click OK. 5. Click Generate. Performing a Lookup for SMH Revision 1 To perform a lookup into the sensitivity map header data using a bit, byte, and frame number from an EMR (Stratix IV devices only): 1. Read the 32-bit frame information string for the frame number: Address = 0x14 + (frame*4) Return value = (frame_info_data_offset, offset_map_array_index) 2. Read the offset map information for a frame. The return value for the offset map information is 16 bits: Address = offset_map_base_address + offset array for current frame + offset data value for current byte and bit where,
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2015.05.04 TU-01006 Subscribe This tutorial introduces you to the Qsys system integration tool available with the Quartus II software. This tutorial shows you how to design a system that uses various test
2015.12.15 UG-01173 Subscribe The Altera Fault Injection IP core injects errors into the configuration RAM (CRAM) of an FPGA device. This procedure simulates soft errors that can occur during normal operation
2015.05.04 Quartus II Software and Device Support Release Notes Version 15.0 RN-01080-15.0.0 Subscribe This document provides late-breaking information about the Altera Quartus II software release version
ModelSim-Altera Software Simulation User Guide ModelSim-Altera Software Simulation User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01102-2.0 Document last updated for Altera Complete
2014.09.22 Using Altera MAX Series as Microcontroller I/O Expanders AN-265 Subscribe Many microcontroller and microprocessor chips limit the available I/O ports and pins to conserve pin counts and reduce
Quartus Prime Standard Edition Handbook Volume 3: Verification Subscribe QPS5V3 101 Innovation Drive San Jose, CA 95134 www.altera.com Simulating Altera Designs 1 QPS5V3 Subscribe This document describes
Using the Altera Flash Loader Megafunction with the Quartus II Software AN-370 Subscribe The Altera Flash Loader megafunction IP core is an in-system programming (ISP) solution for Altera serial configuration
February 2011 NII52018-10.1.0 13. Publishing Component Information to Embedded Software NII52018-10.1.0 This document describes how to publish SOPC Builder component information for embedded software tools.
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de firstname.lastname@example.org Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
(DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de email@example.com NIOS II 1 1 What is Nios II? Altera s Second Generation
Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-01145_avmm_dma 101 Innovation Drive San Jose, CA 95134 www.altera.com Datasheet
NIOS CPU Based Embedded Computer System on Programmable Chip COE718: Hardware Software Co-Design of Embedded Systems 1 Lab Objectives BONUS LAB: PART-I This lab has been constructed to introduce the development
Applying the Benefits of on a Chip Architecture to FPGA System Design WP-01149-1.1 White Paper This document describes the advantages of network on a chip (NoC) architecture in Altera FPGA system design.
Altera SoC Embedded Design Suite User Guide Subscribe ug-1137 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Introduction to SoC Embedded Design Suite... 1-1 Overview... 1-1 Linux
Nios II Software Developer s Handbook Nios II Software Developer s Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com NII5V2-13.1 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA,
IP Compiler for PCI Express User Guide IP Compiler for PCI Express User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-PCI10605-2014.08.18 Document publication date: August 2014 2014 Altera
SignalTap II with Verilog Designs 1 Introduction This tutorial explains how to use the SignalTap II feature within Altera s Quartus II software. The SignalTap II Embedded Logic Analyzer is a system-level
2015.06.12 AN-459 Subscribe This application note explains the process of creating and debugging a hardware abstraction layer (HAL) software device driver. The included example of a HAL software device
UG-033105 Subscribe This document describes the Altera -provided megafunction IP core optimized for Altera device architectures. Using megafunctions instead of coding your own logic saves valuable design
20160114 Putting Altera MAX Series in Hibernation Mode Using User Flash Memory AN-547 Subscribe The MAX II, MAX V, and MAX 10 devices can be used in this example application You can completely power down
PROFINET IRT: Getting Started with The Siemens CPU 315 PLC AN-674 Application Note This document shows how to demonstrate a working design using the PROFINET isochronous real-time (IRT) device firmware.
White Paper Engineering Change Order (ECO) Support in Programmable Logic Design A major benefit of programmable logic is that it accommodates changes to the system specification late in the design cycle.
MAX 10 Analog to Digital Converter User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-M10ADC 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents MAX 10 Analog to
Excalibur Web Server Demonstration December 2002, ver. 1.0 Application Note 285 Introduction This document describes the Excalibur web server demonstration design and includes the following topics: Design
Using the Agilent 3070 Tester for In-System Programming in Altera CPLDs AN-628-1.0 Application Note This application note describes how to use the Agilent 3070 test system to achieve faster programming
SignalTap II with Verilog Designs This tutorial explains how to use the SignalTap II feature within Altera s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging
Video and Image Processing Suite January 2006, Version 6.1 Errata Sheet This document addresses known errata and documentation issues for the MegaCore functions in the Video and Image Processing Suite,
Introduction to the Quartus II Software Version 10.0 Introduction to the Quartus II Software Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Introduction to the
ECSE 4770 Computer Hardware Design: Quartus Tutorial Prepared By: Kalyana Sundaram Venkataraman, Soumya Chakraborty, Philip Jacob & Steven Nicholas 1. INTRODUCTION This tutorial session has the goal of
SOPC Builder User Guide SOPC Builder User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01096-1.0 Subscribe 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY,
Quartus II Introduction for VHDL Users This tutorial presents an introduction to the Quartus II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by
Using Nios II Floating-Point Custom Instructions Tutorial 101 Innovation Drive San Jose, CA 95134 www.altera.com TU-N2FLTNGPNT-2.0 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable
USB-Blaster II Download Cable User Guide Subscribe UG-01150 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Setting Up the USB-Blaster II Download Cable...1-1 Supported Devices and
Nios II System Architect Design Nios II System Architect Design 101 Innovation Drive San Jose, CA 95134 www.altera.com TU-01004-2.0 Document last updated for Altera Complete Design Suite version: Document
MAX 10 FPGA Configuration User Guide Subscribe UG-M10CONFIG 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents MAX 10 FPGA Configuration Overview... 1-1 MAX 10 FPGA Configuration Schemes
One-Time Programmable (ALTOTP) Megafunction User Guide November 2009 UG-01059-1.0 This user guide describes the features and behavior of the ALTOTP megafunction. In addition, this user guide briefly describes
CSE467: Project Phase 1 - Building the Framebuffer, Z-buffer, and Display Interfaces Vincent Lee, Mark Wyse, Mark Oskin Winter 2015 Design Doc Due Saturday Jan. 24 @ 11:59pm Design Review Due Tuesday Jan.
Using the On-Chip Signal Quality Monitoring Circuitry (EyeQ) Feature in Stratix IV Transceivers AN-605-1.2 Application Note This application note describes how to use the on-chip signal quality monitoring
May 2011 NII52001-11.0.0 1. Overview o Nios II Embedded Development NII52001-11.0.0 The Nios II Sotware Developer s Handbook provides the basic inormation needed to develop embedded sotware or the Altera
My First Nios II Software My First Nios II Software 101 Innovation Drive San Jose, CA 95134 www.altera.com TU-01003-2.1 Document last updated for Altera Complete Design Suite version: Document publication
15. Introduction to ALTMEMPHY IP Noember 2012 EMI_RM_013-1.2 EMI_RM_013-1.2 The Altera DDR,, and DDR3 SDRAM Controllers with ALTMEMPHY IP proide simplified interfaces to industry-standard DDR,, and DDR3
2015.12.17 Implementing QPI Using the Transceiver Native PHY IP Core in Stratix V Devices AN-687 Subscribe This application note describes how to implement the Intel QuickPath Interconnect (QPI) protocol
2015.04.15 FPGA-based Safety Separation Design for Rapid IEC 61508 Certification an704 Subscribe This design flow significantly reduces the certification efforts for the lifetime of an FPGA-based industrial
Qsys and IP Core Integration Prof. David Lariviere Columbia University Spring 2014 Overview What are IP Cores? Altera Design Tools for using and integrating IP Cores Overview of various IP Core Interconnect
Introduction to the Altera Qsys System Integration Tool For Quartus II 12.0 1 Introduction This tutorial presents an introduction to Altera s Qsys system inegration tool, which is used to design digital
White Paper Introduction This paper presents a rigorous methodology for benchmarking the capabilities of an FPGA family. The goal of benchmarking is to compare the results for one FPGA family versus another
Vivado Hello World Tutorial Embedded Processor Hardware Design September 9, 2013 VIVADO TUTORIAL 1 Table of Contents Requirements... 3 Part 1: Building a Zynq- 7000 Processor Hardware... 3 Introduction...
Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices March 2006, ver. 1.0 Application Note 409 Introduction The altlvds megafunction allows you to instantiate an
Nios II Development Kit Version 5.1 SP1 Release Notes January 2006 Release Notes Overview This document lists the release notes for the Nios II Development Kit version 5.1 Service Pack 1. Release notes
Nios II Classic Software Developer s Handbook Subscribe NII5V2 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Overview of Nios II Embedded Development... 1-1 Prerequisites for Understanding
Debugging with System Console Over TCP/IP AN624-1.0 Application Note This application note describes software that supports debugging your custom SOPC Builder component with the Altera System Console over
Configuration Encryption Usage Guide June 2013 Introduction Technical Note TN1109 All Lattice FPGAs provide configuration data read security, meaning that a fuse can be set so that when the device is read
Video and Image Processing Suite User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-VIPSUITE 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Video and Image
Quartus II Software Questions & Answers Following are the most frequently asked questions about the new features in Altera s Quartus II design software. PowerPlay Power Analysis & Optimization Technology
White Paper Introduction Changes in technology and requirements are leading to FPGAs playing larger roles in defense electronics designs, and consequently are creating both opportunities and risks. The
August 2012 CIII51016-2.2 9. Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family CIII51016-2.2 This chapter describes the configuration, design security, and remote
1 Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT OF FOR THE DEGREE IN Bachelor of Technology In Electronics and Communication
FPGA-Adaptive Software Debug and Performance Analysis WP-01198-1.0 White Paper The availability of devices incorporating hardened ARM applications processors closely coupled to an on-chip FPGA fabric opens
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide Subscribe UG-01101 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Configuration via Protocol (CvP) Implementation
Timing Considerations with VHDL-Based Designs This tutorial describes how Altera s Quartus R II software deals with the timing issues in designs based on the VHDL hardware description language. It discusses
Developing an Application on Core8051s IP-Based Embedded Processor System Using Firmware Catalog Drivers User s Guide Developing an Application on Core8051s IP-Based Embedded Processor System Using Firmware
White Paper Introduction The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps (300 to 800 MHz), 1.5V operation for lower power, and higher densities of 2
BACKGROUNDER Spectra-Q Engine 2010 s 2000 s 1990 s >50K >500K >5M FPGAs and SoCs have taken huge leaps with next-generation capabilities. These include multi-million logic elements, complex interface protocols,
July 2011 ED51006-1.2 8. Hardware Acceleration and ED51006-1.2 This chapter discusses how you can use hardware accelerators and coprocessing to create more eicient, higher throughput designs in OPC Builder.
Chapter 11. Using MAX II User Flash Memory for Data Storage in Manufacturing Flow MII51011-1.1 Introduction Small capacity, non-volatile memory is commonly used in storing manufacturing data (e.g., manufacturer
Von der Hardware zur Software in FPGAs mit Embedded Prozessoren Alexander Hahn Senior Field Application Engineer Lattice Semiconductor AGENDA Overview Mico32 Embedded Processor Development Tool Chain HW/SW
Project Essentials Summary The basis of every design captured in Altium Designer is the project. This application note outlines the different kinds of projects, techniques for working on projects and how
Using the NicheStack TCP/IP Stack - Nios II Edition Tutorial Using the NicheStack TCP/IP Stack - Nios II Edition Tutorial 101 Innovation Drive San Jose, CA 95134 www.altera.com TU-01001-3.0 Subscribe Copyright
ModelSim Tutorial Software Version 10.0d 1991-2011 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient
1 Getting Started with Altera s DE0 Board This document describes the scope of Altera s DE0 Development and Education Board and the supporting materials provided by the Altera Corporation. It also explains
Q UA R T U S P R I M E D E S I G N S O F T WA R E Fastest Path to Your Design Quartus Prime software is number one in performance and productivity for FPGA, CPLD, and SoC designs, providing the fastest
November 2001; ver. 1.02 8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet Introduction Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre Channel, and other
Xilinx ISE tutorial (Szántó Péter, Csordás Péter 2013-09-06) Required knowledge Digital design. Basic Verilog knowledge. 1. Tutorial project For the Xilinx ISE tutorial the goal is to implement a one-digit
Introduction to Simulation of Verilog Designs For Quartus II 14.0 1 Introduction An effective way of determining the correctness of a logic circuit is to simulate its behavior. This tutorial provides an
Server Manager Diagnostics Page 653. Information. Audit Success. Audit Failure The view shows the total number of events in the last hour, 24 hours, 7 days, and the total. Each of these nodes can be expanded
AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Designs December 2009 AN-588-1.1 The reference designs demonstrate wire-speed operation of the Altera 10-Gbps Ethernet (10GbE) reference design
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