ALTERNATIVE ARITHMETIC STRUCTURES USING REDUNDANT NUMBERS AND MULTI-VALUED CIRCUIT TECHNIQUES

Transcription

1 ALTERNATIVE ARITHMETIC STRUCTURES USING REDUNDANT NUMBERS AND MULTI-VALUED CIRCUIT TECHNIQUES by Uğur Çn B.S., Electroncs and Communcatons Engneerng, Yıldız Techncal Unversty, 1999 M.S., Electrcal and Electroncs Engneerng, Boğazç Unversty, 2003 Submtted to the Insttute for Graduate Studes n Scence and Engneerng n partal fulfllment of the requrements for the degree of Doctor of Phlosophy Graduate Program n Electrcal and Electroncs Engneerng Boğazç Unversty 2010

2 ALTERNATIVE ARITHMETIC STRUCTURES USING REDUNDANT NUMBERS AND MULTI-VALUED CIRCUIT TECHNIQUES APPROVED BY: Prof. Avn Morgül (Thess Supervsor) Prof. Al Toker Prof. Günhan Dündar Prof. Ece Olcay Güneş Assst. Prof. Şenol Mutlu DATE OF APPROVAL:

3 ACKNOWLEDGEMENTS I am very thankful to Professor Avn Morgül, my thess supervsor, who encouraged me to study all the tme to complete ths thess. I hope I wll be able to go on workng on together through my entre academc career. I am especally thankful to Professor Günhan Dündar and Professor Al Toker for ther constructve comments on the mprovement of ths thess through the years of ths study. I should also menton Professor Mtchell Thornton for teachng us advanced dgtal desgn and logc synthess courses n my year of study at Southern Methodst Unversty, TX, USA. I am grateful to Professor Ece Olcay Güneş and Professor Şenol Mutlu for acceptng to be n my thess jury and for spendng ther valuable tme for readng the manuscrpt. Many thanks specally go to Mustafa Aktan for hs great frendshp and techncal support n my thess work. I should also acknowledge Emre Arslan, Cem Çakır, Yasn Çtkaya, Umut Yazkurt, Engn Denz and BETA members for ther frendshp throughout my study. I am very thankful to my mother, brother and especally my wfe Büşra for ther support and love. I would also thank all of my frends for ther frendshp and support throughout the years of ths study. I also thank Boğazç Unversty Research Fund for supportng our work under the Project No: 05HA201.

4 v ABSTRACT ALTERNATIVE ARITHMETIC STRUCTURES USING REDUNDANT NUMBERS AND MULTI-VALUED CIRCUIT TECHNIQUES Arthmetc crcuts play a crucal role n VLSI technology. Arthmetc blocks are usually the most power consumng parts n a system snce the swtchng actvty s qute hgh. Alternatve arthmetc mplementatons can be a soluton to reduce power consumpton and to ncrease the performance of the whole system. Statc CMOS dgtal desgn has robust workng performance, where logc levels are kept at the two extremes, ether the ground voltage or supply voltage. However, the voltage excurson between the supply voltage and ground at all nodes causes excessve power dsspaton. Ths condton also generates nose over the whole crcutry, whch s not desrable especally n mxed sgnal desgns. Current-mode dgtal desgn technques can be a soluton for ths ssue especally whenever the swtchng actvty s hgh. In the frst part of the thess, alternatve current-mode arthmetc structures are bult focusng on mult-valued crcuts. Together wth mult-valued logc mplementatons, sgned-dgt numbers and redundant number systems are also analyzed. The desgn ssues of multvalued crcuts are dscussed and novel buldng blocks for mult-operand addton are developed. In the second part of the thess, redundant arthmetc schemes for new generaton reconfgurable systems are also analyzed. These technques proposed here can be mplemented effcently by usng recently ntroduced 6-nput look-up table based feld programmable gate array (FPGA) systems. A redundant double carry-save mode addton technque s proposed for the new generaton FPGA devces. Usng the proposed technque, effcent multply-accumulate operatons and fnte mpulse response flter structures for reconfgurable systems are developed.

5 v ÖZET YEDEKLİ SAYILAR VE ÇOK DEĞERLİ DEVRE TEKNİKLERİ İLE GELİŞTİRİLEN ALTERNATİF ARİTMETİK YAPILAR Artmetk devreler tümleşk devre tasarımında öneml br yere sahptr. Genellkle artmetk bloklar br sstemde en yüksek güç harcayan brmlerdr. Bunun neden, bu devrelern anahtarlama aktvtelernn oldukça yüksek olmasıdır. Alternatf artmetk uygulamalarla tüm sstemn güç gereksnm azaltılablr ve sstem performansı arttırılablr. Statk CMOS sayısal tasarım dayanıklı çalışma performansına sahptr. Bunun neden lojk sevyelern k uç değer olan besleme gerlm ve toprak arasında korunmasıdır. Buna karşılık tüm düğümlern besleme voltajı değer mktarı salınması yüksek güç tüketmne ve devrelerde gürültüye neden olmaktadır. Bu durum özellkle karma snyal devrelernde stemeyen br durumdur. Özellkle anahtarlama yoğunluğunun fazla olduğu durumlarda akım modlu sayısal tasarım bu duruma br çözüm olablr. Tezn lk kısmında alternatf akım modlu artmetk yapılar çok değerl mantık devreler kullanılarak gelştrlmştr. Çok değerl mantık devreler le beraber şaretl sayılar ve yedekl sayı sstemler de ele alınmıştır. Çok değerl mantık devrelernn tasarım gereksnmler ele alınmış ve özgün çok terml toplama devreler önerlmştr. Tezn knc kısmında yenden yapılandırılablr sstemler çn yedekl sayı sstemlernn kullanımı ncelenmştr. Burada önerlen teknkler yen nesl 6-grşl hafızalı sahada programlanablen kapı dzs (FPGA) sstemler üzernde etkn olarak gerçekleneblmektedr. FPGA sstemler çn yedekl çft saklamalı toplama teknğ önerlmştr. Önerlen teknk kullanılarak yenden yapılandırılablr sstemler üzernde etkl çarp-topla şlemler ve sonlu dürtülü fltre yapıları gerçekleneblmektedr.

6 v TABLE OF CONTENTS ACKNOWLEDGEMENTS... ABSTRACT... v ÖZET... v LIST OF FIGURES... v LIST OF TABLES... x LIST OF SYMBOLS/ABBREVIATIONS... xv 1. INTRODUCTION MATHEMATICAL BACKGROUND OF REDUNDANT NUMBER SYSTEMS AND MULTI-VALUED LOGIC Redundant Number Systems Generalzed Redundant Number Systems Ordnary Sgned-Dgt Number Representaton Bnary Sgned-Dgt Archtecture Carry-Save Arthmetc MVL Functon Representaton and Logcal Operators Basc Defntons of Mult-Valued Logc n Chan Based Post... Algebra Functonal Completeness of Mult-Valued Logc of Post Algebra BINARY AND MULTI-VALUED CURRENT-MODE LOGIC DESIGN Current Comparator Crcuts Bnary Current-Mode Logc (Source-Coupled Logc) Crcuts Arthmetc Buldng Blocks of Mult-valued Logc Crcuts Basc Radx-4 Current Mode Adder Archtecture Implementng MVL Functons Usng Current-Mode Logc Hgh Radx Current Mode Full Adder Archtecture Comments on the Mult-valued Arthmetc Archtectures MULTI-VALUED SIGNED DIGIT CIRCUITS AND COUNTER CIRCUITS Sgned-Dgt Mult-Valued Implementaton Mult-operand Addton and Counter Crcuts Counter Crcut wth Mult-valued Output... 62

7 v Bnary Restored Mult-valued (7, 3) Counter REDUNDANT ARCHITECTURES AND FIELD PROGRAMMABLE GATE ARRAYS (6, 3) Counter and Smultaneous Addton of Sx Bnary Numbers Multplyng Accumulator Unt Desgn Fxed Coeffcent FIR Flter Desgn Realzaton of Multply-add Operaton Flter Implementaton CONCLUSION APPENDIX A: PROBLEM FORMULATION OF THE FIXED-COEFFICIENT FIR FILTER SYNTHESIS REFERENCES REFERENCES NOT CITED

8 v LIST OF FIGURES Fgure 1.1. (a) Voltage mode addton; (b) current mode addton... 3 Fgure 2.1. Parallel addton of two sgned-dgt numbers [13]... 8 Fgure 2.2. (a) Full adder representaton; (b) rpple carry addton usng full adders Fgure 2.3. Carry-save adder structure: (a) normal bnary nputs, (b) redundant nputs Fgure 2.4. An example mult-valued functon Fgure 3.1. (a) Current comparator crcut wth voltage mode output; (b) representaton of equvalent output capactance Fgure 3.2. (a) Threshold comparator [7]; (b) equvalent crcut Fgure 3.3. Bnary Current Mode Logc crcut Fgure 3.4. MCML nverter/buffer Fgure 3.5. Realzaton of Boolean functons wth MOS Source-Coupled Logc (SCL) Fgure 3.6. Current mode radx-4 adder crcut and ts logcal dagram [49] Fgure 3.7. Multple-valued Source Coupled comparator Fgure 3.8. Analyss of Source Coupled Comparator crcut Fgure 3.9. Sgned dgt full adder archtecture Fgure Carry and sum generaton for the crcut proposed n [8] Fgure Truncated dfference: DC characterstcs, crcut and symbol [48] Fgure (a) Upper-threshold DC characterstcs and two-output block dagram, (b) crcut dagram, mnmum feature sze transstor aspect ratos... 37

9 x Fgure (a) y-cwc operaton DC characterstcs, (b) block dagram, (c) crcut dagram Fgure A hgh radx current mode full adder crcut [32] Fgure 4.1. Sgned dgt mult-operand adder example Fgure 4.2. Block dagram of the sgned-dgt mult-operand adder Fgure 4.3. Input block of the sgned dgt mult-operand adder Fgure 4.4. The nput currents I sum and I sum and generated voltages over the source to dran of the nput transstors M n1 and M n Fgure 4.5. Voltage-mode carry generaton crcut Fgure 4.6. Generaton of output currents Fgure 4.7. (a) Crcut for output current generaton; (b) current-mode carry-out generaton crcut Fgure 4.8. Output current and carry-out Fgure 4.9. MVL to voltage mode bnary comparator: (a) Dfferental ended; (b) Sngle ended Fgure Comparator outputs Fgure Sgned dgt bnary outputs Fgure Sx operand rpple carry adder archtecture current consumpton Fgure Sngle bt slce of the mult-operand adder layout Fgure (a) Three operand carry-save adder; (b) four operand carry save adder wth completon adder Fgure Multpler usng (3, 2) counters Fgure Buldng a (7, 3) counter usng full adders... 60

10 x Fgure Partal product reducton usng (7,3) and (3,2) counters Fgure Mult-valued counter block dagram Fgure Input block of the mult-valued 7-bt addton crcut Fgure The nput currents I sum and I sum and generated voltages over the drans of the nput transstors M n1 and M n Fgure Carry generaton crcut Fgure (a) Output current generaton; (b) current-mode carry generaton Fgure Output current (I sum ) and carry-out (I Cout ) smulaton results Fgure Implementaton of the proposed mult-valued counter Fgure Input stage of the mult-operand counter Fgure Current and voltage waveforms of the nput crcut Fgure Dran to bulk connected PMOS transstor used as a nonlnear resstor (a) electrcal connecton; (b) current-voltage characterstcs [60] Fgure Comparator and output generator for s Fgure Comparator stages for sensng the logc levels Fgure (a) Output generaton for the s 0 and ' s 0 ; (b) output buffer Fgure Connectons of the proposed system Fgure Logcal outputs of the crcut Fgure (a) Energy versus Frequency; (b) Energy x Delay versus Frequency Fgure (a) Delay vs. current consumpton; (b) PDP vs. current consumpton Fgure x 8 bt multplcaton scheme Fgure Source-coupled full adder crcut: (a) sum generaton; (b) carry-out... 78

11 x Fgure (a) Input stage of the MV two-bt adder; (b) two bt adder representaton Fgure 5.1. Basc FPGA archtecture Fgure 5.2. Logc module of Altera Flex Fgure 5.3. Adaptve sx nput LUT devce of Stratx II FPGA [61] Fgure 5.4. Addton of 6 operands n the LUT structure Fgure 5.5. Addton of two sgned dgt numbers Fgure 5.6. (6,3) counter: (a) sngle bt structure (b) addton of multple operands usng counters Fgure 5.7. Verlog descrpton of (6, 3) counter Fgure 5.8. (a) Addton of two redundant varables; (b) subtracton Fgure 5.9. (a) Partal product generatng usng modfed Booth encodng; (b) backward sgn extenson Fgure Multply-Accumulate operaton by mplementng (6, 3) reducton Fgure Multply-accumulate unt applcaton: (a) Sngle MAC; (b) multple MAC Fgure FIR flter mplementaton: (a) Transposed form; (b) sharng the coeffcents Fgure Frequency response characterstcs of a low-pass FIR flter Fgure (a) Generaton of the partal products; (b) backward-sgn extenson Fgure Pseudo code representaton of partal product representaton Fgure Multply- add operaton: (a) Generalzed case; (b) up to 3 nonzero bts n the coeffcent Fgure Frequency response characterstcs of the example flters

12 x Fgure Representaton of multply-add operaton and converson to normal bnary Fgure Performance comparson of the flter mplementatons

13 x LIST OF TABLES Table 2.1. Modfed rules for addng bnary SD numbers Table 2.2. Number of combnatonal logc functons by MVL Table 2.3. Multple-valued counterparts of basc MVL operatons Table 2.4. Truth table of Mn, Max and Modular Sum (Msum) operators Table 2.5. MVL unary operatons Table 4.1. Logc levels of I sum and I sum at the nput stage Table 4.2. Logc levels of I out1 and I out1 at the output stage Table 4.3. Comparator output values and s Table 4.4. Delay of the adders for varous bt lengths Table 4.5. Logc levels of I sum and I sum currents at the nput stage Table 4.6. Logc levels of I out and I out currents at the output Table 4.7. Logc levels of I sum and I sum currents at the nput stage Table 4.8. Summaton and correspondng comparator outputs Table 4.9. Comparson of the adders and multplers Table 5.1. Modfed Booth Encodng Table 5.2. Performance comparson (6-nput LUT) Table 5.3. Performance comparson (4-nput LUT) Table 5.4. ( ω) T for dfferent types of lnear-phase FIR flters m Table 5.5. Frequency response characterstcs of a low-pass FIR flter... 99

14 xv Table 5.6. Frequency response characterstcs of the example flters Table 5.7. Coeffcents of Flter Table 5.8. Coeffcents of Flter Table 5.9. Comparson of flter mplementaton schemes

15 xv LIST OF SYMBOLS/ABBREVIATIONS BDD BSD BSC BSCB CCWC CML CMOS CWC DCVSL DSL FA FIR FPGA LUT MAC MCML MOS MV MVL NMOS OSD PDN PMOS SB SC SCB SCL SD VLSI Bnary Decson Dagram Bnary Sgned-Dgt Bnary Stored-Carry Bnary Stored Carry-or-Borrow Counter Clockwse Cyclc Current Mode Logc Complementary Metal Oxde Semconductor Clockwse Cyclc Dfferental Cascode Voltage Swtch Logc Dfferental Splt-level Logc Full Adder Fnte Impulse Response Feld Programmable Gate Array Look-up Table Multply-Accumulate MOS Current Mode Logc Metal Oxde Semconductor Mult-Valued Mult-Valued Logc N-type Metal Oxde Semconductor Ordnary Sgned Dgt Pull Down Network P-type Metal Oxde Semconductor Radx-r Stored-Borrow Radx-r Stored-Carry Radx-r Stored Carry-or-Borrow Source-Coupled Logc Sgned-Dgt Very Large Scale Integraton

16 1 INTRODUCTION Arthmetc desgn blocks play a crucal role n the dgtal and mxed-sgnal systems. The bottleneck of dgtal sgnal processng and many other dgtal systems s arthmetc blocks where addton and multplcaton operatons are the core unts. As the VLSI technology reduces to nanometer sze devces, power dsspaton reduces and devce speeds ncrease every year. However, slcon technology s reachng ts physcal lmts, where the desgn szes already have reached the atomc levels. In ths thess, alternatve crcut desgn technques are proposed for arthmetc systems that can help desgnng analog frendly crcuts; or ncrease performance wth lower power consumpton. Addton of numbers s the most basc operaton of all arthmetc systems, such as subtracton, multplcaton and dvson. In the basc addton structure, the addton tme s proportonal to the bt sze of the numbers to be added snce the next output dgt depends on prevous carry-out of each dgt. Ths causes an unacceptable delay for many systems especally when the word-length of the nput operands s hgh. Therefore, carry sgnal propagaton must be elmnated n the arthmetc crcuts. There have been varous technques developed for breakng the long carry chans of the arthmetc crcuts [1-3]. Bascally, these technques are based on redundant number representatons. Redundant representaton means that a number s represented n more than one way n the number system. As an example, f the number base s radx-4 (each weght of the dgt s a multple of 4 n where n represents the nth dgt) and dgt set s selected to be { 3, 2, 1, 0, 1, 2, 3}, the numbers 0013, 0021, and 0121 all have arthmetc value 7. In ths representaton, x represents x for each dgt. The redundancy n the number system can provde the carry chans n the addton algorthms to be broken. Ths makes the arthmetc operatons ndependent on the bt sze of the operands [1]. The detals of redundant systems and carry-free addton crcuts are explaned n detals n the next chapter. Redundant systems are not necessarly bnary, but the numbers computed can be encoded as bnary. As a result, more than one dgt s requred for the representaton of

17 2 redundant systems when the system s mplemented n bnary logc. Hence, the redundancy n numbers means that the number structure s non-bnary. Mult-valued crcut technques are sutable to mplement the arthmetc operatons wth such redundant numbers. Consderng redundant number systems n the number theoretc approach, carry propagaton free algorthm development s acheved by usng sgned dgt numbers or usng carry save arthmetc. A sgned dgt system can be represented as A B, where A represents postve dgts and B represent negatve dgts. On the other hand, carry save format numbers can be represented as the addton of two numbers; Z = {S, C},. e., sum dgts (S) and carry dgts (C), respectvely [4]. Shortly, carry-save mode addton technques may also be consdered as redundant number addton technques where negatve numbers do not exst n the dgt set. The detals of redundant systems are analyzed n Chapter 2. Snce the redundant systems are not bnary n prncple, they can be mplemented as mult-valued crcuts. By mult-valued crcut technques, carry-save mode redundant archtectures or sgned dgt systems can be mplemented. Mult-valued logc (MVL) has always been an alternatve logc desgn style, however, the crcut mplementaton drawbacks have been the obstacles over the years. In general, current-mode and voltage-mode mplementaton of MVL s possble. Voltage mode mplementatons of MVL are dffcult n today s technology, snce the low voltage desgn requrements do not leave enough voltage room for each logc level. Current-mode mplementatons of mult-valued crcuts have the advantage of dynamc range, whch gves flexblty n crcut desgn to have multple logc levels on the same node. Another pont s that, addton of two or more nput operands s very easy n current mode MVL [5, 9]. The addton s mplemented by smply nterconnectng two current carryng wres (Fgure 1.1), accordng to the Krchoff s Current Law. Snce addton of two branches needs no logc crcut and hence happens wthout delay n theory, t s clearly a great advantage aganst voltage mode crcuts. In ths work, the focus s mostly on the mplementaton of arthmetc crcuts by usng MVL crcuts. They have certan advantages over standard bnary CMOS crcuts. Standard CMOS dgtal desgn has robust workng performance, where each node s kept n two extremes, ether ground or supply voltage. However, the voltage excurson between

18 3 I A I OUT = I A + I B I B (a) Fgure 1.1. (a) Voltage mode addton; (b) current mode addton (b) the supply voltage and ground at all nodes causes excessve power dsspaton. Moreover, t generates nose over the whole crcutry. Ths s not desrable especally n mxed-system desgns. Current-mode desgn technques can be a soluton for ths ssue especally when the swtchng actvty s hgh. In statc CMOS desgn, the power consumpton s neglgble when the crcut s not swtchng. Nevertheless, n current-mode desgns the supply current s not zero and power s consumed all the tme. As the supply voltages scale down and devce geometry reduces to nanometer szes, leakage current n voltage mode crcuts becomes sgnfcant, gvng a chance to the current-mode desgn technques [10,11]. The sgnfcance of leakage currents for statc CMOS appears at low voltage desgns especally for the geometres lower than 0.18 μm. Another property of the current-mode desgn s that the swtchng nose of the dgtal crcutry can be elmnated by usng proper crcut technques. Ths property s especally mportant for mxed-sgnal systems, where dgtal crcut nose s an mportant artfact. The current-mode crcuts are drven by approxmately constant current. Ths reduces d/dt nose, whch s generated by the nductve effect on the bondng wres of the chp. The am of ths thess work s twofold. The frst s to mplement alternatve arthmetc blocks n mult-valued style wth a smple and effcent desgn methodology. The second part of our research work s to mplement effcent arthmetc algorthms usng redundant number technques wth alternatve number representatons and mplementatons on reconfgurable systems for dgtal sgnal processng applcatons.

19 4 For the mult-valued crcut desgn, the effcency metrc s mnmzng the area and nterconnect and obtanng lower power at hgh speed. Our research work on the multvalued crcut desgn s concentrated n enhancng the current comparators and the current swtchng crcuts. Current comparson and current swtchng s the man desgn problem of all systems. Gltch free and fast current swtchng makes the system an alternatve to standard CMOS logc. In an alternatve mult-valued crcut desgn technque, t s also mportant to select a good arthmetc algorthm sutable for the hardware. Here, the am s to fnd systems where mult-valued crcuts have advantages over standard bnary logc crcuts. Therefore, desgnng wth redundant numbers or sgned dgt multple valued arthmetc s focused. Mult-valued to bnary converson may be requred at the end, dependng on the applcaton of the system. The startng pont of ths work has been desgnng hgh performance arthmetc crcuts usng alternatve mult-valued and current-mode crcut desgn technques. However, very hgh performance crcuts can be bult by bnary logc by properly arrangng the devce szes or by usng dynamc crcut technques lke domno logc [12]. Ggahertz range addton crcuts are realzable n bnary crcuts and these performance benchmarks are dffcult to be beaten by current-mode mult-valued crcuts. The reason for the lmtatons of current-mode logc crcuts s that, the performance s lmted by the current source and ncreasng the current to very hgh levels causes excessve current dsspaton. On the other hand, current mode technques allow controllng power consumpton. Therefore, the power may be adjusted effcently accordng to system requrements. In the frst part of ths thess work, novel current-mode mult-valued crcut topologes are developed that are especally effcent for mult-operand addton. The crcuts developed here are orgnal and unque to the best of our knowledge. The secondary research effort n ths work s to mplement effcent arthmetc systems, especally mult-operand adders and redundant number systems on reconfgurable archtectures,.e., Feld Programmable Gate Array (FPGA) devces. FPGAs, especally new generaton hgh performance 6-nput look-up table based structures can be used as multple valued nput bnary output devces, where effcent arthmetc structures can be

20 5 bult usng redundant mult-operand addton technques. Fnte Impulse Response (FIR) flter structures are mplemented on FPGAs as sgnal processng applcatons to show the advantages of multple valued addton schemes to acheve hgh operaton speeds. To summarze, Chapter 2 gves some background n the basc theory of redundant numbers and gves a short ntroducton to mult-valued logc. Chapter 3 provdes basc current-mode crcuts both n bnary and mult-valued sense. Chapter 4 dscusses the proposed mult-valued crcuts and explores the desgn both n crcut technques sense and redundant number system approach. Chapter 5 contans FPGA mplementatons, whch are realzed by usng redundant numbers. Chapter 6 s the concluson, whch summarzes the outcome of the work done.

21 6 MATHEMATICAL BACKGROUND OF REDUNDANT NUMBER SYSTEMS AND MULTI-VALUED LOGIC In ths chapter, the mathematcal bass of redundant numbers s gven. A short and general ntroducton of mult-valued logc s also gven for the analyss of varous multvalued logc mplementatons n lterature Redundant Number Systems In redundant number systems, a number can be represented n alternatve ways. The redundancy gves extra nformaton for representng a number. Moreover, redundancy s requred for breakng the carry propagaton chans of the addton process and s very useful when buldng arthmetc crcuts, such as adders, adder trees, multplers, etc. Sgned-dgt numbers and carry-save arthmetc are well-known examples of the redundant number systems. Sgned-dgt arthmetc was frst ntroduced by Avzens [13]. Sgned-dgt systems were conceved wth the purpose of mplementng totally parallel addton [13]. Avzens proposed an arthmetc system where carry propagaton s elmnated. Carry propagaton s elmnated by makng each dgt of the resultng sum a functon of only two nput dgts. Ths s made possble by ntroducng redundancy n the number representaton. A proper ntermedate representaton of the operand dgt summaton, x + y s selected so that the fnal addton result can be generated usng wthout requrng or generatng carry sgnals [14]. In conventonal number systems, numbers can be represented as x {0, 1,... r 1}, where r s the radx, x s the th dgt of the number. In a sgned dgt number system, x can take over the values such that x { ( r 1), ( r 2),... 1, 0, 1,... (r 1)}. In ths scheme, ( r 1) equals to (r 1), 1 equals to 1, etc. Each dgt can have postve and negatve values. Therefore the system s named sgned-dgt (SD) representaton [2].

22 7 Sgned-dgt representaton gves redundancy n sgnal representaton. As an example, 1 can be represented as 01 or 2 1. In radx 10 (r = 10), a two-dgt number X can have values n the range of 99 X 99. Snce X s a two-dgt number, each dgt can have 19 ( 9 to 9) dfferent representaton, where X can have 19 2 = 361 representatons. The number X can nclude 199 values ( 99 to +99). Therefore, n ths number system X has = 162 redundant numbers, whch means that X has 81 per cent (162/199) redundancy. The algebrac value of a sgned-dgt number s gven by Z = m = 0 z r. In ths representaton, r s a postve nteger called the radx, and each dgt s denoted as z. In a redundant representaton wth radx r, each dgt can assume more than r values. In conventonal number representatons dgts can assume exactly r values,.e. z {0, 1, (r 1)}. The values of the radx and the number dgts, z, should satsfy the condton of a unque representaton for the algebrac value Z = 0. It s then easy to prove that the algebrac value Z s zero f, and only f, all dgts of ts sgned-dgt representaton have the value z = 0. It s also evdent that the sgn of the algebrac value Z s determned by the sgn of the most sgnfcant non-zero dgt. Smlarly, the sgned-dgt representaton of Z, the addtve nverse of Z, s obtaned by changng the sgn of every non-zero z dgt of Z. Fgure 2.1 depcts the totally parallel addton approach n a sgned-dgt arthmetc system. In the fgure, u s named as nterm sum. The addton of two dgts x and y s totally parallel f two condtons are satsfed. Frst, the nterm sum dgt u s only the functon of the operand dgts, x and y [14]. Second, the carry dgt to the next poston c s functon only of the operand dgts, x and y. Totally parallel subtracton x y s realzed as the totally parallel addton of x and the addtve nverse of y, that s, x y = x + ( y ). The detals of the operatons are gven n the followng sectons.

23 8 Fgure 2.1. Parallel addton of two sgned-dgt numbers [13] Generalzed Redundant Number Systems Generalzed sgned-dgt number s a postonal system wth the dgt set {-α, -α + 1,..., 0,, β 1, β} where, α 0, β 0, and for redundant number systems [1]: α + β + 1 > r (2.1) Here, r s the number representaton radx. For the case where α + β + 1 = r results n non-redundant number representaton systems. The conventonal radx-r system wth α = 0 and β = r 1 s the case for the generc r s complement numbers and the 2 s complement system s the most popular one. Redundancy ndex of a generalzed sgneddgt number system s defned as: ρ = α + β + 1 r (2.2) A number can be represented as Z = m = 0 z r (2.3)

24 9 In ths representaton, r s the radx of the number system and z s nsde the dgt set z {-α, -α + 1,..., 0,, β 1, β} where, α 0, β 0. Parham classfes some specal cases nsde the generalzed sgned-dgt system [1]: 1. Bnary stored-carry (BSC): r = 2, α = 0, β = Radx-r stored carry (SC): α = 0, β = r. 3. Bnary stored-borrow or bnary sgned dgt (BSB or BSD): r = 2, α = β = Radx-r stored-borrow (SB): α = 1, β = r Bnary stored carry-or-borrow (BSCB): r=2, α = 1, β = Radx-r stored-carry-or-borrow (SCB): α = 1, β = r. 7. Mnmally redundant symmetrc sgned-dgt: r 4, 2α = 2β = r. 8. Ordnary sgned-dgt (OSD): r 3, 1/2r < α = β < r. 1 a. Mnmally redundant: α = β = r b. Maxmally redundant: α = β = r 1. Sgned-dgt systems for r > 2 are were frst proposed by Avzens [13]. Moreover, Parham [1] proposed generalzed sgned-dgt number representaton that explans redundant number systems ncludng bnary case and other alternatves. Avzens s sgned dgt system s named as ordnary sgned-dgt number system (OSD) n Parham s work. Carry-save arthmetc s also one of the redundant number systems and has smlar propertes wth sgned-dgt systems and t s defned n the followng sectons Ordnary Sgned-Dgt Number Representaton Addng some redundancy to a number system can be benefcal n some of the arthmetc operatons; on the other hand, t s costly when t s used more than needed. Amount of redundancy n a sgned dgt representaton can be restrcted as follows: r 1 z { a, a 1,... 1, 0, 1,... a-1, a} wth 1 2 a r (2.4)

25 10 where z s the th dgt of a number. A number can be represented as n (2.3) usng the dgt set of (2.4). Accordng to the defnton of the generalzed redundant number systems n Secton 2.1.1, α = β = a n the ordnary sgned dgt representaton. At least r dfferent dgts n the dgt set are necessary to represent a number n a radx r system. In addton, each dgt z should satsfy a z a for each dgt n ths representaton. There are 2a + 1 alternatves for each dgt n ths representaton. Therefore, the nequalty 2a + 1 r must be satsfed and the lower bound n the nequalty s for that ssue [13, 14]. As an example, n radx-8 representaton, the value of a s between 4 a 7 accordng to (2.4). As stated above, the man advantage of the sgned-dgt (SD) representaton s to elmnate the carry propagaton chans n addton and subtracton. Ths s done by breakng the addton nto two steps [13]. Step 1: Compute an nterm sum u and carry dgt c : u = x + y rc (2.5) where c 1 = 1 0 f ( x + y ) a f ( x + y ) a f x + y < a (2.6) Step 2: Calculate the fnal sum: s = u + c -1 (2.7) Consder the example where r = 10 and a = 6. Step 1 wll result n u = x + y 10c where c s calculated from:

26 11 c 1f (x + y ) 6 = 1f (x + y ) 6 0 otherwse If two numbers, 4536 and 1466 are added n a classcal way, Carry propagates from the frst dgt through the last one. If they are added n SD representaton: c u s scheme. As can be seen from ths example no carry propagaton appeared n the SD addton To fnd an SD representaton of a number, the aforementoned algorthm can be used. For example, to fnd the SD representaton of 27956, each dgt s represented as x + y. In other words, here, each dgt can be vewed as an nterm sum of a prevous addton: x + y c u s

27 12 When mplementng SD addton scheme, to guarantee that no new carry s generated, the range of a must be selected properly. In the case where x + y = a, whch s the smallest value for whch c s stll 1, u = a r < 0. Substtutng u ( a 1) yelds the nequalty 2 a r + 1. Hence, the selected dgt must satsfy: u = r a nto r a r Bnary Sgned-Dgt Archtecture In bnary sgned-dgt (SD) addton schemes, t s not guaranteed that no new carry wll be generated when computng s. Interm sum u and carry generatons should be revsed, accordng to the Table 2.1 to assure that no new carry wll occur n the generaton of s [15]. As can be seen n Table 2.1, nterm sum and carry generatons are made accordng to the th dgt x y and the prevous dgt x -1 y -1. Table 2.1. Modfed rules for addng bnary SD numbers x y x -1 y -1 Not used Nether s 1 At least one s 1 Nether s 1 At least one s 1 Not used Not used c u For radx-2, the arthmetc here s named as bnary sgned-dgt (BSD) or bnary stored-borrow and the rules dverges from the ordnary SD systems. The modfed rules for addng bnary SD numbers as shown n Table 2.1 s not unque. Varous bnary sgneddgt addton schemes can be generated [16, 17]. SD bnary arthmetc mplementatons can be seen n [3, 18-23]. The bnary sgned dgt addton scheme can be analyzed usng the followng example:

28 nterm sum (u ) nterm carry (c ) fnal sum (s ) where two SD numbers are added up based on the bnary SD addton prncples. The nterm sum and carry dgts are generated based on Table 2.1. The fnal sum s calculated by addng up the nterm results. Note that, no new carry occurs n the fnal sum generaton. Another ssue related to redundant systems s the format converson. For SD systems, redundant bnary to normal bnary converson s trval. Snce each number s represented as postve dgts and negatve dgts, subtracton of negatve dgts from postve dgts results the converson to normal bnary. There are other algorthmc approaches for these mplementatons for speed mprovement of format converson. In order to mprove the speed of the converson operaton, other algorthmc approaches have been proposed [21, 22]. Converson from unsgned normal bnary to SD bnary s also trval, such that, all non-zero bts of the normal bnary number are equal to the postve dgts of the sgned dgt numbers, and all the negatve dgts are equal to zero. For 2 s complement bnary, sgn bt s equal to the correspondng negatve dgt of the sgned-dgt number and all other postve dgts are equal to the non-zero bts of the normal bnary number, same as the normal bnary case Carry-Save Arthmetc Carry-save adder concept has been used for more than four decades. Wallace named the classcal full-adder archtecture for the usage of carry-save arthmetc as pseudo adder, snce t reduces three nput operands to two [24]. Wallace also desgned parallel reducton tree for the reducton of the partal products of the multpler. Carry-save reducton has been used n countless arthmetc applcatons where t s mostly used for partal product

29 14 reducton of multplers. Carry-save arthmetc can also be generalzed as a redundant bnary system [1, 4]. Before defnng the carry-save arthmetc, the most basc addton scheme,.e. full adder, should be mentoned here. A full adder has three nput operands x, y, z and two outputs s and c. The operaton s descrbed as x + y + c n = 2c out +s where, + operaton s arthmetc addton here and each x, y, z, c and s {0, 1} here. The sngle bt cell of a full adder and a mult-bt rpple carry adder are depcted n Fgure 2.2 (a) and 2.2 (b), respectvely. Fgure 2.2. (a) Full adder representaton; (b) rpple carry addton usng full adders Counter crcuts are used for mult-operand addton of bnary numbers. The smplest counter crcut s the (3, 2) counter whch s smply a full adder. The only dfference s the applcaton, such that, all x, y, and c n nputs have same functonalty, and, there s no carry rpple acton contrary to the stuaton shown n Fgure 2.2 (b). A (3, 2) counter counts the number of non-zero nputs and encodes the result nto a two dgt bnary number. The maxmum number of non-zero nput dgts s 3, hence we need at least 2 output dgts to represent the result as shown n Fg 2.3 (a). The delay of the crcut s the sngle cell (3, 2) counter delay (sngle FA delay) as total, ndependent of the bt wdth of the operands.

30 15 (a) (b) Fgure 2.3. Carry-save adder structure: (a) normal bnary nputs, (b) redundant nputs In a carry-save system, each dgt s represented as summaton of two numbers, sum and carry. However, the fnal bnary result,.e. addton of ths sum and carry, s not computed unless t s requred. The output of the (3, 2) counter, composed of two numbers S and C, s an example to a carry-save number. In carry-save representaton, each dgt s represented as: z = {s, c } (2.8) where the summaton Z s represented as Z = {S, C}. Carry-save arthmetc s a redundant system where the dgt set s descrbed as z {0, 1, 2} and each dgt of Z s equvalent to z = s +c. Carry-save arthmetc also provdes carry propagaton free addton smlar to SD systems. Two arbtrary numbers n carry-save format can be added up usng a (4, 2) reducton scheme, seen n Fgure 2.3 (b). The (4, 2) reducton s realzed by a two stage (3, 2) counter reducton scheme. Moreover,

31 16 more compact (4, 2) reducton schemes for VLSI desgn exst for faster performance [25]. Carry-save arthmetc s an advantageous alternatve to SD systems n many of the carryfree arthmetc applcatons. It should be noted here that, t s also possble to mplement hgher radx carry-save arthmetc provdng less redundancy n the system [3]. Normal bnary to carry-save converson and the reverse should be noted here as well: 1. A normal bnary number X can be represented as n (2.8.b) n a way that S = X and C = Addton of two normal bnary numbers X and Y can be represented as a sngle carry-save number such that: S = X and C = Y wthout applyng any addton hardware. 3. Three normal bnary numbers can be converted to carry-save format (addton of three normal bnary numbers wth the output n carry save format) as shown n Fgure 2.3 (a). 4. And fnally, a carry-save format number can be converted to normal bnary by usng a two operand adder, such as a rpple carry adder, where s and c components are added up resultng a normal bnary number such that Result = S + C MVL Functon Representaton and Logcal Operators The proposed crcuts n ths thess are not based on the formal defntons of MVL algebra. However, there are varous works referenced n the thess usng MVL logcal operators and formal defntons. Ths secton s gven as an ntroducton to general MVL functon defntons. Mult-Valued Logc (MVL) s a generalzaton of bnary logc. Bnary logc s a subset of MVL [26]. Mult-valued logc s a logc system whch has more values than 0 and 1 contrary to bnary logc. Boolean logc can be bnary Boolean logc or mult-valued Boolean logc where n mult-valued Boolean algebra the varable sze must be a power of 2. There are other multvalued logc systems rather than Boolean logc. Especally chan based Post algebra s an

32 17 mportant research area of mult-valued logc whch has functonal completeness. Furthermore, contrary to mult-valued Boolean logc, n chan based Post algebra the varable space need not to be a power of 2. Post algebra was frst ntroduced by Emle Post n 1921 [27] and has been very famous among the mult-valued logc communty. A partcular set of Post algebra s the chan based Post Algebra whch s functonally complete and attaned much attenton and welcomed much among the mult-valued logc research communty. For the chan based Post algebra, when the varable space s restrcted to bnary, t s equvalent to bnary Boolean Logc. The chan based Post algebra or chaned Post algebra s defned as M, +,, L,0, 1 [26-29], where M s a totally ordered fnte set contanng m elements {0, 1,, m 1}, + s the max operator,. s the mn operator and L s the lteral. Mn, max and lteral operators are defned n next secton. In chan based Post algebra, logcal zero 0 = 0 and logcal one 1 = m 1 for an m- valued logc system [26-28]. For the Boolean case, the logc defnton s only functonally complete n the set m = 2 n, n {1,2,3...}. For chan based Post algebra, there s no restrcton for functonal completeness, and, m may have any arbtrary postve nteger value,.e. t s functonally complete where m = {1, 2, 3, }. Ths means that chan based Post algebra gves more general vew than Boolean logc. As stated above, whenever m = 2 (bnary case), Boolean algebra and chan based Post algebra are equvalent. Mult-valued logc s studed for varous ntentons. For some researchers, multvalued logc s a mathematcal concept and can be vewed as a pure mathematcal research area, whch has a broad vew n logc. Secondly, mult-valued logc can be used for logc synthess of conventonal bnary logc crcuts. Another research area s mult-valued crcut generaton whch also deals wth electroncs and crcut theory Basc Defntons of Mult-Valued Logc n Chan Based Post Algebra Consderng a multple valued combnatonal functon f(x) n chan based Post algebra, whch s m valued, where X = {x 1, x 2,..., x n }, each x can take m values from the set M = {0, 1,... m-1}. Here, the mappng of the functon s defned as f: M n M. There

33 18 are n m m dfferent functons that can be mplemented. Table 2.2 shows the number of functons that can be mplemented, dependng on the radx and varable count. Basc operatons n MVL and ther smlar counterparts n bnary logc are shown n Table 2.3. Table 2.2. Number of combnatonal logc functons by MVL n varable radx (r) x x x x x Defnton: A mn operator can be defned as: mn(a 1, a 2,... a n ) = a 1 a 2 a 3... a n (2.9) where a 1, a 2,... a n R = {0, 1,... r-1}. For a 1 = 5, a 2 = 2, a 3 = 3, mn(5,2,3) = 2. The operator wll be replaced by. n the followng representatons for smplcty [30-32]. Defnton: A max operator s defned as: max(a 1, a 2,... a n ) = a 1 a 2... a n (2.10) where a 1, a 2,... a n R = {0, 1,... r-1}. For a 1 = 5, a 2 = 2, a 3 = 3, max(5,2,3) = 5. The operator wll be replaced by + n the followng representatons for smplcty. Table 2.3. Multple-valued counterparts of basc MVL operatons Bnary MVL NOT Complement, Cycle AND MIN OR MAX XOR SUM (mod r)

34 19 Defnton: Complement of x, s defned as: x = ( r 1) x (2.11) For 4 valued-logc, f x = 2, x = ( 4 1) 2 = 1. Defnton: Cycle operator can has two defntons, y-clockwse cyclc operator (CWC) and y-counter clockwse cyclc operator (CCWC): y-cwc: x k : (x + y) mod r y-ccwc: x k : (x y) mod r (2.12) Clockwse cyclc operator s equvalent to modular sum of the two varables. Table 2.4 shows the truth table of mn, max, and modular sum operators. Defnton: The lteral s defned as: r 1 f x S x S = (2.13) 0 otherwse where S M. If m = 2,.e. bnary case, then we get element set the brackets can be omtted and { 1} x = x and { 1} x can be wrtten as { 0} x = x'. If S s a sngle 1 x. Defnton: The wndow lteral or, lteral s defned as:, r 1 f a x b a = (2.14) 0 otherwse x b Defnton: The complementary wndow lteral s defned as:, r 1 f x < a or x > b a = (2.15) 0 otherwse x b

35 20 MVL unary operatons can be seen n Table 2.5. Defnton: A product term, havng the value of k (k r 1) s gven by P k : {0,1,2... n} g( x ) = k (2.16) where, g(x ) refers to a unary operator such as lteral, cyclc operator or any other, and, refers to mn operator over unary operators. Defnton: A multple-valued combnatonal functon can be expressed n terms of products as: j f x, x... x n ) = P ( 0 1 (2.17) where mples the max operator and P j represents all the products for the mplementaton of the functon. Any mult-valued functon has a canoncal expresson n chan-based Post algebra n terms of max, mn and lterals, whch are defned above. As an example, a two-varable, 3- valued functon shown n Fgure 2.4 has the followng canoncal expresson: f ( x x x , x2) = 1 x1 x2 + 1 x1 x2 + 2 x1 x2 + 2 x1 x x 1 x Fgure 2.4. An example mult-valued functon

36 21 Table 2.4. Truth table of Mn, Max and Modular Sum (Msum) operators Mn r r r-1 Max r r r r-1... r-1 r-1 r-1 r-1 r-1 Msum r r r-1 r x(r-1) mod r Name Table 2.5. MVL unary operatons Notaton Defnton Cycle x k (x + k) mod r Cycle Counter clockwse x k (x - k) mod r Successor x+ (x + 1) mod r Predecessor x- (x 1) mod r Complement (negaton) x' (r 1) x Selecton lteral (lteral) x S r 1 f x n S; 0 otherwse Wndow lteral x a,b r 1 f a<=x<=b; 0 otherwse Complementary wndow lteral a b x, r 1 f x<a or x>b; 0 otherwse

37 22 Property 2.1.1: The followng propertes of lterals hold: j x x = 0, for any, j M, j. m 1 = 0 x = 1. For example, the functon n Fgure 2.4 can be represented as f ( x x , x2) = 1 x1 x2 + 1 x1 x where + s max and. s mn operators. Here, max(a, b) = a for any followng rule can also be used for smplfcaton [28]. a b, a, b M. The Property 2.1.2: Let a and b be constants n M such that a b. Then j j j a x1 + b x2 = a ( x1 + x2 ) + b x2. Usng the above property, the functon n Fgure 2.4 can be reduced to: f ( x = x. 1 1, x2) 1 x Furthermore, the constant 2 can be omtted from the product terms snce 2 s the unt functon (m-1 = 2) by defnton. As a result the functon reduces to: f ( x x + x 1, x2) = There are varous references about mult-valued logc mnmzaton. Some of whch appear n [33-37].

38 Functonal Completeness of Mult-Valued Logc of Post Algebra Functonal completeness s a crtcal ssue for logc functons where, f t s provded, any knd of logc crcut can be realzed. Once a complete set of functons s defned, any logc crcut can be constructed from the gates mplementng the prmtve functons from ths set. Basc defntons of functonal completeness of chan based Post algebra s defned n [28, 29].

39 24 BINARY AND MULTI-VALUED CURRENT-MODE LOGIC DESIGN In ths chapter, an ntroducton to current comparators and current-mode bnary logc (source-coupled logc) s gven. Furthermore, some of the current mode mult-valued crcuts appearng n the lterature are explored. The am s to gve a bass and comparson for the contrbutons n ths work Current Comparator Crcuts Current comparator crcuts are the most common buldng blocks of current mode logc crcuts. One of the smplest and most popular current comparator crcuts has been proposed n [38]. The crcut s shown n Fgure 3.1. (a) (b) Fgure 3.1. (a) Current comparator crcut wth voltage mode output; (b) representaton of equvalent output capactance

40 25 Here, the nput current I IN s compared to the threshold current I TH. In the crcut, the current I IN s coped to M 2. When the nput current s less than the threshold current, the output voltage wll become hgh. Hgh f I IN < ITH V 0 = (3.1) Low f I IN ITH The transstor M 2 behaves as an actve loaded nverter. A large gan s desred to provde a sharp comparator transton and greater nose margn. Assumng that the equvalent capactance at the output s assumed as C, the delay of the crcut s estmated by: t DELAY α C VDD I I x T (3.2) Ths delay s controlled by the nput current range ( I x - I T ), supply voltage (V DD ) and equvalent nput capactance C. Another current comparator crcut s proposed n [7]. The crcut and ts equvalent s shown n Fgure 3.2. (a) Fgure 3.2. (a) Threshold comparator [7]; (b) equvalent crcut (b)

41 26 The threshold functon s defned as: I y 0 = I m f I x f I x < I T I T (3.3) Here, the transstor M 1 s assumed to operate n the saturaton regon. For multvalued logc desgn, each logc level s defned as multples of I 0 unt current. The comparator values are set between n between each logc level such as I T = 0.5 I 0 to detect logc level 1 (.e. I 0 ), I T = 1.5 I 0 to detect logc level 2 etc. In the worst case, the dfference between the comparson current and varable current s 0.5 I 0. Usng (3.2) the worst case delay of a comparator s estmated as: t DELAY α V C DD (3.4) 0.5I 0 It s possble to reduce the delay by decreasng the supply voltage V DD, or alternatvely ncreasng the unt current I 0. However, ncreasng the logc level current ncreases power dsspaton. In the followng sectons, current mode bnary logc and a smlar scheme for multple-valued mplementaton wll be explaned Bnary Current-Mode Logc (Source-Coupled Logc) Crcuts Snce current-mode mult-valued crcuts wll be explored, bnary current mode logc (source-coupled logc) crcuts are analyzed here n order to compare the functonalty of the mult-valued crcuts. In addton, t s possble to use current mode bnary crcuts n some buldng blocks of MVL crcuts when needed. A dgtal crcut style that seems to be promsng n both reducng power consumpton and provdng an analog frendly envronment s MOS Current Mode Logc (MCML). The Source-Coupled Logc (SCL) s synonymous wth MOS Current-Mode Logc (MCML), where SCL expresson s more popular n the lterature. In the past, hghspeed dgtal ICs were often realzed n S bpolar and III/V compound technologes. However, as the feature szes scales down, nowadays t s possble to realze hgh speed

42 27 ICs at Ggabt/s speeds wth CMOS crcuts [39]. Moreover, f current mode logc (or source couple logc equvalently) crcuts are used, even hgher speeds can be acheved because of ts shorter logc level voltage swng [40, 41]. Whle bpolar CML, a dervatve of emtter coupled logc (ECL), has been used for years n hgh performance applcatons, t has become less desrable over tme due to ts hgh statc power consumpton and relance on bpolar processng [42]. The deal gate mplemented n source-coupled logc manner s shown n Fgure 3.3. It conssts of three man parts: the pull up resstors, the pull down network swtch, and the current source. The nputs to the pull down network (PDN) are fully dfferental. In other words, the true and complement of all logcal nputs must be present. The PDN can mplement any logc functon but must have a defnte value for all possble nput combnatons. In general, the desgn of the SCL pull down network s smlar to other dfferental logc styles such as dfferental cascode voltage swtch logc (DCVSL) or dfferental splt-level logc (DSL). Fgure 3.3. Bnary Current Mode Logc crcut Unlke DCVSL or DSL, the pull down network n MCML crcuts s regulated by a constant current source. The pull down network steers the current I to one of the pull up resstors based upon the logc functon beng mplemented. The resstor connected to the current source through the PDN wll have current I and a voltage drop equal to V = I R. The other resstor wll not have any current flowng through t and ts output node wll be pulled up to V DD n the DC state. If we look at the dfferental output voltage, the total