SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR

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1 Look-Ahead Circuitry Enhances Cascaded Counters Fully ynchronous in Count Modes Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear Package Options Include Plastic mall-outline () Packages, Ceramic Chip Carriers (FK), and tandard Plastic (N) and Ceramic (J) 00-mil IPs description The AL19A are synchronous, reversible, 4-bit up/down binary counters. ynchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count/clock ( or OWN) input. The direction of the count is determined by which count input is pulsed while the other count input is high. N4AL19A, N4AL19A N4AL19A...J PACKAGE N4AL19A... O N PACKAGE (TOP VIEW) Q A OWN NC Q C Q Q A OWN Q C Q GN All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load () input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-n dividers by simply modifying the count length with the preset inputs. A high level applied to the clear (CL) input forces all outputs to the low level. The clear function is independent of the count and inputs. The, OWN, and inputs are buffered to lower the drive requirement, which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words. These counters are designed to be cascaded without the need for external circuitry. The borrow () output produces a low-level pulse while the count is zero (all Q outputs low) and the OWN input is low. imilarily, the carry () output produces a low-level pulse while the count is 9 or 1 (all Q outputs high) and the input is low. The counters can then be easily cascaded by feeding and to the count-down and count-up inputs, respectively, of the succeeding counter. The N4AL19A is characterized for operation over the full military temperature range of C to 12 C. The N4AL19A is characterized for operation from 0 C to 0 C V CC A CL C N4AL19A... FK PACKAGE (TOP VIEW) Q NC Q GN NC V CC C A NC No internal connection CL NC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. POUCTION ATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1996, Texas Instruments Incorporated POT OFFICE X 60 ALLA, TEXA 26 1

2 logic symbol CL 14 CTIV16 CT = CT = 1 G1 4 OWN 1 1 2CT = 0 G2 11 C 12 A C [1] [2] [4] [8] 2 6 QA Q QC Q This symbol is in accordance with ANI/IEEE td and IEC Publication Pin numbers shown are for the, J, and N packages. 2 POT OFFICE X 60 ALLA, TEXA 26

3 logic diagram (positive logic) CL OWN 4 A 1 C1 1 QA 1 1 C1 2 Q C 10 C1 1 6 QC 9 C1 1 Q Pin numbers shown are for the, J, and N packages. POT OFFICE X 60 ALLA, TEXA 26

4 typical clear, load, and count sequence the following sequence is illustrated below: 1. Clear outputs to zero 2. Load (preset) to binary 1. Count up to 14, 1 (carry), 0, 1, and 2 4. Count down to 1, 0 (borrow), 1, 14, and 1 CL A ata Inputs C OWN QA ata Outputs Q QC Q equence Illustrated 0 Clear Count Up Count own Preset NOTE: A. Clear overrides load, data, and count inputs.. When counting up, count-down input must be high; when counting down, count-up input must be high. 4 POT OFFICE X 60 ALLA, TEXA 26

5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) upply voltage, V CC V Input voltage, V I V Operating free-air temperature range, T A : N4AL19A C to 12 C N4AL19A C to 0 C torage temperature range, T stg C to 10 C tresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions N4AL19A N4AL19A UNIT MIN NOM MAX MIN NOM MAX VCC upply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current ma IOL Low-level output current 4 8 ma fclock Clock frequency MHz CL high tw Pulse duration low 2 20 ns or OWN high or low ata before 2 20 tsu etup time CL inactive before or OWN ns inactive before or OWN ata after th Hold time high after OWN 0 ns OWN high after 0 TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TET NITION N4AL19A N4AL19A MIN TYP MAX MIN TYP MAX VIK VCC = 4. V, II = 18 ma V VOH VCC = 4. V to. V, IOH = 0.4 ma VCC 2 VCC 2 V VOL VCC =4V 4. IOL = 4 ma IOL = 8 ma II VCC =. V, VI = V ma IIH VCC =. V, VI = 2. V µa IIL or OWN All others VCC =V. V, VI =04V IO VCC =. V, VO = 2.2 V ma ICC VCC =. V, ee Note ma All typical values are at VCC = V, TA = 2 C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IO. NOTE 1: ICC is measured with the clear and load inputs grounded and all other inputs at 4. V. UNIT V ma POT OFFICE X 60 ALLA, TEXA 26

6 switching characteristics (see Figure 1) PAAMETE FOM (INPUT) TO (OUTPUT) VCC = 4. V to. V, CL = 0 pf, 1 = 2 = 00 Ω, TA = MIN to MAX N4AL19A N4AL19A MIN MAX MIN MAX fmax 2 0 MHz ns OWN ns 2 19 or OWN Any Q ns 8 0 Any Q ns CL Any Q 20 1 ns For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT 6 POT OFFICE X 60 ALLA, TEXA 26

7 PAAMETE MEAUEMENT INFOMATION EIE 4AL/4AL AN 4A/4A EVICE VCC V L = 1 = 2 1 L From Output Under Test CL (see Note A) L Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) 1 2 Test Point CICUIT FO I-TATE TOTEM-POLE OUTPUT CICUIT FO OPEN-LLECTO OUTPUT CICUIT FO -TATE OUTPUT Timing Input High-Level Pulse ata Input tsu th Low-Level Pulse tw VOLTAGE WAVEFOM ET AN HOL TIME VOLTAGE WAVEFOM PULE UATION Output Control (low-level enabling) Waveform 1 1 Closed (see Note ) tpzl tphz tplz VOL tpzh Waveform 2 VOH 1 Open (see Note ) 0 V VOLTAGE WAVEFOM ENALE AN IALE TIME, -TATE OUTPUT Input In-Phase Output Out-of-Phase Output (see Note C) VOH VOL VOH VOL VOLTAGE WAVEFOM POPAGATION ELAY TIME NOTE: A. CL includes probe and jig capacitance.. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch 1 is open.. All input pulses have the following characteristics: P 1 MHz, tr = tf = 2 ns, duty cycle = 0%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POT OFFICE X 60 ALLA, TEXA 26

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