Solutions for LCD TV Super IP Applications

Transcription

1 Solutions for D T Super IP Applications By Simon in and Stephen i, Fairchild Semiconductor Abstract: Super inverters or high voltage inverters for D Ts continue to draw a tremendous amount of market attention due to their high efficiency and lower cost. This article conducts a circuit analysis and reviews the practical design considerations for Super IP converters in a inch D T application. It also explores transformer and circuit design in D T applications.. onventional Block vs. Super IP Block In today s D T inverter designs, designers are usually seeking solutions that offer high efficiency, but at minimal cost. With conventional topologies, it is difficult to improve the efficiency without increasing the cost. As a result, Super inverters or high voltage inverters have been offered as a viable solution since these products save the main output s rectification circuit. There are many different types of Super IP topologies, but this paper will focus on one of the topologies shown in Figure, which is suitable for a U-shaped lamps D T. D38fromPF output M T3 F HI T M T F T T F3 PWM output Backlight I T F FB Figure. Super IP D T Power Block In the above Super IP block Figure, the power stage and inverter stage have been combined into one stage to improve the total efficiency and save the cost. The halfbridge block supply directly comes from the primary side of PF 38 output, and

2 T works as the primary side and secondary side isolation transformer. The resonant tank circuit, which is made of series cap, T, T3, T, T & T as well as F, converts the square-wave voltage to a sinusoidal output to drive the F.. urrent Balance urrently, U-shape lamps are commonly adopted by panel suppliers to reduce cost and power losses. However, for both terminals P and P of the U-shape lamp require operating in high voltage, it is very difficult to sense the lamp current, since you cannot directly measure the lamp s current by insert a sensing resistor in a series with a lamp. And it is also difficult to control the U-shape lamps current balance due to the difference of lamp impedance. An inverter circuit consists of an inverter transformer, inside secondary side leakage inductance, lamp operation impedance and resonant caps as well as the lamp parasitic cap lamp. Here, the lamp operation impedance is simplified as a resistor lamp. Figure shows the lamps current value with frequency variation. It is interesting that the lamp current MS value meets together at f resonant point while the lamp in Figure3 is varied from K to Mohm. The f resonant point is decided by the 3 and lamp, and. It means that we can easily get current balance if the operating frequency is close to f. Ilamp ua ua 8uA fo ua A KHz KHz KHz 8KHz KHz... Ilamp Frequency f Figure. amp urrent s Frequency, lamp frequency

3 S Figure 3. Simplied tank circuit The circuit in Figure 3 is a simplified inverter resonant circuit. It consists of inverter transformer leakage inductance, and which is made by lamp parasitic cap paralleled with outside caps, and amp equivalent resistor. Then the lamp current transfer function I is expressed as below. S S I. S. S.3 If, then the I S, which is not related with lamp value, we can make constant current inverter. The amp current MS value is decided by the s, the inverter transformer leakage inductance and value. And we also learn the current curve around f π is more closer, if the is more smaller.

4 3. A Half-Bridge MOSFET Switching Feature Another issue is that the half-bridge MOSFETs turn-on spike. Figure is the simulation waveform with a small duty cycle. There is big current spike when high side MOSFET S or low side MOSFET S turn on. The turn on loss of S and S is very big and the efficiency is not good. Switching noise is also a big challenge since it can negatively impact the overall system reliability. First, assuming the half-bridge load is inductive and the current waveform lags behind with oltage waveform, D is the High side MOSFET S body diode, and D is the low side MOSFET S body diode. t->t: Before t<t, S was turning on, and the transformer primary current I was negative, at tt, S is turned off, causing the current I to charge and discharge, and the switching node s voltage are charging to 38.@t. t->t: D starts to turn on, the transformer primary side current charge the 38D input power and the current reduce t->t3: The D turns off, the resonant between,tx primary side inductance, and / start, the switching node s voltage reduces to negative voltage make D turn on first, then the s voltage become positive. t3->t: The dead time finish, the high side gate drive turns on the MOSFET. There is a large current spike conducted at MOSFET I DS. To reduce the current spike, we need to increase the and 8 turns on duty to close to % to make the S and S ZS. Then we can get square-wave voltage at the halfbridge switching node. On the other hand, we use Fairchild s FFET to reduce the MOSFET body diode recovery during switching transition time to enhance the inverter ruggedness even in hard-switching conditions.

5 - tt t t3 t t t :,:- 8: I I s : A A I8 SE>> -A.8ms.8ms.8ms.88ms.ms.ms.ms.ms.8ms.ms -I8 Time Figure. Operating Waveform. Fairchild Production eady Board Figure is a Fairchild total solution for a U-shaped lamps D T block diagram. D FFPF8HSTU A~ ~ - ~ M3 FPF HI FA38 M FDPFU T T3 T F F PF I FA3 T M FDPFU T F3 PWM output Backlight I FA33 T F FB T D M FYPF FPF3 /3A STB PWM I FAB M D3 FYPF M PDS888 STB /3A STB FPF38 S Figure.Super IP Fairchild Block Diagram

6 p s s The specifications for this circuit were: - amps typical operating voltage: MS - amps typical operating current:.ma MS - amps starting voltage: 38rms@ Ta º - amps typical operating frequency: Khz - Backlight typical power consumption: W - Output /3A for Audio Amp, /3A for USB. - Standby power<.w@a, with Standby /.A for MU - Open amp Protection, amp Short protection, amp over voltage protection - urrent balance :</-% The Backlight PWM I FA33 was selected as it provided all the control functions, such as soft start, open lamp regulation, open lamp protection, over voltage protection, short circuit protection, UO, and synchronization circuit with an external signal for a series parallel resonant converter. At the same time, external component count is minimized and system cost is reduced by integration. It also supports analog and burst dimming modes of operation. The FA33 provides all the control functions for a series parallel resonant converter as well as a pulse width modulation PWM controller to develop a supply voltage. F3 FUSE 38PF Output D 8 8 D FDPFU T8 p/3k D3 8 BA D3 3 3K 3 BA D38 BA O SP H 3 T3 8 DIE TAS 8 K 8 B D K 8 K T 8 8 HI HO n p/3k K D3 3 I S.uF/ 8 OM O T K U 8 8 FA38 3 D D D D E8 p/3k D33 8 BA FDPFU K K K uf/3 SP n D8 8 D EF 8 p/3k K OP 3 D U K 8 K K T OP OP3 8 OP OP3 3K 88 3K 3 3 K nf S OP 3K 8 K p/3k n OP OP 3 D3 O K 3 8 BA n EF 3 SS_MP O n k 8 n k nf FB BT k K K K nf BDIM~3.3 BDIM T 8 EF k p/3k K K n ADIM SP K k O/OFF T EA S 8 n 8 3 GD OUTH p/3k OUT B D BA 8 u/3 EF 8 K n n 8 n p/3k K 3 K 3 K 3 K K D. OP S D3 D 3K 3 BA BA D3. OP S D3 D3 3K 3 BA BA D. OP S D3 D3 3K 3 BA BA D. OP 8 O SP O SP O SP H H H S Figure. FA33 Backlight Super IP circuit. Design procedure

7 Set first stage Transformer T spec. T isolates the primary side ground and secondary side ground, and convert 38 PF high voltage to a middle square voltage /-8 to drive secondary transformer. And T primary inductance should be large enough, so that the and T primary resonant frequency are far smaller than the operating frequency K and the tank circuit will be inductive load for the half-bridge converter to achieve ZS. First, we choose.uf/, set and T primary inductance resonant frequency to khz, which is lower than the operating frequency khz. T primary inductance is. mh. uf π f π khz hoose T primary inductance mh, and EE8 core, with A e 8 mm, The T primary minimum turns is t 8. us.3 T 8 mm in max p min B A e 8. We choose pturns, T primary secondary turns is s p p s 8. We choose sturns, so secondary output voltage is s p s 8. 3 p Set Second stage Transformer T spec. T, T, T, T8 are same transformers to convert the square voltage to square-wave voltage and then to a sinusoidal output to drive the F. First, we set the secondary resonant circuit frequency f khz,, from., the leakage inductance is

8 k. H l π khz we chose turns is l.h, and EE core, with A e mm, T primary minimum t us.t mm in max p min B A e. Transfer the T input square-waveform to sinusoidal wave, the fundamental sinusoidal wave MS oltage is π rms in sin D π. sin. π π From.3, the transformer turn ratio is n 3. lamp rms khz khz. khz khz egarding minimum primary turns, minimum turns ratio and leakage inductance, we can then determine primary turns, turns ratio and the gap of core to get the required leakage inductance. For this application, the number of primary turns is 8Ts and that of the secondary turns is Ts whereas the Turns ratio is Determine The equired Output apacitance, Assume a parasitic capacitance per U shape lamp is pf. Each parasitic capacitance is effectively in paralleled with the output capacitors. Then the output capacitor is p para pf pf pf π khz k amp we choose & pf.

9 Summary With the consumer demand for highly efficient and cost-effective D Ts, high voltage inverters need to provide efficiency at a minimal cost. This article explored an innovative solution that combines the power stage and inverter stage without a conventional D-D block after the PF block. By using this advanced topology, D T system efficiency and reliability were dramatically increased, while overall system cost was reduced. EFEEES [] Jason hoi, Application ote A D Backlight Inverter Drive I FA3.Korea, Fairchild Semiconductor. [] Datasheet FA33, Fairchild Semiconductor.