Arquitectura Virtex. Delay-Locked Loop (DLL)

Transcription

1 Arquitectura Virtex Compuesta de dos elementos principales configurables : CLBs y IOBs. Los CLBs se interconectan a través de una matriz general de routeado (GRM). Posse una intefaz VersaRing que proporciona recursos adicionales de interconexión a la periferia del dispositivo. Existen otoros circuitos que se conectan a la GRM: 1) Bloques dedicados a memoriaas de 4K. 2) Relojes DLL para la distribución y compensación de retardo del reloj. Delay-Locked Loop (DLL)

2 IOB y señales soportadas

3 Bancos de I/O

4 CLBs y LCs Each Virtex CLB contains four Lcs, organized in two similar slices, as shown in Figure. The basic building block of the Virtex CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop.

5 Vista detallada del slice de Virtex

6 Conexiones locales en el Virtex

7 The Most Advanced Serial I/O Virtex-4 RocketIO transceivers Full-duplex serial transceiver blocks with integrated SERDES and Clock and Data Recovery (CDR) 622 Mbps to >10 Gbps operation Widest Range of Operation Compatible with Virtex-II Pro Supports chip-to-chip, backplane, chip-to-optics SONET 7

8 SerialSerial I/O Challenges Virtex-4 I/O Solution 1GFC 1.06 Storage 2GFC 2.12 SATA SATA CEI (OIF) XAUI GFC SATA3 3.0 GbE Networking 8GFC 4GFC CEI (OIF) 11G 10GbE OC-48 Telecom OC-12 OBSAI CPRI GbE 1.25 Computing SATA 1.5 SATA2 3.0 Support HD-SDI Video 1.45 Rate (Gb/s) PCIE Gen2 PCIE

9 World-Class Clocking High-performance Powerful DCM clocking Up to 500 MHz system clock Up to 700 MHz source synchronous clock Zero-delay buffer Phase-shift control Frequency synthesis More resources Up to 20 DCMs 32 global clocks 9

10 Fast and Flexible BRAM Enhanced architecture for higher performance 500 MHz performance Optional programmable FIFO logic Saves logic resources 500 MHz FIFO performance Tunable Block Structure Scalable and efficient memory utilization Design compatible with VirtexII Pro 10

11 Virtex-4 Secure Chip AES Provides Maximum Design Security Bitstreams encrypted with 256-bit AES algorithm Cryptographic keys automatically erased upon malicious tampering Part of standard design flow Among FPGA vendors, only Xilinx meets U.S. Government standards for secure module design 11

12 Virtex-4 Clock Management: Powerful Solutions Simplified system design Abundant resources Application-targeted features Comprehensive software support Increased system performance Lower jitter and duty cycle distortion 500 MHz clock generation and control Clocking features, performance, and flexibility unmatched by any other FPGA 12

13 Next Generation PCOUT BCOUT A:B BREG B 0 18 CEB 1 CE D Q 2-Deep Subtract 18 CEM MREG CE D RSTB A CE D Q 2-Deep PREG Q AREG CEA CEP X 36 0 CE D Y Q RSTM bit shift RSTP Z 17-bit shift RSTA CarryIn 48 C 7 OpMode PCIN BCIN 13 P

14 Integrated PowerPC 405 World s Most Popular Embedded Processor Architecture High-performance 680 DMIPS@ 450MHz Low power 0.29mW/MHz 2nd generation FPGA with PowerPC 405 Preserves HW and SW IP CoreConnect bus architecture Full array of system-level IP New APU interface Provides direct access from FPGA fabric to PowerPC core Easy microcontroller and coprocessor support 14

15 New Tri-Mode Ethernet MAC Fully integrated Ethernet Media Access Controller (EMAC) 10/100/1000 Mbps 2 or 4 cores per Virtex-4 FX device UNH-Compliant Use with PowerPC or standalone Key benefits Saves up to 4000 logic cells per Ethernet MAC Implement single-chip 1000 Base-X Ethernet Great for network management or remote FPGA monitoring Statistics Interface Processor Block Client Interface Phy Interface Client Interface Phy Interface Statistics Interface 15

16 Three Virtex-4 Platforms LX FX SX Resource Logic K LCs 23-55K LCs Mb Mb N/A 0-24 Channels N/A N/A 1 or 2 Cores N/A N/A 2 or 4 Cores N/A K LCs Memory 0.9-6Mb DCMs 4-12 DSP Slices SelectIO RocketIO PowerPC Ethernet MAC Choose the Platform that Best Fits the Application 16