10-/100-Mbps Ethernet Media Access Controller (MAC) Core

Transcription

1 10-/100-Mbps Ethernet Media Access Controller (MAC) Core Preliminary Product Brief December 1998 Description The Ethernet Media Access Controller (MAC) core is a high-performance core with a low gate count, dual operating speeds of 10 and 100 Mbps, options to support physical layer devices, and many other features that make it attractive for use in a custom ASIC design (Figure 1). The MAC core design, designed in Verilog with a nominal core size of approximately 11,000 gates, may be synthesized in 0.8-micron CMOS process technology or better. Features 10- or 100-Mbps MIl-based device support 10BASE-T 100BASE-TX 100BASE-FX 100BASE-T4 Optional interface cores: R, ENDEC, or PMD Optimized for switching and multiport applications 802.3x full- and half-duplex flow control Optional bus interface Figure 1. Functional Block Diagram Host Data Streams Host CPU Access Signals Dual-Speed MAC Data Management Network Device 10/100 Customer ASIC Including High-Level Functions 98YL-0219A (12/98) Applications The 10-/100-Mbps MAC core is optimized for applications using multiple Ethernet MACs, including switches, multiport bridges, and routers. Network interface designs Ethernet switching designs Test equipment designs The MAC core consists of six subcores, three for MAC functions and three for network I/O functions (Figure 2). The subcores, together with the additional cores, may be connected together to make a dual-speed (100 Mbps and 10 Mbps) Ethernet controller. Verilog is a registered trademark of Cadence Design Systems. A13991EU1V0PB00 1

2 Figure 2. Internal Block Diagram Host Transmit Byte Stream MACCTL 802.3x Flow Control Module TFUN Transmit Function Transmit Data Host Receive Byte Stream RFUN Receive Function Receive Data Device Host CPU Access Signals Host M M Clock Reset 98YL-0220A (12/98) Management Statistics Statistics Gathering and Vectors The transmit and receive functions of the MAC core are not instrumented with numerous counters for statistics collection. Instead the device uses a vector generation method that simplifies the timing of many asynchronous events and is more efficient in multiple MAC systems because statistics can be accumulated centrally for all of the MACs, reducing gate count and improving processing efficiency. The statistics-gathering mechanism is created outside the MAC on a case-by-case basis. Most activity in a MAC is focused on major events such as completion of packet reception or transmission attempts. For each major event, the MAC generates a statistics vector summarizing the results of the event and then latches it into a statistics collection block. There are generally two different vectors, one for receive and one for transmit. Vectors may be designed to include or exclude as many different parameters as a design requires (Table 1). Table 1. Statistics Example Transmit Status Receive Status Bit Description Bit Description 51 Transmit VLAN tag detect 50 Transmit back pressure previous packet 49 Transmit pause control frame 48 Transmit control frame 30 Receive VLAN tag detected Total bytes transmitted on wire 29 Receive unsupported opcode 31 Transmit under run 28 Receive pause frame statistics 30 Transmit giant 27 Receive control frame statistics 29 Transmit late collision 26 Dribble nibble 28 Transmit excessive collision 25 Broadcast packet 27 Transmit excessive collision 24 Multicast packet 26 Transmit excessive defer 23 Receive OK 25 Transmit broadcast 22 Field length out of range 24 Transmit multicast 21 Field length check error 23 Transmit done 20 CRC error 22 Transmit field length out of range 19 Receive code violation 21 Transmit field length check error 18 Carrier event previously seen 20 Transmit CRC error 17 RXDV event previously seen 19-6 Transmit collision byte count 16 Packet ignored 15-0 Transmit byte count 15-0 Received byte count 2

3 The vector approach reduces the requirement for individual synchronization of many individual events and also reduces gate count by eliminating the need for flip-flops throughout the MAC design. When multiple MAC designs are involved, using a statistics collecting block common to all MACs is easier than distributed gathering for parsing cumulative and derivative statistics. Switch Building Block The MAC core is optimized for use in multiple MAC applications, including switches, multiport interface cards, and routers. Figure 3 shows a typical application where the MAC core is used as a building block for an eight-port switch. Figure 3. Eight-Port Ethernet Switch Application Common System Transport, Address Recognition, and Statistics Common Host Processor 98YL-0221A (12/98) The exact nature of the common sections for system data transport, address recognition, and statistics will be application-dependent. The MAC core has built-in flexibility to accommodate almost any system design. The physical () devices may be internal to the design or external. With the internal, the may be a logical implementation without line driving capability, and the ports may be dualspeed or fixed at one speed. The MAC core can be adapted to each of these variations in design. 3

4 Network Controller Figure 4 shows the MAC core implemented in a network controller chip used to create a PCIbased network controller for PCs. Figure 4. Single MAC Core Implementation End Station Bus Host Bus Module Address Recognition Statistics Gathering 98YL-0222A (12/98) Management statistics are generated as vectors by the MAC core. A mechanism creates and collects the vectors and then parses the information appropriately. The generalized byte date streams may interface to almost any bus type, including IISA, PCI, MCA, VLB, S-Bus, Nubus, SCSI, Multibus, and others. Depending on the sophistication of the bus, the bus interface core implementation can range from simple to complex. Host The 10-/100-Mbps MAC connects to any one of a number of host system types. In a switching system, the host is generally the embedded CPU, or the backplane switching fabric (Figure 5). In a general network interface, the host might be a general-purpose computer communicating over the computer bus. Many different types of host interfaces may be used, including sophisticated bus mastering types such as PCI, shared memory, ring buffer, DMA and FIFO-based designs. FIFOs are useful for implementing the MAC core in an ASIC since the ASIC vendor s cell library may include appropriate FIFO cells. Figure 5. to Host System Address Recognition Logic Receive Byte Stream Receive Byte Stream Logic Host System Transmit Byte Stream Logic Transmit Byte Stream Host Processor Statistics Vector 98YL-0224A (12/98) 4

5 The MAC core communicates with external devices through the logical interface, which is divided into two signal sets (Figure 6). One set handles data transmission and reception, while the second set handles management functions. Figure 6. Data and Management Signal Sets Host System Data Management 98YL-0223A (12/98) Within the MAC core, the data functions are handled by the TFUN and RFUN cores. The management set is handled by the M core. Host access to the management interface in on a word basis through the normal host interface. The interface between the M and the external is a clocked serial interface as defined by the IEEE 802.3u specification. 5

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