PCB Manufacture Designing with RF and EMC issues in mind

Transcription

1 PCB Manufacture Designing with RF and EMC issues in mind Tim Jarvis BSc CEng MIEE MIEEE Radio & EMC Specialist Section 1: EMC and PCB Design Slide 2 1

2 Single sided PCB - track Very old fashioned Nice antenna! Slide 3 Double sided PCB track pair Two parallel tracks have constant impedance Not very practical Slide 4 2

3 Multi-layer PCB with GND plane Track and ground have constant impedance Practical track can be routed anywhere BUT track still radiates! Even if properly terminated Slide 5 Transmitting digital signals Basic Square Wave Amplitude Vdd Period = T (even MS ratio) t r = t f (same rise and fall time) Slide 6 3

4 db Take the FFT of Basic Square Wave Fundamental 0dB = Vdd/2 2 3rd 5th 7th F=1/2t r Region 1 Roll_off = 6dB/octave Region 2 Roll-off = 12dB/octave In practice even harmonics are also present due to uneven MS ratio of real signals /T 2/T 3/T 4/T 5/T 7/T 9/T etc (log frequency) Slide 7 db 0 Take the transfer function of a track λ/4 3λ/4 5λ/4-20 λ/2 6dB/octave region Resonant region Example: 200 mm PCB track Courtesy of Keith Armstrong Cherry Clough Consultants ,000 2,000 MHz Slide 8 4

5 db 0-10 Convolve the two spectra original square wave envelope 16 MHz clock, tr=tf=2ns, 200mm PCB Track Radiated Component Convolution of antenna and square wave spectra ,000 2,000 MHz Slide 9 Back into time domain - FFT -1 original square wave Radiated Noise Transmitted Square Wave Slide 10 5

6 The PCB ground plane Adds shielding Form constant impedance transmission lines Reduces emissions And improves immunity Slide 11 Is the 2-layer PCB dead? Does the ground plane force a multi-layer solution? NO! we can still make a ground plane one side And place the tracking on the other side And use small apertures in the ground plane to cross tracks over. Slide 12 6

7 2-layer ground plane example Bottom tracking micro, mixed signal & RF TX Slide 13 2-layer ground plane example Top tracking ground plane with apertures Slide 14 7

8 Zooming in on the routing Section of routing Add ground plane Slide 15 Working out the maximum aperture The 1 st resonant length of an aperture is λ/2 λ/20 is an order of magnitude smaller λ for 1 GHz is 300/1000 M = 30 cm Therefore 15mm is a good figure of merit aperture limit for a 2 layer PCB with ground plane. This is quite large! NB: a 15mm track grid is as good as a solid ground plane (to 1 GHz) for most applications, and it will improve copper balance. Slide 16 8

9 Ground plane resonance Particularly an issue for immunity, but also an emissions issue as we ll see. Uniform field At resonance large RF voltage variations occur across ground plane These are not exactly matched in components and traces Resulting in differential RF voltages signal-to-ground All semiconductor junctions demodulate the envelope Sensitive analogue circuits are particularly vulnerable Slide 17 Improving Immunity Find sensitive circuit(s) Isolate them from rest of the PCB (disconnect them from all antennae) One method I ve used is remove sensor circuits from the ground plane Give them their own small isolated planes Another method is to use screening can(s) Whatever the method it will involve segregation and isolation Slide 18 9

10 Power plane pairs (4 layer example) t r Classic 4-layer stack still much used But the worst topology for EMC! Wideband noise source (CMOS power) Coupled to a large patch antenna Slide Vdd impulse FFT (In a synchronous system) Fundamental 3rd 5th 7th F=1/2t r NB: t r = current impulse rise time and is faster than signal rise time. Region 1 Roll_off = flat Region 2 Roll-off = 6dB/octave Amplitude depends on Supply impedance (Assume this is flat) -60 1/T 2/T 3/T 4/T 5/T 7/T 9/T etc (log frequency) Slide 20 10

11 Power plane patch antenna Small power planes are best (<= 75 mm for 1 GHz) Slide 21 Power plane separation Close is best (<=2 requires specialist PCB manufacturing techniques) Slide 22 11

12 Interaction with decoupling caps The more caps the better (but they have little effect in resonant region) Slide 23 Interaction with decoupling caps (continued) 2 plane separation is better than 99 * 10nF Caps with a 0.8mm freq>λ/4 Slide 24 12

13 What value of decoupling cap? <1nF caps are not recommended because their LC ratio (parasitic L) is significant for resonance. Plain old 100nF caps are usually best (lots and lots of them) Slide 25 What about power plane shape? Non-trapezoidal irregular shapes are best (but not much better) Slide 26 13

14 Improved 4-layer stack order Asymmetrical is best Greatest free decoupling capacitance Highest damping factor Signal traces are only coupled to ground-plane Signal transmission lines have roughly constant impedance when changing layer (Vias). (but cross-talk is increased) Copper balance can be restored By hatching the power planes Watch out for isolated vias! Slide 27 4-Layer stack no power plane 10 pre-peg separation still isn t very good for damping patch resonance. Experimentation has shown that having no power plane is better To learn more Slide 28 14

15 6-layer construction types Sequential Build Multi-core Build Need to know how your PCB will be built before assigning layers! Slide 29 8-layer construction example SM-Pads, short traces, ground fills. Built on 3 x 12 cores Routing 1. Ground plane 1. Power planes 1. Routing 2 + one small power plane. Ground plane 2. Routing 3. SM-Pads, short traces, ground fills. Power and ground planes are closest (prepreg) Power is wrapped in ground. Outer layers have as much ground fill cover as possible. All grounds stitched on 10mm grid. Roughly same route-ability as 6 layers. Slide 30 15

16 Segregating power planes Segment power planes to: Isolate noisy, susceptible and I/O circuit blocks, Allow for different supply voltages on same layer, Minimise plane size to push resonant region up (<75mm, 1GHz) BUT beware, common clocks create antenna arrays! Slide 31 Stitching ground planes Some stitch outer ground fills around the PCB edge To remove edge effects and create a Faraday Cage But the same then punch holes in the cage for components Therefore it s better to connect all ground layers and fills on a regular grid where apertures (between grid vias) are reduced to <λ/20 Slide 32 16

17 Cutting ground planes Putting a cut in a ground plane isn t necessarily a bad thing to do, but it must be done with great care and only if absolutely necessary. i.e. when isolating noise currents in the plane. Never-ever route tracks over a ground plane cut. Signal reflections Plane cross-coupling Poor signal integrity If you must cut the ground plane always use a well-placed filter to cross the gap. Slide 33 Simple DIY Filters (to 1 GHz) Making filters symmetrical gives equal isolation in both directions. Why not show the barrier boundary on your schematic? High Impedance Signal Use existing resistance of 10 kω or greater. Medium Impedance Signal Use existing resistance of 1 kω or greater and add 100pF capacitor. Low Impedance Signal Add 150 nh and 100pF capacitor. Remember components limitations! 0603 NPO 100pF capacitor, ~900 MHz nf chip inductor, ~900 MHz Slide 34 17

18 Section 2: RF and PCB Design Slide 35 Segregate segregate - segregate Don t mix tracks from one block with another. Separate circuit blocks: noisy, i/o and sensitive. Vital for RF and EMC performance alike Slide 36 18

19 Use via walls at boundaries These vias also for thermal management of RF TX output transistor. Contain edge-effect emissions by creating a via-wall all around the screening can land. NB: this can is seam soldered to the PCB Slide 37 Place filters properly Lay the inline filter component across the boundary with any shunt components right behind it and directly tied down to the ground plane. Slide 38 19

20 Real components Spice model: C=100pF ESR=0.2Ω ESL=0.25nF 100pF 0603 Component on PCB 1 KΩ PCB: Cpads=0.33pF Lvia=2nF component Essential to correctly model component, pad and trace parasitics. Slide 39 Using parasitics to make a good filter Example: Pass 1 2 GHz, stop 3 4 GHz Performance without modelling parasitics Slide 40 20

21 Using parasitics to make a good filter Now include selected parasitics into model Without modelling parasitics Including selected parasitics Slide 41 Now to implement the filter L1=10nH C1=1pF L2=9nH C2=1.5pF L3=7nH NB: can progressively cut GND vias to tune a filter These two λ/4 stubs create a notch at 2.5 GHz Insert between mixer output and buffer input Slide 42 21

22 And measure the performance Actual measured performance on PCB Slide 43 RF and EMC issues in mind THE END Question from the floor Tim Jarvis BSc CEng MIEE MIEEE Radio & EMC Specialist 22