Memory Management. 3.1 Fixed Partitioning

Transcription

1 Chapter 3 Memory Management In a multiprogramming system, in orer to share the processor, a number o processes must be kept in memory. Memory management is achieve through memory management algorithms. Each memory management algorithm requires its own harware support. In this chapter, we shall see the partitioning, paging an segmentation methos. In orer to be able to loa programs at anywhere in memory, the compiler must generate relocatable object coe. Also we must make it sure that a program in memory, aresses only its own area, an no other program s area. Thereore, some protection mechanism is also neee. 3.1 Fixe Partitioning Memory (n KB) Small (3n KB) Meium (6n KB) Large In this metho, memory is ivie into partitions whose sizes are ixe. is place into the lowest bytes o memory. Processes are classiie on entry to the system accoring to their memory they requirements. We nee one Process Queue (PQ) or each class o process. I a process is selecte to allocate memory, then it goes into memory an competes or the processor. The number o ixe partition gives the egree o multiprogramming. Since each queue has its own memory region, there is no competition between queues or the memory. Fixe Partitioning with Swapping This is a version o ixe partitioning that uses RRS with some time quantum. When time quantum or a process expires, it is swappe out o memory to isk an the next process in the corresponing process queue is swappe into the memory. 2K 6K P4 P5 12K empty empty Lecture Notes by Uğur Halıcı 18

2 Normally, a process swappe out will eventually be swappe back into the same partition. But this restriction can be relaxe with ynamic relocation. In some cases, a process executing may request more memory than its partition size. Say we have a 6 KB process running in 6 KB partition an it now requires a more memory o 1 KB. Then, the ollowing policies are possible: Return control to the user program. Let the program ecie either quit or moiy its operation so that it can run (possibly slow) in less space. Abort the process. (The user states the maximum amount o memory that the process will nee, so it is the user s responsibility to stick to that limit) I ynamic relocation is being use, swap the process out to the next largest PQ an locate into that partition when its turn comes. The main problem with the ixe partitioning metho is how to etermine the number o partitions, an how to etermine their sizes. I a whole partition is currently not being use, then it is calle an external ragmentation. An i a partition is being use by a process requiring some memory smaller than the partition size, then it is calle an internal ragmentation. 2K 6K 12K (2K) Empty (6k) (9K) Empty (3K) External ragmentation Internal ragmentation In this composition o memory, i a new process,, requiring 8 KB o memory comes, although there is enough total space in memory, it can not be loae because ragmentation. 3.2 Variable Partitioning With ixe partitions we have to eal with the problem o etermining the number an sizes o partitions to minimize internal an external ragmentation. I we use variable partitioning instea, then partition sizes may vary ynamically. In the variable partitioning metho, we keep a table (linke list) inicating use/ree areas in memory. Initially, the whole memory is ree an it is consiere as one large block. When a new process arrives, the searches or a block o ree memory large enough or that process. We keep the rest available (ree) or the uture processes. I a block becomes ree, then the tries to merge it with its neighbors i they are also ree. There are three algorithms or searching the list o ree blocks or a speciic amount o memory. First Fit : Allocate the irst ree block that is large enough or the new process. This is a ast algorithm. Lecture Notes by Uğur Halıcı 19

3 Best Fit : Allocate the smallest block among those that are large enough or the new process. In this metho, the has to search the entire list, or it can keep it sorte an stop when it hits an entry which has a size larger than the size o new process. This algorithm prouces the smallest let over block. However, it requires more time or searching all the list or sorting it. Worst Fit : Allocate the largest block among those that are large enough or the new process. Again a search o the entire list or sorting it is neee. This algorithm prouces the largest over block. Example 3.1 Consier the ollowing memory map an assume a new process P4 comes with a memory requirement o 3 KB. Locate this process. <ree> <ree> <ree> 10 KB 16 KB 4 KB a. First it algorithm allocates rom the 10 KB block. b. Best it algorithm allocates rom the 4 KB block. c. Worst it algorithm allocates rom the 16 KB block. New memory arrangements with respect to each algorithms will be as ollows: P4 <ree> 10 KB <ree> 10 KB <ree> 7 KB <ree> 16 KB P4 <ree> 16 KB <ree> 13 KB P4 <ree> 4 KB <ree> 1 KB <ree> 4 KB First Fit Best Fit Worst Fit At this point, i a new process, P5 o 14K arrives, then it woul wait i we use worst it algorithm, whereas it woul be locate in cases o the others. Compaction: Compaction is a metho to overcome the external ragmentation problem. All ree blocks are brought together as one large block o ree space. Compaction requires ynamic relocation. Certainly, compaction has a cost an selection o an optimal compaction strategy is iicult. One metho or compaction is swapping out those processes that are to be move within the memory, an swapping them into ierent memory locations. <ree> 20 KB <ree> 7 KB <ree> 10 KB Compaction <ree> 37 KB Lecture Notes by Uğur Halıcı 20

4 3.3 Paging Paging permits a program to allocate noncontiguous blocks o memory. The ivie programs into pages which are blocks o small an ixe size. Then, it ivies the physical memory into rames which are blocks o size equal to page size. The uses a page table to map program pages to memory rames. Page size (S) is eine by the harware. Generally page size is chosen as a power o 2 such as 512 wors/page or 4096 wors/page etc. With this arrangement, the wors in the program have an aress calle as logical aress. Every logical aress is orme o A page number p where p = logical aress iv S An oset where = logical aress mo S When a logical aress <p, > is generate by the processor, irst the rame number corresponing to page p is etermine by using the page table an then the physical aress is calculate as (*S+) an the memory is accesse. Logical memory Physical memory P0 page rame Attributes Page Table 3 P0 4 5 The aress translation in paging is shown below Logical aress Physical aress p p page rame Attributes p Logical Memory Page Table Physical Memory Lecture Notes by Uğur Halıcı 21

5 Example 3.2 Consier the ollowing inormation to orm a physical memory map. Page Size = 8 wors Physical Memory Size = 128 wors A program o 3 pages where P0 3; 6; 4 Logical Program Wor 0 Wor 1 Page 0 (P0) Wor 7 Wor 8 Wor 9 Page 1 () Wor 15 Wor 16 Wor 17 Page 2 () Wor 23 Page Table Page Frame Physical Memory Wor 0 Wor 1 Frame 3 (3) Wor 7 Wor 16 Wor 17 Frame 4 (4) Wor 23 Wor 8 Wor 9 Frame 6 (6) Wor 15 Program Line Logical Aress Oset Page Number Frame Number Physical Aress Wor Wor Wor Wor Wor Wor Wor Wor Wor How to Implement The Page Table? Every access to memory shoul go through the page table. Thereore, it must be implemente in an eicient way. a. Using ast eicate registers Keep page table in ast eicate registers. Only the is able to moiy these registers. However, i the page table is large, this metho becomes very expensive since requires too many registers. Lecture Notes by Uğur Halıcı 22

6 Logical aress p PTLR: Page Table Length Register Physical aress p<ptlr? YES Access PT in Registers Access memory rat mat NO ERROR Given a logical aress to access the wor in physical memory, irst access the PT store in registers, which requires register access time (rat), an then in out the physical aress an access the physical memory, which requires memory access time (mat). Thereore eective memory access time (emat) becomes: emat= rat + mat b. Keep the page table in main memory In this metho, the keeps a page table in the memory. But this is a time consuming metho. Because or every logical memory reerence, two memory accesses are require: 1. To access the page table in the memory, in orer to in the corresponing rame number. 2. To access the memory wor in that rame Logical aress p PTBR: Page Table Base Register PTLR: Page Table Length Register Physical aress. p<ptlr? NO ERROR Access PT entry in Memory at aress PTBR + p mat Access memory mat In this approach emat is: emat= 2 * mat Lecture Notes by Uğur Halıcı 23

7 c. Use content-aressable associative registers These are small, high spee registers built in a special way so that they permit an associative search over their contents. That is, all registers may be searche in one machine cycle simultaneously. However, associative registers are quite expensive. So, a small number o them shoul be use. Logical aress p PTBR: Page Table Base Register PTLR: Page Table Length Register Physical aress p<ptlr? YES Search PT in AR FOUND? YES (hit) NO ERRO rat Access PT entry in Memory at aress PTBR + p NO (miss) Physical aress Access memory mat mat When a logical memory reerence is mae, irst the corresponing page number is searche in associative registers. I that page number is oun in one associative register (hit) then the corresponing rame number is get, else (miss) the page table in memory is accesse to in the rame number an that <page number, rame number> pair is store into associative registers. Once the rame number is obtaine, the memory wor is accesse. The hit ratio is eine as the percentage o times that a page number is oun in associative registers. Hit ratio is important in perormance o the system since it aects the eective memory access time. In the case o ining the page number in associative registers, only one memory access time is require whereas i it cannot be oun two memory accesses are neee. So, greater the hit ratio, smaller the eective memory access time. Eective memory access time is calculate as allows: where emat= h *emat HIT + (1-h) * emat MISS h = The hit ratio emat HIT = eective memory access time when there is a hit = rat + mat emat MISS = eective memory access time when there is a miss = rat + mat + mat Lecture Notes by Uğur Halıcı 24

8 Example 3.3 Assume we have a paging system which uses associative registers. These associative registers have an access time o 30 ns, an the memory access time is 470 ns. The system has a hit ratio o 90 %. Now, i the page number is oun in one o the associative registers, then the eective access time: emat HIT = = 500 ns. Because one access to associative registers an one access to the main memory is suicient. On the other han, i the page number is not oun in associative registers, then the eective access time: emat MISS = 30 + (2 * 470) = 970 ns. Since one access to associative registers an two accesses to the main memory iare require. Then, the emat is calculate as ollows: emat = 0.9 * * 970 = = 547 ns Sharing Pages Sharing pages is possible in a paging system, an is an important avantage o paging. It is possible to share system proceures or programs, user proceures or programs, an possibly ata area. Sharing pages is especially avantageous in time-sharing systems. A reentrant program (non-sel-moiying coe = rea only) never changes uring execution. So, more than one process can execute the same coe at the same time. Each process will have its own ata storage an its own copy o registers to hol the ata or its own execution o the share program. Example 3.4 Consier a system having page size=30 MB. There are 3 users executing an eitor program which is 90 MB (3 pages) in size, with a 30 MB (1 page) ata space. To support these 3 users, the must allocate 3 * (90+30) = 360 MB space. However, i the eitor program is reentrant (non-sel-moiying coe = rea only), then it can be share among the users, an only one copy o the eitor program is suicient. Thereore, only * 3 = 180 MB o memory space is enough or this case. Lecture Notes by Uğur Halıcı 25

9 User-1 PT-1 Physical P0 e1 Page# Frame# Memory e e ata e2 User-2 PT-2 5 e3 P0 e1 Page# Frame# 6 e ata1 e e1 ata ata3 11 User-3 PT-3 12 ata 2 P0 e1 Page# Frame# 13 e e ata Segmentation In segmentation, programs are ivie into variable size segments, instea o ixe size pages. Every logical aress is orme o a segment name an an oset within that segment. In practice, segments are numbere. Programs are segmente automatically by the compiler or assembler. For example, a C compiler will create separate segments or: 1. the coe o each unction 2. the local variables or each unction 3. the global variables. Main Func 1 Func 2 Data 1 Data 1 Data 3 Lecture Notes by Uğur Halıcı 26

10 For logical to physical aress mapping, a segment table is use. When a logical aress <s, > is generate by the processor: 1. Base an limit values corresponing to segment s are etermine using the segment table 2. The checks whether is in the limit. (0 < limit) 3. I so, then the physical aress is calculate as (base + ), an the memory is accesse. logical aress s base Seg. # Limit base Attr. 0 < limit NO YES acess the wor at physical aress = base + Segment S ERROR Example 3.5 Generate the memory map accoring to the given segment table. Assume the generate logical aress is <1,123>; in the corresponing physical aress. Segment Limit Base Now, check segment table entry or segment 1. The limit or segment 1 is 200. Since 123 < 200, we carry on. The physical aress is calculate as = 5623, an the memory wor 5623 is accesse. physical memory s0 s s s Segment tables are also implemente in the main memory or in associative registers, in the same way it is one or page tables. Lecture Notes by Uğur Halıcı 27

11 Sharing Segments Also sharing o segments is applicable as in paging. Share segments shoul be rea only an shoul be assigne the same segment number. Example 3.6: Consier a system in which 3 users executing an eitor program which is 1500 KB in size, each having their own ata space. eitor ata-1 eitor ata-2 eitor ata-3 user-1 ST-1 seg lim base user-2 user-3 ST-2 seg lim base ST-3 seg lim base physical memory eitor ata ata ata Lecture Notes by Uğur Halıcı 28

12 3.3. Page segmentation The iea is to page the segments an eliminate the external ragmentation problem. In page segmentation the logical aress is mae o <s,p,> triplet. The ST entry or segment S now, contains: the length o segment S the base aress o the PT or segment S. There is a separate PT or every segment. On the average, now there is hal a page o internal ragmentation per segment. However, more table space is neee. In the worst case, again three memory accesses are neee or each memory reerence. The lowchart or accessing a wor with logical aress <s,p,> is shown below. STBR s p + ST limit base 0 p limit NO ERROR + p PT or segment S STBR: Segment Table Base Register QUESTIONS 1. Why o we nee memory management an CPU scheuling algorithms or a multiuser system? Can we o without these algorithms? Explain briely. 2. a. Explain the terms: internal ragmentation an external ragmentation. b. List the memory management methos iscusse, an inicate the types o ragmentation cause by each metho. Lecture Notes by Uğur Halıcı 29

13 3. Consier a multiuser computer system which uses paging. The system has our associative registers. the content o these registers an page table or user_12 are given below: Page table or user_12 associative registers 0 9 user # page # rame # PTLR[12]:5 PTBR[12]:50000 PAGE SIZE :1024 wors For the ollowing logical aresses generate by user_12's program, calculate the physical aresses, explain how those physical aresses are oun, an state the number o physical memory accesses neee to in the corresponing wor in memory. I a given logical aress is invali, explain the reason. i. <2,1256> ii. <3,290> iii. <4,572> iv. <5,290> v. <0,14> 4. The ollowing memory map is given or a computer system with variable partitioning memory management. 0 Job Requeste memory J1 (50K) 1) J4 arrives 10K ree (45K) 2) J5 arrives 20K 3) J6 arrives 15K J2 (40K) 4) J7 arrives 20K ree (10K) 5) J3 leaves J3 (20K) 6) J8 arrives 50K ree (30K) Fin an raw the resulting memory maps, ater each step o the above job sequence is processe, or : a. irst-it b. best-it c. worst-it 5. Consier a computer system which uses paging. Assume that the system also has associative registers. a. Explain how logical aresses are translate to physical aresses. Lecture Notes by Uğur Halıcı 30

14 b. Calculate the eective memory access time given: assoc. register access time = 50 nanosec. memory access time = 250 nanosec. hit ratio = 80% c. With the above associative register an memory access times, calculate the minimum hit ratio to give an eective memory access time less than 320 nanosecons. 6. A system which utilizes segmentation gives you the ability to share segments. I the segment numbers are ixe, then a share segment table is neee, an the ST must be moiie. We shall assume that the system is capable o ynamic relocation, but to reuce the overhea, we want to avoi it unless it is absolutely necessary. The ollowing example is given or such a system : ST-6 ST-9 s# base size shares s# base size shares SST s# base size no. o sh Assume maximum number o segments per process is 256, an segments are numbere starting with 0. a. What woul be one when a segment previously unshare, becomes a share segment? b. When o we nee ynamic relocation in this system? c. Assume segment-2 o process 6 is being execute. A reerence is mae to segment-0 o process 6. How is the corresponing physical aress going to be oun?. How woul sel-reerences within share segments be hanle? e. What is the no. o sharers iel in SST use or? 7. In the X-2700 computer, logical aresses are 24 bits long. The machine implements page segmentation with a maximum segment size o 64K wors an 4K-wor pages: a. Show the logical aress structure inicating the segment, page an isplacement bits. b. How many segments can a user process contain? c. I a process has to be ully loae into memory to execute, what is the minimum physical memory capacity?. I the memory unit contains rames, show the physical aress structure. Lecture Notes by Uğur Halıcı 31

15 e. Show the unctional block structure o a suitable architecture or implementing page segmentation in the X Inicate the sizes o all necessary tables. 8. Given the memory map in the igure, where areas not shae inicate ree regions, assume that the ollowing events occur: Step event require contiguous memory size (K) i) process 5 arrives 16 ii) process 6 arrives 40 iii) process 7 arrives 20 iv) process 8 arrives 14 v) process 5 leaves - vi) process 9 arrives 30 <ree> 30 K <ree> 20 K <ree> 50 K P4 a. Draw the memory maps ater step (iv) an (vi) using irst it, best-it an worst-it allocation techniques, without compaction b. Draw the same memory maps as in part (a) i compaction is perorme whenever require. Also show the maps ater each compaction. 9. In a paging system, the logical aress is orme o 20 bits. the most signiicant 8 bits enote the page number, the least signiicant 12 bits enote the oset. Memory size is 256K bits. a. What is the page size (in bits)? b. What is the maximum number o pages per process? c. How many rames oes this system have?. Give the structure o the page table o a process executing in this system. Assume 2 bits are reserve or attributes. e. How many bits are require or each page table entry?. I physical memory is upgrae to 1024 K bits, how will your answer to c an e change? 10. Consier a segmentation system with the ollowing ata given: STBR=1000 STLR=5 Associative Registers access time = 50 nsec Memory Access time = 500 nsec Lecture Notes by Uğur Halıcı 32

16 ST AR s# base limit s# base limit Assume ata can be written into associative registers in parallel with a memory rea or write operation. For replacement o ata in associative registers, LRU policy is use. For each o the ollowing logical aresses, in the corresponing physical aress to be accesse, an the total execution time require or that access, incluing the time spent or aress translation operations. Also inicate which memory locations are accesse uring aress translation. Clearly show all changes mae in associative registers. a. <0,150> b. <0,3700> c. <2,900>. <2,3780> e. <5,200>. <1,200> 11. <ree> 9K <ree> 20 K <ree> 14 K P4 Consier the memory map given in the igure. I worst it policy is to be applie, then what will be the memory map ater arrival o the processes P5=3K, P6=5K, P7=7K P8=6K. Inicate i compaction is neee. 12. The ollowing memory map is given or a computer system with variable partitioning memory management. 9K <ree> 20 K 11K <ree> 10 K 18K <ree> 30 K event require contiguous memory size (K) i) P4 arrives 16 ii) P5 arrives 40 iii) P6 arrives 20 iv) P7 arrives 14 Fin an raw the resulting memory maps ater the above job sequence is processe completely or a. irst it b. best it c. worst it inicating whenever a compaction is neee. Lecture Notes by Uğur Halıcı 33