Arithmetic Acceleration Techniques for Wireless Communication Receivers

Transcription

1 Arithmetic Acceleration Techniques for Wireless Communication Receivers Suman Das Srihar Rajagopal Chaitali Sengupta Joseph R Cavallaro Rice niversity Center for ultimeia Communication Department of Electrical an Computer Engineering S ain St, Houston, T Abstract We evelop techniques to accelerate the implementation of the next generation wireless communication algorithms in harware We iscuss an implementation of a key computationally intensive baseban algorithm for joint multiuser channel estimation an etection for this purpose an stuy its real-time requirements An analysis of the bottlenecks present in the algorithm is mae We present an acceleration technique using task ecomposition to take avantage of the existing pipelining an parallelism flow in the algorithm We show that an application specific system esign with multiple processing elements is more effective than the conventional single processor approach as it can satisfy the high ata rate requirements of the next generation wireless communication systems Our analysis is one inepenent of the final mapping of the processing elements in harware 1 Introuction The next generation wireless communication receivers are being esigne to support enhance features such as multimeia capabilities, higher ata rates, Quality of Service (QoS) an multi-rate services in the existing wireless communication framework Wieban Direct Sequence Coe Division ultiple Access (W-CDA) is the chosen multiple access protocol for these communication systems [1] Support for high ata rates [4, 5] such as 2 bps inoor, 384 Kbps peestrian an 144 Kbps vehicular traffic is to be provie by the base-station receivers Several algorithms are being evelope for the ifferent functional blocks of the next generation base-station Currently at Texas Instruments, Inc Dallas, T This work was supporte in part by Nokia Corporation, Texas Instruments Inc,the Texas Avance Technology Program uner grant , an by NSF uner grants NCR an ANI receiver These algorithms have extremely high complexity an they put increase pressure on the next generation receivers, which have stringent time, power an size constraints One of the main computational bottlenecks in the basestation receiver is the estimation an etection of the transmitte bits from the receive signal ultiuser channel estimation an etection is being consiere as part of the avance receiver structures for next generation communication systems For our evaluation purposes, we choose one of the esigne computationally intensive algorithms for W-CDA multiuser channel estimation an etection [7] This algorithm is base on a joint multiuser estimation an etection technique which eliminates the nee for conventional extraction of parameters in channel estimation an thus gives gains both in performance in terms of Bit Error Rates (BER) as well as computational complexity This algorithm inclues chip level espreaing, which is one of the main bottlenecks in the receiver An implementation of this algorithm on a Texas Instrument s C6x DSP Simulator[9], chosen as a example of current processor technology, oes not meet real time constraints We evelop techniques to accelerate the implementation of this algorithm A task ecomposition of the algorithm is one to explore the ata epenencies between the ifferent tasks in the algorithm an take avantage of available pipelining an parallelism The analysis also shows how frequently we can upate the algorithm base on ecision feeback The main contributions of this paper are twofol First, we evelop techniques to accelerate the implementation of the wireless communication algorithms on harware, which is inepenent of the final harware mapping of the algorithm We show this specifically for the joint estimation an etection algorithm Also, we show that an application specific approach of multiple processing elements is more effective than a single processor system in meeting the realtime constraints in the base-station receiver

2 Base-station Receiver ultiple sers Antenna Demo -ulator Pilot Delay Data ultiuser Detection + Channel Estimation Decision Feeback b Decoer Detecte Bits Figure 1 Simplifie view of the Base Station Receiver 2 Joint Estimation an Detection 21 Channel oel The channel estimation an etection block in the basestation receiver is shown in Figure 1 We assume an asynchronous Coe Division ultiple Access (CDA) base system with Binary Phase Shift Keying (BPSK) moulation, where the signal is multiplie with a short repeating spreaing coe before transmission As the sprea signal is sent through the channel, it experiences unesirable effects such as elays ue to multiple paths, interference from other users, faing an noise The etector nees to acquire synchronization with the input signal in orer to correctly etect the incoming bit sequence Hence, the parameters of the channel nee to be estimate for proper etection Channel estimation involves estimating an tracking the elays of each users bits an the channel attenuation over the ifferent paths The channel estimation scheme uses the aximum Likelihoo principle [6] to estimate the channel parameters an irectly fees this information to the etector without actually extracting the channel parameters The etection scheme is the Differencing ultistage Detection metho [11], base on the principle of Parallel Interference Cancellation (PIC) [10] The etector uses the information from the channel estimation block to remove the interference from other users The channel information is built on the basis of a priori information obtaine by transmission of a pilot signal (b), which is a sequence of bits that is known at the receiver The pilot signal receive at the base-station (pilot), is compare with the known bits to form an estimate of the channel The ecisions from the multiuser etection block () are fe back to the channel estimation block along with the receive ata bits (ata), elaye by the time require for etection, for tracking the algorithm when the pilot signal is absent 22 Real-time Requirements Data transmission in the next generation wireless systems [5] is one in frames of The ata transmission can be one in variable rates epening on the spreaing factors (SF), as shown in Table 1 The table gives an example of the number of bits in a frame for spreaing factors of 4, 32 an 256 We assume BPSK moulation for our algorithm To support real-time, the number of bits etecte per frame shoul be at the rate of transmission We choose a short Gol Coe sequence of length 31 for our spreaing (which matches nearest to the propose spreaing factor of 32) This implies that the real-time requirement of our joint estimation an etection scheme is to etect input ata bits at a rate of 128 Kbps 23 Computations Involve The erivation of the joint estimation an etection algorithm is etaile in [7] We inclue the algorithm here to explain the computational aspects involve without proof The moel for the channel can be expresse as (1) where are the receive bits of all users, % ')( *,+-'/0'1( sprea * ) with a( *,+-' / spreaing ( *5476 factor,!"$ SF Bits Data Rates bps Kbps Kbps asynchronous are the bits of users to be Table 1 Propose Data Rates for Next Generation Communication Systems

3 TTTS TTTTTTTTS D E D E TTTTTTTTTTTS TTTS g i etecte, 89"/;:< is the estimate of the channel containing information about the spreaing coes, attenuation an elays from the various paths, * is the noise, which is assume to be Gaussian (AGWN) an = is the time inex The computations that occur uring the synchronization phase [7, 11] are: >@?BA C >J?B? C *GFH' *GFH' * I* * I* C >?BA where is the length of the pilot sequence, "$;: is the cross-correlation matrix between the synchronization bits * an the receive signal * >?K? an L"$;:"$ is the autocorrelation matrix The channel estimate can be obtaine by solving >?B? 5 >?BA (4) Dropping the subscript = for convenience, the matrix * can be rearrange into its o an even columns ON ' ;: which correspons to the bits +-P an in the estimate In vector form, * % NRQ ' 4 '1( *7+V' (*,+-' ')( * ( * WY [ * 3 It has been shown that etecting a block of bits simultaneously (multishot etection) can give performance gains [11] Also, multishot etection is near-far resistant as it accounts for the interference from both the overlapping symbols of the interfering users In orer to o multishot etection, the above moel shoul be extene to inclue multiple bits Let us consier \ bits at a time (= )]<0^ ^0^_ \ ) So, we form the multishot receive vector of length `\ by concatenating \ * -s a7= )]<0^ ^0^- \b 0')( ' W N ' WY c N ' ( ' N ' ')( e : ( (2) (3) (5) (6) Let represent the multishot channel estimate matrix We now procee to the etection part of the algorithm after the formation of N)i using the matrix The initial soft ecision N)i outputs fhg j an har ecision outputs klg m of the etector is given by N/i f g npo % 4 N/i (7) k g ' i =BqRrla7fHb (8) f g N/is f g npo % s[t 45u N/i ' (9) i ' k g i =BqRrla7f g b (10) ' i where vwg u ' i an g are the soft an har ecisions after the first stage of the joint etector an x y :< is the iagonal elements in These computations are iterate z )]<0^ ^0^-){ { where is the maximum number of iterations i gy} ihs +-' i ' k gy} k gy} (11) i f gy}y~ is f gy} npo % st 4 ' i ' gy} (12) k gy} ~ i 0=BqRrla7f g }Y~ b (13) The structure of m ƒ :< ƒ is as shown P W P [ P P P P P P The har ecisions, k, which are mae at the en of the final stage, are fe back to the synchronization block an to the rest of the processing blocks in the receiver 3 Task Decomposition an Implementation The algorithm is implemente on a TI C6x DSP simulator [9], assuming a TI TS320C6701 (C67) floating point processor This processor is taken as an example of the current generation processor technology for our analysis The C67 is one of the recent DSPs from TI, which has a highperformance VLIW (Very Long Instruction Wor) architecture an has been propose for wireless base-stations It has a 32-bit architecture with 8 functional units, consisting of 2 multipliers, 4 ALs an 2 Loa/Store nits It has harware support for IEEE single an ouble precision floating point instructions an can prouce 2 ultiply an Accumulate s (AC) per cycle The algorithm was written in C The algorithm was written in a memory-efficient manner so as to avoi transposes an uses inplace computations The entire coe an ata fits in the internal memory of the DSP In this initial implementation, the L ecomposition was use to calculate (4) We use the TI C Compiler ver 30 to generate the assembly coe for the DSP The highest possible compiler optimizations recommene by TI [8] were use The optimizations perform software pipelining, loop unrolling an other program level optimizations to exploit (14)

4 Block I Block II Block III b Correlation atrices (Per Bit) R br [R] O(KN) Inverse R bb A H = R br [R] atrix Proucts A 0 H A 1 Block IV ultistage Detection (Per Winow) Data' Pilot R br [I] O(KN) Rbb O(K 2 ) R bb A H = R br [I] A 0 H A 0 A 1 H A 1 O(DK 2 e ) Data A H r O(KND) Figure 2 The Task Partition Graph for the Joint Estimation an Detection Algorithm the available fine-grain parallelism available in the VLIW architecture The structure an sparseness of the various matrices were also accounte for in the implementation 31 Task Decomposition The sequential implementation of the entire algorithm on the DSP oes not meet real-time constraints In fact, the achieve ata rates for just the etection block implementation, assuming a single stage iteration, shows the ata requirements falling short by a factor of 6 So, a task ecomposition of the algorithm is carrie out to fin the ata epenencies an to ientify all available sources of pipelining an parallelism A coarse graine pipeline-parallel task ecomposition of the joint estimation an etection algorithm is as shown in Figure 2 The input to the channel estimation block to the left is either the known pilot bits (b) an the receive pilot bits (pilot) or the etecte ata bits () an the receive ata bits, elaye by the time require for etection (ata ) The otte blocks (I-IV) represent pipeline operations whereas the blocks insie a otte block represent operations that can be one in > parallel?ba >?K? Equations 2,3 are shown in block I as both an can be compute in parallel These are outer prouct computations Also, both the real an imaginary parts of >?BA can be compute inepenently > Equation?K? 4 is represente in block II, where the inverse of is calculate by using a L Decomposition The block III shows the computation of equation 14 P I is not compute as it is a ˆI P b I Block III also inclues the computation of the ultiuser etection part (7), as it can be one in parallel with the above operations The iterative loop of the ultistage Detection (8-13) is shown as a single block IV The input ata bits are streaming in continuously in the receiver, which has to ensure that the receive ata stream Block Complexity Cycle count Correlation atrices " Inverse " Š NI Š ' Š NI Š N Š I' Š ' " Š IŒ \ per bit KN ultistage(1st stage) \O " per bit " 3367 Table 2 Cycle count an Complexity for ifferent blocks is being continuously processe so as to meet the real-time constraints However, the channel estimation can be upate less frequently so as to meet with the requirements of the etection (We neglect the effect of channel estimation on bit error rates for this purpose) The parts of multiuser etection which epen on the input ata are the calculation of I, as in (7), an the multistage etection loop (8-13) An orer complexity analysis was also one on the algorithm to fin the bottlenecks in each block 32 Simulations an Analysis An in-epth profiling of the various blocks was carrie out using the clock function in the C6x DSP The cycle count for the various blocks is as shown in Table 2 for 15 users an a etection winow of length 12 Assuming a 250 Hz processor, a ata rate requirement of 128 Kbps implies the available number of cycles per bit is 1953 for real-time etection The successive stages in the ultistage etector take significantly less time than the first stage Hence, let us assume the effective number of stages

5 { Optimization Cycle count A + B * A B max(13272,3367* ) (Pl A) B 3367* (Pl A) (Pp B) 3367 (Pl A) (PlPp B) 885 Table 3 Cycle count for ifferent optimization levels of blocks A ( I ) an B (block IV) Block III A H r 1 K A 0 H A 1 A 0 H A 0 A 1 H A 1 { { 9Ž { as where { The time require for block IV for all the stages can excee the time require to calculate I Also, the first an last K bits in each winow are ignore ue to ege effects an have to be recalculate The task partition graph at this level is unable to match the real time constraints as the present solution still requires R {[ ] ] cycles Therefore, we nee to search for more fine grain parallelism from the above task partition graph Table 3 shows the avantages of various levels of parallelism(pl) an pipelining(pp) Let A refer to the calculation of I in block III an B to block IV Let (A + B Sequential) be the present solution obtaine If A an B were pipeline (A B), the require Š computation becomes the maximum of A an B Next, Š I can be one for each user in parallel as each row of I correspons to a user, reucing the time to 885 cycles This puts the bottleneck to block B (Pl(A) B) Hence, block B is also unrolle into ifferent stages The first stage now has the most complexity, it becomes the new bottleneck, neeing 3367 cycles ((Pl A) (Pp B)) It has been shown [11] that each successive stages in B requires less computation than the previous stage Hence, fewer or less powerful processing elements nee to be use to these stages Each stage can also be split into multiple processing elements in a manner similar to A This reuces the cycles neee to 225, putting the bottleneck back to A (Pl(A) PlPp(B)) A an B after this step are shown in Figure 3 4 eeting Real Time Constraints The ata rates which can be met with ifferent levels of pipelining an parallelism are as shown in Figure 4 The figure shows the variation in the achieve ata rates with the number of users We assume that the effective {[ number of stages of the multistage etector is 3 ( ) As the level of pipelining an parallelism increases, we observe an increase in the ata rates The ata rates from (Parallel A)(Pipe Ž B) satisfies the requirements for lower number of users ( ) as it is limite by the complexity of the first stage which is a " b By having K processing elements for the first stage, the bottleneck shifts back to A ((Parallel Stage 1 Stage2 Stage3 Block IV Figure 3 Further Pipelining Parallelism in the ultistage Detection A)(Parallel + Pipe B)), which is of orer a b an hence, the ata rate achieve is inepenent of the number of users Juging from the time requirements for the block I an block II, we can upate block II once in 27 upates to block I The frequency of upates is etermine by the amount of error that can be tolerate in the etection If the upates are not frequent enough to keep up with the faing of the channel, the performance of the system will egrae in terms of the bit error rate ore frequent upates of once in 14 bits can be achieve by again further partitioning the matrix inverse into 2 separate tasks Here, the key iea is to use the amount of parallelism necessary to satisfy the bit error rate tolerance levels Alternate methos coul also be use for computing the inverse to reuce the complexity an make more upates feasible 5 Harware apping The above analysis with task partitioning is inepenent of the final harware mapping of the processing elements We assume that the processing elements in the critical part (block IV an I ) are equivalent to the functional units in a C67 for that particular operation because the C67 is use as the basis for our timing results The processing elements coul be mappe to ifferent architectures such as a single ASIC or multiple processors or a combination of a processor with an ASIC or FPGA The mapping coul also be one such as to have a DSP core with some coprocessor structures for critical parts Also, if there exists many processing elements in parallel where a single element ominates the computation, such as block III where the time taken by IŒ takes the same time as the other 3 matrix proucts taken together (see Table 2), all those processing elements coul be mappe to a single processor Thus, the loa between elements that have ile times coul be is-

6 3 x 105 Data Rates for Different Levels of Pipelining an Parallelism 7 Summary Data Rates (Parallel A) (Parallel+Pipe B) (Parallel A) (Pipe B) (Parallel A) B A B Sequential A + B Data Rate Requirement = 128 Kbps Number of sers Figure 4 Data Rates for various levels of Pipelining an Parallelism for A ( I ) an B (block IV) tribute to other processing elements The other assumptions inclue ieal communication overhea, no restriction on the number of processing elements available an the feasibility of esigning such an application specific system The number of processing elements are epenent on the number of users (K), which is variable Allocating elements for the maximum number of users may not lea to optimum utilization Hence, reconfigurable architectures supporting varying number of users shoul also be consiere 6 Future Work The ynamic range requirements for the joint estimation an etection algorithm are being analyse In the initial version, the algorithm is implemente in floating point ue to the possible loss in precision involve in L ecomposition From the analysis of the ifferencing multistage etector[11], we expect a precision range of less than 24 bits A fixe point implementation with a lower precision range coul benefit from the VLIW an SID type of fine graine parallelism shown in recent DSP an general purpose architectures Also, matrix oriente architectures [3], such as a vector processor with SID, showing 2 levels of parallelism coul be beneficial to these applications Another iea is to explore special systems to take avantage of the complex arithmetic ata involve, such as using reunant complex number systems (RCNS) for a ASIC architecture [2] We evelop acceleration techniques to implement key computationally intensive baseban algorithms in harware The joint multiuser channel estimation an etection algorithm is consiere for this purpose A etaile task partition of this algorithm along with its complexity analysis is shown with the help of a C6x DSP simulator The available parallelism an pipeline tasks in the algorithm are exploite to satisfy the real-time constraints We iscuss mapping issues of the task partitions in harware Such an application specific esign with multiple processing elements is more effective than a single processor in meeting the real time requirements of next generation communication systems References [1] F Aachi, Sawahashi, an H Sua Wieban DS- CDA for Next-Generation obile Communication Systems IEEE Communications agazine, 36(9):56 69, September 1998 [2] T Aoki, Y Ohi, an T Higuchi Reunant Complex Number Arithmetic For High-Spee Signal Processing IEEE Workshop on VLSI Signal Processing VIII, pages , October 1995 [3] J Corbal, Valero, an R Espasa Exploiting a New Level of DLP in ultimeia Applications In ICRO, International Symposium on icroarchitecture, November 1999 [4] E Dahlman, B Gumunson, Nilsson, an J Scol TS/IT-2000 Base on W-CDA IEEE Communications agazine, 36(9):70 80, September 1998 [5] eng, AAnnamalai, an V K Bhargava Recent avances in Cellular Wireless Communications IEEE Communications agazine, 37(9): , September 1999 [6] C Sengupta, J Cavallaro, an B Aazhang aximum Likelihoo ultipath Channel Parameter Estimation in CDA systems using antenna arrays In 9th IEEE International Symposium on Personal, Inoor, an obile Raio Communications(PIRC), pages , September 1998 [7] C Sengupta, S Das, J Cavallaro, an B Aazhang Efficient ultiuser Receivers for CDA Systems In IEEE Wireless Communications an Networking Conference, New Orleans, LA, pages , September 1999 [8] TI C6000 Compiler Optimization Tutorial ticom/sc/ocs/tools/sp/ccstutorhtm [9] TI TS320C6x Optimizing C Compiler, chapter 6 Texas Instruments, February 1998 [10] K Varanasi an B Aazhang ultistage etection in asynchronous Coe-Division ultiple -Access communications IEEE Transactions on Communications, 38(4): , Apr 1990 [11] G u an J Cavallaro Real-time Implementation of ultistage Algorithm for Next Generation Wieban CDA Systems In Avance Signal Processing Algorithms, Architectures, an Implementations I, SPIE, 1999