Cost of a Chip. Example: An IBM chip. Parallel Scan Output Compaction. Parallel Scan. Illinois Scan Architecture. Cost of Testing Semiconductor Chips

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1 Illinois Architecture Janak. Patel Center for Reliable and igh-performance Computing University of Illinois at Urbana-Champaign Cost of a Chip 3mm wafer will give ~1cm 2 chips Material Costs (wafer, copper etc) ~5% Fab amortization cost ($3B/fab) plus Fab operational cost ~25% Personnel cost ~2% Package Cost ~% Testing Cost ~4%!!! 25 Janak. Patel 2 Cost of Testing Semiconductor Chips Three main variable components Test Application Time When amortizing the cost of a tester over all chips, higher test time results in to higher actual cost Rule of thumb: 1 second per chip! Test Data Volume Low and medium cost testers have limited storage Tester Pins Cost of a tester is directly proportional to the number of pins it supports 3 Example: An IBM chip million gates (logic only, RAM not included) 25k Flip-Flops Full design, all FFs connected as shift register in 25, ffs out Test Vectors Test Application Time: x25k = 1.5 cycles at Mz scan speed it takes 1.5 Seconds! at 5Mz scan speed it takes 3.5 Seconds Tester memory required: x25k = 1.5 bits 4 Parallel Parallel Output Compaction -in Parallel Chains by 25 FFs -out -in Parallel Chains by 25 FFs output compactor scan-in pins! scan-out pins! A Combinational Compactor is a tree of XOR gates Reduces Test Vector Load time by a factor of! Channels on a Tester range from to 2 5 A Sequential Compactor is a Linear Feedback Shift Register with multiple parallel inputs XORed. Also called a Multiple Input Signature Analyzer (MISR) 6

2 Parallel - Summary Test Vector Compaction loading time can be reduced by dividing the single scan chain in to parallel scan chains Some Observations Output Compaction is well established Number of scan chains is limited by the availability of pins on a chip and tester scan channels Additional pins on an embedded core require more routing in the SOC Parallel has no impact on test data volume For example, all 4 ISCAS 85 and ISCAS89 (full scan) circuits, sizes of the test sets generated by MinTest (amzaoglu and Patel, ICCAD 1998, pp ) meets Lower bounds for 31 out of 4 ISCAS circuits. This shows that Compaction has already reached theoretical lower bounds in many instances So we must look for other solutions beyond vector compaction Test Vectors Lower Min Bound Test C C C S S S S BIST: STUMPS Architecture Limitations of Logic BIST P.. Bardell and W.. McAnney, Self-Testing of Multichip Logic Modules, Proc. Of Int. Test Conf., pp. 2-24, Nov (used by IBM for multi-chip-modules) L F S R Linear Feedback Shift Register Phase Shifter Chain Chain Chain Chain Under Test This has the same limitations as any other BIST based scheme M I S R Multiple Input Signature Register 9 BIST is excellent for Data Volume, But Lower Fault Coverage. Test Point insertion and/or additional logic in test generator is required to cover Random Resistant Faults Design Modification needed to permit any arbitrary test pattern Tri-State logic must be fully decoded No floating bus is permitted, since unknown values can corrupt the signature Switching activities of various modules, and hence the power, cannot be easily controlled Will almost always increase the tester time! Failure Diagnosis becomes extremely difficult Proposed New Method Illinois Architecture Illinois Architecture Applicable to full-scan embedded cores and fullscan stand-alone chips Addresses all issues raised earlier - Low test application time, low pin overhead, and low test data volume Does not have any of the limitations of the BIST No test point insertions and No design modifications! Undesirable test vectors can be filtered, e.g., Vectors that produce Tri-State Conflicts, Unknown value generation, or igh switching activity 11 in in Take a Serial 1. Divide it up into several chains keeping the same -in pin 2. Add a MISR to compact the outputs MISR out out 12

3 Cycles Circ uit Illinois Untestable Faults in Illinois -in pin Internal Chains Output Compactor scan in In the figure shown on left, all three scan chains will have identical test vectors Therefore, only applicable test vectors are and 111 for the AND gate Test vectors, and 1 cannot be applied due to Broadcast constraint This makes three faults on the AND gate Untestable In practice, how serious is this problem? ow many faults become untestable? Additional Untestable Faults Two Test Modes of Illinois Illinois puts constraints on inputs Cannot generate tests for some of the faults that are testable under normal scan The number of such Additional Untestable Faults is surprisingly small even for arbitrary partition! Experimental Data for Chain divided into 16 chains (arbitrary partition), with a single scan input Untestable Faults ILS-132 ILS-1585 ILS ILS-3841 ILS In 1. Broadcast Test Mode Chain 1 Chain 2 Chain n M I S R 1. Reduces Time by a factor of n 2. Reduces Data by a factor of n But may require many more vectors and may reduce fault-coverage! Out In 2. Serial Test Mode Chain 1 Chain 2 Chain n Mode 2 Used for covering the loss of fault-coverage in the Broadcast Mode enerates top-off vectors. M I S R Out Number of Test Vectors Number of Test Cycles Vectors fs132 ILS-132 scan vectors broadcast vectors fs1585 ILS-1585 fs35932 ILS fs3841 ILS-3841 fs38584 ILS Versions: fs = full scan, and ILS = Illinois, DIV16 1 2, 15, 15, 125,, 5, 5, 25, fs132 ILS-132 scan cycles broadcast cycles fs1585 ILS-1585 fs35932 ILS fs3841 ILS-3841 Versions: fs = full scan, and ILS = Illinois, DIV16 fs38584 ILS

4 45, 4, 35, Illinois Data Volume Test Data Broadcast Test Data Illinois internal scan chains Data Bits 3, 25, 2, 15, scan-in pin, 5, fs132 fs1585 fs35932 fs3841 fs38584 Versions: fs = full scan, and ILS = Illinois, DIV16 19 output compactor 2 external scan-in pins Illinois with multiple pins internal scan chains output compactor 21 Case Study at Texas Instruments Original : 15K logic gates, 93 scan flip-flops 9 Vectors, 94.25% stuck-at fault coverage Illinois Version DIV16 DIV24 DIV32 Broadcast Vectors 15, 14, 12, Broadcast Fault Coverage 94.8% 94.9% 93.8% Additional Untestable Faults Serial Vectors needed Serial Broadcast Fault Vectors Coverage needed % 6% 3% Data Volume Factor Similar reduction was also found in Transition Fault Data Frank su, Ken Butler and Janak Patel, A Case Study on the Implementation of the Illinois Architecture, Int. Test Conf. Oct IBM Data using Illinois (OPMISR+) Design Chip1 Chip2 Chip3* ate Count 1.M 2.1M 15k flip-flops 23k 31k 41k Test Time 13x 38x 21x Chip4* 1.2M 65k 8x 12x * These chips already had their scan divided by customer x Test Volume 2x 54x.scan fan-out, which is sometimes informally referred to as Illinois [ix]. In the Cadence ATP tools we refer to this as OPMISR+. Data and quote From: Test Compression Methods in Cadence Encounter Test Design Edition, Technology Application Note, December 23 Intel Data on Illinois From a Paper by D. Wu et. al. of Intel, published in 23 Int. Test Conf. The first test chip has 81 scan-in and 81 scan-out channels, we use Illinois with 4 scan-in and 81 scan-out. The results are quite surprising: both methods got the same test coverage. We have implemented Illinois scan into one of the microprocessors, but the silicon results will not be ready for the timing of this year s ITC

5 More Data on Illinois M ates, 25k flip-flops, test vectors Illinois in CAD Tools Cadence (formerly IBM) Illinois on their patented OPMISR is called OPMISR+ Syntest Illinois is called Virtual Synopsis ATP Tools understand and support Illinois Mentor raphics No Illinois! Proprietary tool called TestCompress Source: V. Chickermane, B. Fautz and B. Keller, Channel-Masking Synthesis for Efficient On-Chip Test Compression, Int. Test Conf., Illinois with multiple pins Large Industrial s have used Illinois with multiple pins IBM ASIC-4 chip (Design and Test, Sept. 22, pp. 65-2) 1.14 million gates, 46 pins, 269 internal chains Intel chips (Int. Test Conf., Sept. 23, pp ) ASIC-1, 4 pins, 81 internal chains ASIC-2, 4 pins, 96 internal chains Next generation microprocessor (no data given) All of the above scan-chain groupings are ad-hoc! Optimal rouping of Chains scan-in pins scan chains Objective: Minimize number of -In Pins without loss in fault coverage Compatibility among Chains Compatibility between two scan cells Two inputs (scan cells) are compatible if and only if no fault becomes untestable as a result of tying the two cells to a single input (Chen&upta, ITC 1995) Compatibility between two scan chains Two chains are compatible if and only if every pair of scan-cells that receive the same broadcast value are compatible (amzaoglu&patel, FTCS 1999) Determination of all pair wise compatibilities is computationally very expensive Resort to an inexpensive algorithm which gives a subset of all compatible pairs Incompatibilities from a Test Set A Partially Specified Test Vector, 2-bits long folded on to 5 chains Chain 1x xx1 x1x 11 xx11 1 x a No conflicting values found x x 1 b x 1 x c 1 1 d x x 1 1 e 1x xx1 x11x 11 xx11 Chains a and c are incompatible, so are chains c and d 1 x a x x 1 b x 1 1 x c 1 1 d x x 1 1 e 29 3

6 Example of Chain rouping Dual-mode Illinois iven Incompatible Pairs: AB, AD, A, BD, BE, BF, CE, CF, EF, E, E, F Construct a raph with Nodes=Chains and Edges=Incompatibility A A B B A B C D E F A B C D E F C D E F Single Pin Broadcast Mode roup Mode C D E F Perform raph Coloring Algorithm Conflict-free Chain rouping Some Results on Pin Illinois : Summary s132.1 s no. of Chains no. of Pins Factor A simple DFT technique, ideal for reducing test costs for large chips Significant reduction in test application time, test data and test pins without loss in fault coverage Even a dumb partition is very effective! For very large chips, 2 fold reduction is likely! s3841 s Things should be made as simple as possible, but not any simpler Albert Einstein More information on Illinois 1. I. amzaoglu and J.. Patel, Reducing test application time for full-scan embedded cores, Proc. 29th Int. Symp. On Fault-Tolerant Computing (FTCS-29), pp.26-26, June F. su, K. Butler and J.. Patel, A case study on the implementation of Illinois Architecture, Proc. Int. Test Conf. pp , October A.R. Pandey and J.. Patel, An incremental algorithm for test generation in Illinois Architecture based designs, Proc. Of Design Automation and Test in Europe (DATE), pp , March A.R. Pandey and J.. Patel, Reconfiguration techniques for reducing test time and test data volume in Illinois Architecture based designs, IEEE VLSI Test Symp. (VTS), pp. 9-15, April M.A. Shah and J.. Patel, Enhancement of the Illinois Architecture for Use with Multiple Inputs, IEEE Computer Society Annual Symposium on VLSI, pp , Feb

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