# Error Detection and Data Recovery Architecture for Systolic Motion Estimators

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3 accelerating the computation speed depends on a large PE array, especially in high-resolution devices with a large search range such as HDTV. The Mean Absolute Difference value of the current and reference pixel value are computed using the following equation. MAD = Xij Yij = q. m + r q. m + r (1) where r xij, q xij and r yij, q yij denote the corresponding RQ code X ij, Y ij of the current and reference values respectively and m denotes modulo operation. Importantly, X ij and Y ij represent the luminance pixel value of Cur_pixel and Ref_pixel, respectively. Based on the residue code, the definitions shown the following equations can be applied to facilitate generation of the RQ code and the TCG. A. Test Code Generator Figure 2, illustrates the structure of the TCG module in the proposed EDDR architecture. Notably, TCG design is based on the ability of the RQCG circuit to generate the corresponding test codes in order to detect errors and recover data. The specific PE i estimates the absolute difference between the Cur_pixel of the search area and the Ref_pixel of the current macroblock. Thus the Residue and Quotient value for an array size of N X N is given by equations (3) and (5). R T = X Y m (2) R T = [ r m + r m + r m + + r m] (3) Figure 2.Test Code Generator In the event of a fault, the RQ code from RQCG2 of the TCG is still equal to absolute difference value. However, R PEi and Q PEi are changed because an error e has occurred. R PEi = [ r m + r m + r m + + r m] + [ r m] Q PEi = [q + q + + q + q ] + B. Numerical Example A numerical example of the 16 pixels for a 4x4 macroblock in a specific PE i of a ME is described as follows. Fig. 5 presents an example of pixel values of the Cur_pixel and Ref_pixel. Based on (1), the MAD value of the 4x4 macroblock is, MAD = X Y = [ X Y + X Y X Y ] = = {(128-1) +(128-1)+ +(128-5)} Q T = (4) Q T = [q + q + + q ] + (5) Figure 3. Example of pixel values Notably the error signal e is expressed as, e = q e.m + r e ISSN: Page 264

4 IV. RESULTS AND DISCUSSION The proposed architecture was executed on Windows XP operating system at an operating frequency of 2.80GHz using ModelSim for functional verification and synthesized using Xilinx ISE simulator. Table 1 gives the synthesis report provides the device utilization which is analyzed in terms of percentage. The timing summary of the code execution is also obtained. The proposed architecture was simulated on XC3S100E device of Spartan3E family provided the following synthesis results. ====================================== Selected Device : 3s100evq100-5 Number of Slices: 651 out of % Number of Slice Flip Flops: 305 out of % Number of 4 input LUTs: 1160 out of % Number of IOs: 158 Number of bonded IOBs: 158 out of % IOB Flip Flops: 77 Number of MULT18X18SIOs: 4 out of 4 100% Number of GCLKs: 1 out of 24 4% Figure 4. Screenshot of the operation of the proposed system Table 1. Synthesis report The proposed architecture achieved a minimum period of 3.866ns and a maximum combinational path delay of ns.The following screenshots describes the operation of the proposed EDDR architecture. Results show that the pixel values are efficiently recovered by means of the data recovery module in the presence of a stuck at fault in the processing element. Figure 4 shows the output of the proposed system. The input pixel values and the final output are observed from the waveforms of the figure. Figure shows the operation the Data Recovery module. The CUT here is the second processing element which is given by the value of S. A stuck at fault model is used and the value of the second element is stuck at 64. The RQ code from the TCG module and the DRC module efficiently recover the original pixel which was initially 127. The error between the expected and the actual value is also obtained. Figure 5.Pixel values set to the PE array and the TCG module Figure 6. Comparison of error output with the recovered output ISSN: Page 265

5 V. CONCLUSION Our work presents an EDDR architecture for detecting the errors and recovering the data of PEs in a ME. Based on the RQ code, a RQCG-based TCG design is developed to generate the corresponding codes to detect errors and recover data. Experimental results obtained from ModelSim indicate that that the proposed EDDR architecture can effectively detect errors and recover data in PEs of a ME with reasonable area overhead and only a slight time penalty. Synthesis results show that the timing constraints and device utilization are minimum compared to error detection techniques available. [13] C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen, T. C. Wang, and L. G. Chen, Analysis and architecture design of variable block-size motion estimation for H.264/AVC, IEEE Trans. Circuits Syst. I, Reg.Papers, vol. 53, no. 3, pp , Mar [14] Y. W. Huang, B. Y. Hsieh, S. Y. Chien, S. Y. Ma, and L. G. Chen, Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC, IEEE Trans. Circuits Syst. Video Technol., vol. 16, no. 4, pp , Apr [15] L. Breveglieri, P. Maistri, and I. Koren, A note on error detection in an RSA architecture by means of residue codes, in Proc. IEEE Int. Symp. On-Line Testing, Jul. 2006, REFERENCES [1] Chang- Hsin Cheng, Yu Liu, and Chun-Lung Hsu, Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications IEEE transactions on very large scale integration (VLSI) systems, VOL. 20, NO. 4, April [2] Chun-Lung Hsu, Chang-Hsin Cheng, and Yu Liu, Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays, IEEE transactions on very large scale integration (vlsi) systems, vol. 18, no. 2, February [3] Y. S. Huang, C. J. Yang, and C. L. Hsu, C-testable motion estimation design for video coding systems, J. Electron. Sci. Technol., vol. 7, no. 4, pp , Dec [4] Che Wun Chiou, Chin-Cheng Chang,Chiou-Yng Lee, Ting- Wei Hou, and Jim-Min Lin, Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2m), IEEE transactions on computers, vol. 58, no. 6, June [5] W. Y Liu, J. Y. Huang, J. H. Hong, and S. K. Lu, Testable design and BIST techniques for systolic motion estimators in the transform domain, in Proc. IEEE Int. Conf. Circuits Syst., Apr. 2009, pp [6] S. Dhahri, A. Zitouni, H. Chaouch, and R. Tourki, Adaptive Motion Estimator Based on Variable Block Size Scheme, in World Academy of Science, Engineering and Technology Jan [7] Yu-Sheng Huang, Chen-Kai Chen and Chun-Lung Hsu, Efficient Built-In Self-Test for Video Coding Cores: A Case Study on Motion Estimation Computing Array - Dec [8] Y. S. Huang, C. K. Chen, and C. L. Hsu, Efficient built-in self-test for video coding cores: A case study on motion estimation computing array, in Proc. IEEE Asia Pacific Conf. Circuit Syst., Dec. 2008, pp [9] M. Y. Dong, S. H. Yang, and S. K. Lu, Design-fortestability techniques for motion estimation computing arrays, in Proc. Int. Conf. Commun., Circuits Syst., May 2008, pp [10] D. K. Park, H. M. Cho, S. B. Cho, and J. H. Lee, A fast motion estimation algorithm for SAD optimization in subpixel, in Proc. Int. Symp. Integr. Circuits, Sep. 2007, pp [11] S. Bayat-Sarmadi and M. A. Hasan, On concurrent detection of errors in polynomial basis multiplication, IEEE Trans. Vary Large Scale Integr. (VLSI) Systs., vol. 15, no. 4, pp , Apr [12] T. H. Wu, Y. L. Tsai, and S. J. Chang, An efficient designfor-testability scheme for motion estimation in H.264/AVC, in Proc. Int. Symp. VLSI Design, Autom. Test, Apr. 2007, pp ISSN: Page 266

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