Built-In Current Sensor for I DDQ Testing Embedded I DDQ Testing Architecture Based on IEEE

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1 SCOPE VLSI Technology and Computer Architecture Lab Research and teaching in the area of architectures and design techniques for VLSI integrated circuits and systems. ACTIVITIES PERSONEL Faculty: CK C. Kavousianos Y. Tsiatouhas Testing and esign for Testability Graduate Students: elay Testing V. Tenentes Test ata Compression A. Floros Scan Testing G. Sfikas Built-In Self Test (BIST) IQ Testing On-line Testing Memory Testing RF Testing Low Power esign PROJECTS Logic Low Power Techniques PYTHAGORAS-II (EPEAEK-II) Memory Low Power Techniques Activity co-funded by the European Low Power Testing Social Fund and National Resources. CMOS Circuit esign Logic Families UNIVERSITY OF IOANNINA Memory Circuit esign EPT. OF COMPUTER SCIENCE Analog Circuit esign 30/11/2007 Activities 1

2 Testing & esign for Testability Built-In Current Sensor for I Q Testing Embedded I Q Testing Architecture Based on IEEE CUT V sub-cut L sub-cut R T_ENB VGd V_Gnd L Test_sub sub-cut CUT_L S-Box V_Gnd R T_ENB Test_sub-CUT_R INJCT CMA BIAS COMP V REF Gnd Fail/Pass ESSCIRC-05 30/11/2007 Activities 2

3 Testing & esign for Testability On-Line Testing: Soft and Timing Error etection Concurrent Error etection and Correction Architectures Totally Self-Checking Checker esign Cycle i Cycle i+1 Cycle i+2 Cycle i+3 Register Valid ata Correct Arrival Cap_ Timing Fault Valid ata elayed Arrival Logic Stage S j 0 MUX 1 M Main Flip-Flop Flip-Flop Q Logic Stage S j+1 MUX Latch Memory State Error ata i ata i+1 MUX Latch Extended Memory State XOR Error_L Error_R j Capture Q ata i ata i ata i+1 Logic Logic Logic Logic 0 Q 0 1 Q 1 2 Q 2 3 Q 3 4 Q 4 Stage Stage Stage Stage I EX Error_R 0 Error_R 1 Error_R 2 Error_R 3 Error_R 4 Correct ata Failing stage I EX Erroneous ata Timing Error Erroneous stage Error Correct ata Correction Time in cycles Capture I ~EX I EX I EX Error Error FF elay Cap_ ICECS-06 Instruc ctions Re-execution with correct values at stage inputs I EX I 30/11/2007 Activities 3

4 Testing & esign for Testability Built-In Self Test (BIST): Test Pattern Generation BIST: Test Response Compaction Απόκριση εξόδων του υπό έλεγχο κυκλώματος Accumulator Constant k M k M k-1... M 3 M 2 M 1... TEST Arithmetic Unit Τμήμα B FF FF Είσοδος O Είσοδος Είσοδος κρατουμένου C out αθροιστής C in... TEST Register Τμήμα A k X FF Καταχωρητής (R) r k r k-1 r 2 r 1... FF 1 FF 2 FF 3 FF 4 ITC 30/11/2007 Activities 4

5 Testing & esign for Testability Test ata Compression Embedded Architectures for Test ata ecompression ATE_ATA ATE_SYNC ATE_ HSync Huffman FSM Code Index SE CSR Pure ata LFSR... Cell MUX Block Shifter Source Select MUX SYSTEM_ CSync Valid Code ecoding Controller Fail Fail Cluster/ Block Cluster Group Length SE Scan Chain IEEE-TCA-05 30/11/2007 Activities 5

6 Testing & esign for Testability Built-In Self Test (BIST) for RF VCO Circuits Built-In Test for RF LNA Circuits CIS-05 30/11/2007 Activities 6

7 Testing & esign for Testability Path elay Fault C-Testable Iterative Logic Arrays (ILAs) Path elay Fault Testing for Embedded IP Blocks sp 1 A B C IP Block Q 0 E sp 4 C F 6 8 G K MUX 0 L M IP Block Q 1 N R C 1 MUX 1 O 1 O 2 Y s Y s+1 Y s+g-2 Y s+g-1 Y s+g 1 Y + 2 Y + 1 Y + B s X s B s+1 X s+1 B s+g-2 X s+g-2 B s+g-1 X s+g-1 B s+g X s+g Z s Z s+1 Z s+g-2 Z s+g-1 Z s+g sp 5 ATE-99 sp 2 sp 3 30/11/2007 Activities 7

8 Low Power Circuit esign Low Power Technique for NORA Circuits State Assignment Algorithm for Activity Reduction in State Machines V V V M ecoding Unit B M α r N n Buffer O i A B C N p B Switch MB Gnd Gnd Gnd CLΚ Recycle Phase Recycle Phase Precharge Phase Evaluation Phase M Evaluation Phase Precharge Phase IEEE-TCAS-06 30/11/2007 Activities 8

9 Performance Oriented Circuit esign Logic Families esign Memory Circuit esign IN V pmos ifferential Network INB Precharge Evaluate Memory L=i-1 L=i L=i+1 NL V NR clk2 out1 clk4 out2 clk6 out3 OUTL M8 M6 M1 M2 M7 M11 OUTR n-network n-network n-network M3 M5 M4 clk1 clk3 clk5 ISCAS-06 M9 M10 Clk1 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 M12 M13 M14 M15 Clk2 Clk3 Clk4 Clk5 Clk6 30/11/2007 Activities 9 IOLTS-04