Operational Amplifiers Rail to Rail Input Stages Using Complementary Differential Pairs

Transcription

1 Oerational Amlifiers Rail to Rail Inut Stages Using Comlementary Differential Pairs Submitted to: Dr. Khoman Phang Submitted by: Ahmed Gharbiya Date: November 15, 2002

2 Abstract A rail to rail inut common mode range is an imortant requirement in oerational amlifiers for some alications. The most common method for imlementing full range oeration is by using a comlementary differential air. It is simly a comound structure that consists of NMOS and PMOS differential airs connected in arallel. The comound structure achieves rail to rail oeration; however, it roduces variations in the transconductance over the inut common mode range. The variations obstruct the design of an otimal oerational amlifier. This aer discusses sources and solutions for the transconductance variations. Several reorted aroaches to solve the roblem will be evaluated. They reduce the variations to 5-28% deending on the technique and method of imlementation used. This is a significant imrovement over 100% variations we get from comlementary differential air without utilizing any constant g m technique. i

3 Table of Contents Abstract... i Table of Contents... ii List of Figures... ii 1. Introduction Rail to Rail Oeration The Inut Stage Constant Transconductance Inut Stage Constant g m,n by means of tail current control Constant g m,n by means of voltage control Constant g m,n by means of asect ratio control Constant g m,n by alternative means Summary of constant g m,n methods Conclusion References List of Figures Figure 1: O Am in: (a) inverting configuration (b) non-inverting configuration... 2 Figure 2: Voltage follower... 3 Figure 3: NMOS differential air common mode inut range... 4 Figure 4: PMOS differential air common mode inut range... 4 Figure 5: Comlementary differential air common mode inut range... 5 Figure 6: NMOS differential air transconductance verses inut common mode... 5 Figure 7: PMOS differential air transconductance verses inut common mode... 6 Figure 8: Comlementary differential air transconductance verses inut common mode 6 Figure 9: Two stage o-am... 7 Figure 10: Selecting maximum g m Figure 11: DC level shifting ii

4 1. Introduction Oerational amlifiers are the back bone for many analog circuit designs. It is used in numerous alications such as amlifiers and filters. The oerational amlifier can be used in two basic configurations: inverting and non-inverting. These configurations lace different requirements on the common-mode inut range. The required range varies from almost zero to a full rail to rail. The differential amlifier is used as the inut stage for oerational amlifiers. The roblem is that it will behave as a differential amlifier only over a limited range of common-mode inut. Therefore, to make the oerational amlifier versatile, its inut stage should work for rail to rail common-mode inut range. The most common method to achieve this range is to use a comlementary differential amlifier at the inut stage. This method uses an n-tye and a -tye differential airs simultaneously. Although the method achieves a rail to rail common-mode inut oeration, it introduces subotimal oerational amlifiers. This is due to the non-constant transconductance (g m ) of the comlementary differential amlifier. However, there are methods that kee g m variations small over the entire inut common mode range. This aer gives an introduction to the concet of designing rail to rail constant gm oerational amlifiers using comlementary differential air inut stages. Section two starts with exlaining the reasons for the need of a rail to rail oeration. Section three introduces the comlementary differential air as a solution to achieve the desired range of oeration and identifies its drawbacks. Finally, section four examines ossible solutions to the subotimal design roblem introduced by the comlementary differential air and discusses imlementation methods reorted in academic aers. 2. Rail to Rail Oeration The oerational amlifier is a circuit building block that can be used in many alications. O-ams are used in conjunction with feedback networks to achieve several useful functions. However, there are only two main configurations: the inverting and non-inverting configurations. These configurations are shown in Figure 1. Each of the configurations will be analyzed next to determine its inut common mode requirements. 1

5 z 2 v i z v o (a) z 2 z 1 v i - + v o Figure 1: O Am in: (a) inverting configuration (b) non-inverting configuration (b) In the inverting configuration, the o-am will kee the two inut nodes at the same voltage. Since the ositive terminal is connected to ground, the non-inverting terminal will have the same voltage. Regardless of the changes of the inut voltage vi, both o-am terminals will be aroximately the same and equal ground otential. Therefore, the o-am needs almost zero common mode inut range. Similarly, in the non-inverting configuration, the o-am will kee the two inut nodes at the same voltage. Since the ositive terminal is connected to the inut voltage, it will have large variations. The inverting terminal must follow these variations. The worst case allowable variation (v i swing) is determined by the outut voltage and feedback network. Therefore, the common mode inut range is given by: V Z = (1) 1 CMR V o,max Z1 + Z 2 And if the o-am outut stage in caable of rail to rail oeration, V o,max will equal the suly voltage. A secial case of the non-inverting configuration is the voltage follower shown in Figure 2. This configuration will have the most constraint requirement for the common mode inut range. 2

6 v i - + v o Figure 2: Voltage follower Similar to the non-inverting configuration, the allowable variation (v i swing) is determined by the outut voltage and feedback network. But, since the feedback is unity, it is only determined by the outut voltage swing. If the o-am outut stage in caable of rail to rail oeration, then the common mode inut range should be rail to rail. It is clear that to design a versatile o-am that is useful for any configuration; its inut stage should have a rail to rail inut common mode range caability. Therefore, we will look into inut stages next. 3. The Inut Stage The inut stage of every o-am is a differential amlifier. In CMOS technology the differential amlifier can be realized using a PMOS or NMOS differential air. There are several tradeoffs that determine which differential air to use [1]. One criterion that is considered in making the choice is the common mode inut range. To analyze the common mode inut range of the NMOS differential inut stage, a simlified diagram will be used as shown in Figure 3. Several modifications are made to the simle differential air in actual imlementation such as active loads and cascodes, however this is sufficient for the urose of illustration. The range extends from the ositive suly to V gs,n +V Dsat,b above the negative suly. This minimum voltage is needed to kee the NMOS differential air and the tail current source in saturation. 3

7 v DD R R v CMR v 1 Mn Mn v 2 v GS, Mn Ib v Dsat, Ib v SS Figure 3: NMOS differential air common mode inut range A similar analysis can be carried out for the PMOS differential air shown in Figure 4. The range extends from V gs,n +V Dsat,b below the ositive suly to the negative suly. This minimum voltage is needed to kee the PMOS differential air and the tail current source in saturation. v DD Ib v Dsat, Ib v GS, M v 1 M M v 2 R R v CMR v SS Figure 4: PMOS differential air common mode inut range The simle differential air can not meet the rail to rail common mode inut requirement. A ossible solution to the roblem is to use both NMOS and PMOS differential airs simultaneously. The resulting comound differential air is called the comlementary differential air and is shown in Figure 5. 4

8 v DD Ib v Dsat, Ib v 1 M R R M v 2 v GS, M v CMR, n Mn Mn v CMR R R v CMR, v GS, Mn Ibn v Dsat, Ibn v SS diff air n diff air Comlementary diff air Figure 5: Comlementary differential air common mode inut range For low common mode inut, the PMOS differential air is in saturation and NMOS is off. For high common mode inut, the NMOS differential air is in saturation and PMOS is off. Therefore, the total effect is that the comlementary differential air is always working and the rail to rail common mode inut requirement is met. It should be noted that for common mode inut in the middle region both airs are working, this will have a significant effect on the erformance of the circuit. To understand the effect, we will investigate how the transconductance of each air and of the comlementary air changes with common mode inut signal. First the transconductance verses inut common mode of the NMOS air is shown in Figure 6. g m v CMR, n v SS v DD v CM Figure 6: NMOS differential air transconductance verses inut common mode 5

9 Similarly, the transconductance verses inut common mode of the PMOS air is shown in Figure 7. g m v CMR, v SS v DD v CM Figure 7: PMOS differential air transconductance verses inut common mode We see that the transconductance of each air is almost constant over its common mode range and dros to zero outside this range. Combining these two grahs gives the transconductance verses inut common mode of the comlementary air as shown in Figure 8. It is assumed here that both airs in the comlementary structure had been sized aroriately to obtain equal transconductance in their region of oeration. g m v CMR v SS v DD v CM Figure 8: Comlementary differential air transconductance verses inut common mode 6

10 The transconductance of the comlementary differential air (g m,n ) is almost constant for high or low common mode inut when only one of the airs is active. In the middle region, both airs are on and the effective transconductance is twice that of the other regions. The large variations in the transconductance will result in a subotimal o-am design with the comlementary differential air used as the inut stage. This can be understood by studying the design of a two stage o-am shown in Figure 9. Cc v 1 g m1 g m2 v 2 C L Figure 9: Two stage o-am Where C c is the comensation caacitor and C L is the load caacitor. The unity-gain bandwidth of the amlifier is aroximately given by: g m 1 ω t = (2) C c And the second ole is aroximately given by: g m 2 ω = 2 C (3) L Also, for stability reasons, we wish to satisfy the following condition: g m 1 2 α ω t α Cc ω > = (4) Where α is a multilication factor determined by the stability requirement. For examle, for a hase margin of 60º, α is about 2. In order to maintain a minimum unity-gain bandwidth, a lower limit is set on the value of g m1 as seen from (2), assuming C c is constant. Therefore, the worst case condition for ω t is when g m1 is at its minimum. On the other hand, to maintain a minimum distance between first and second oles, an uer limit is set on the value of g m1 as seen from (4), assuming C c and α are constants. Therefore, the worst case condition for ω 2 is when g m1 is at its maximum. There is a clear conflict of requirements between the two 7

11 conditions. In the comlementary differential air, g m,n is twice as large in the middle of the common mode rage as the sides. Therefore, when the minimum required g m,n is evaluated as required by ω t, it determines g m,n in the side regions. Then, α is set based on the middle g m,n which is the stability s worst case condition. Therefore, α is twice as large as it should be without g m,n variations. From (2), this requires g m2 to be twice as large; this translates into increased ower consumtion. Another less significant disadvantage of the varying transconductance is harmonic distortion. In o-ams, the distortion will be significantly reduced when the feedback network is added to the amlifier. Therefore, this effect is not usually an issue. The large variation of the comlementary differential air transconductance is not desirable. Its main disadvantage is the ower subotimal frequency comensation of the amlifier. Methods for reducing the transconductance variation are discussed next. 4. Constant Transconductance Inut Stage We need to formulate g m,n to exlore ossible methods for achieving a constant transconductance inut stage. Assuming all transistors are in the saturation region and using the square law models, the comlementary differential air transconductance is given by: or: g m, n = g m, n + gm, g W W m, n = µ n Cox I n + µ Cox I (5) L n L W W, µ (6) g m n = n Cox Veff, n + µ Cox Veff, L n L Investigating these formulas gives us suggestions on how to kee g m,n constant. From (5), we see that we can accomlish this by controlling the tail current or the asect ratio of either NMOS or PMOS differential air or both. From (6), we see that we can also obtain a constant g m,n by controlling the effective voltage of the transistor. 8

12 4.1. Constant g m,n by means of tail current control We will start with a condition to simlify the relationshi given by (5). If we choose: W W µ n Cox = µ Cox = K (7) L L then, (5) simlifies to: n ( I I ) g = K + m, n n (8) Therefore, to kee g m,n constant, we have to kee ( I ) I + constant. This can be done using translinear circuits to obtain a square root biasing scheme. The disadvantage of this design is its relative comlexity. Also, it is not very accurate since it uses the square law models of the MOS transistors and for today s dee submicron technology; there is a significant deviation from the ideal relation. The constant ( I ) I + method was used in [4] and 10% g m,n variations was n achieved. It was also used in [5] with 5% variations. Another method that uses tail current to maintain constant g m,n can be understood by utting another condition ( I I I ) g m n 2 =, therefore (8) becomes: n =, = K I (9) However, g m,n is only half the value given in (9) when only one differential air is oerating because I is half. Therefore, in the regions where one air is working, an increase in the tail current by a factor of 4 will kee g m,n constant. This can be imlemented by diverting the tail current of the non working air to the working air after multilying by a factor of 3. The multilication by 3 can be accomlished by using a three-times current mirror. The disadvantage of this technique is the limited accuracy due to ideal square law deendence (9). Also, the transition between the three regions is not well controlled and will cause variations in g m,n. The constant ( I ) method was used in [6] and 15% g m,n variations was achieved. It was also used in [7]and [8] with 15% variations in both. n 9

13 the following: 4.2. Constant g m,n by means of voltage control We can rewrite equation (6) using condition (7) to simlify the exression, we get g ( V + V V V ) 2 m, n = K gs, n sg, thn th (10) Therefore, to kee g m,n constant, we have to kee ( V ) V gs n sg,, + constant. This can be done by connecting a voltage source between the common source of the NMOS and the common source of the PMOS differential airs. This will kee both airs working for all common mode inut voltage. One method for imlementing the voltage source is by using two diode connected MOS transistors and sizing them aroriately. The disadvantage of this technique is that the behavior of the diode connected transistors is a function of the voltage across them. Therefore, g m,n still has some variations over the common mode inut range. The constant ( V ) V gs n sg,, + method was used in [9], 8% and 28% g m,n variations was achieved. The authors in this aer used two different methods to control g m,n by voltage adjustment, this accounts for the two values given here Constant g m,n by means of asect ratio control A closer look into (5) or (6), reveals the ossibility of controlling g m,n by controlling the asect ratio of one or both differential airs. One method for imlementing this is by using a second NMOS and a second PMOS differential airs in standby that are connected in arallel to the comlementary differential air. In the middle region of oeration, both airs in the comlementary differential air are oerating and the other two airs are off. To exlain how the circuit oerates in the other two regions, let s start with the inut common mode voltage in the middle region and going down towards Vss. When the voltage becomes low enough for the PMOS air to turn off, the other NMOS differential air will be activated. Effectively, doubling the asect ratio for low common mode inut, therefore, g m,n is constant. The same haens if the voltage increases towards Vdd, the second PMOS differential air will be activated and the effective asect ratio is doubled to kee g m,n constant. The disadvantage of this technique is that in the transition between the three regions results in a non-smooth 10

14 current transition. This causes relatively large variations in g m,n which results in a subotimal erformance. The asect ratio control method was used in [10] and 20% g m,n variations was achieved Constant g m,n by alternative means This section reorts two alternative methods for making g m,n constant. The first method utilizes a maximum selection circuit. The rincile of oeration is to allow only one air to oerate in the middle region. This can be done by keeing the differential air that has the larger tail current oerating and turn the other differential air off. The scheme assumes that the differential air with larger tail current is oerating roerly while the other air is going into (or just coming out of) triode region. The rincile is illustrated in Figure 10. The disadvantage of this design is its relative comlexity. This method was used in [11] and [12] which achieves 5% g m,n variations. g m g m,n off g m, on g m,n on g m, off g m,n v SS v DD v CM Figure 10: Selecting maximum g m Another alternative method uses DC level shifting. The rincile of oeration is to shift the transconductance characteristics curve of the NMOS differential air to the left or the transconductance characteristics curve of the PMOS differential air to the right such that the sum of g mn and g m is constant. This can be accomlished simly by alying a DC level shift to the NMOS air (or PMOS air) to make its turn on voltage higher (or lower). The rincile is illustrated in Figure 11 for NMOS shift. The 11

15 disadvantage of this method is its need for tuning. Because the characteristics will vary with rocess, voltage, and temerature, the otimal DC level will change. If the shift level is not tuned, large or small g m,n will aear around the transition region, therefore, instability might occur. This method was used in [13] and achieves 13% g m,n variations before tuning and 5% g m,n variations after tuning. g m g m,n v SS v DD v CM Figure 11: DC level shifting 4.5. Summary of constant g m,n methods This section rovides a summary of all the methods discussed to achieve constant transconductance for the comlementary differential inut stage. Princile Tail current control I: ( I + I ) = cons tan t n Tail current control II: ( I ) = cons tan t Voltage control: ( V + V ) cons tan t gs, n sg, = g m,n variation 10% [4] 5% [5] 15% [6], [7], and [8] 8% [9] 28% [9] Asect ratio control 20% [10] 12

16 Maximum selection circuit 5% [11] and [12] DC level shifting 13% [13] before tuning 5% [13] after tuning 5. Conclusion Oerational amlifiers inut stages utilizing a single differential air have a common mode inut range that extends to only one rail. This limits the alication where the o-am can be used. A rail to rail common mode inut range is a desirable characteristic for the inut stage to make it more versatile. This characteristic can be achieved using a comound differential air structure called the comlementary differential air. A drawback of this structure is that its transconductance varies by a factor of two over the range of oeration. This variation results in a subotimal frequency comensation of o-ams because it requires much more ower. Therefore, regulating the transconductance to kee it almost constant over the entire common mode range is essential. This aer rovides an overview of some techniques used to achieve near constant transconductance for the comlementary differential air oerating in strong inversion. Three systematic methods based on mathematical understanding of the transconductance behavior were described. They can be classified as: tail current control, voltage control, and asect ratio control. Two more alternative methods using maximum selection and DC level shifting were also described. The best erformers achieved 5% transconductance variation over the entire common mode range. However, they are also the more comlicated techniques. As the suly voltage shrinks for newer CMOS technologies, some of the techniques resented here will be obsolete. New methods have to be develoed to achieve rail to rail common mode oeration and caable of oerating in future CMOS technologies. 13

17 References [1] David A. Johns and Ken Martin, Analog Integrated Circuit Design, New York: Wiley, [2] Ron Hogervorst and Johan H. Huijsing, Design of Low-Voltage, Low-Power Oerational Amlifier Cells, Kluwer Academic ublishers, [3] Shouli Yan and Edgar Sanchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A Tutorial, IEICE Trans. Analog Integrated Circuits and Systems, vol. E00-A, no. 2 February [4] S. Sakurai and M. Ismail, Robust design of rail-to-rail CMOS oerational amlifiers for a low ower suly voltage, IEEE Journal of Solid-State Circuits, vol. 31, no. 2, , February [5] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, A low voltage CMOS o am with a rail-to-rail constant-gm inut stage and a class AB rail-to-rail outut stage, EEE Proc. ISCAS 1993, vol. 2, , May 1993 [6] R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R. F. Wassenaar, and J. H. Huijsing, CMOS low-voltage oerational amlifiers with constant-gm railto-rail inut stage, IEEE Proc. ISCAS 1992, [7] R. Hogervost, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, A comact ower-efficient 3-V CMOS rail-to-rail inut/outut oerational amlifier for VLSI cell libraries, IEEE Journal of Solid-State Circuits, vol. 29, no. 12, , December [8] J. H. Huijsing, R. Hogervorst, and K.-J. de Langen, Low-ower low-voltage VLSI oerational amlifier cells, IEEE Trans. Circuits and Systems-I, vol. 42. no. 11, , November [9] R. Hogervost, J. P. Tero, and J. H. Huijsing, Comact CMOS constant-gm rail-torail inut stage with gm-control by an electronic zener diode, IEEE Journal of Solid-State Circuits, vol. 31, no. 7, , July [10] R. Hogervorst, S. M. Safai, and J. H. Huijsing, A rogrammable 3-V CMOS railto-rail oam with gain boosting for driving heavy loads, IEEE Proc. ISCAS 1995,

18 [11] C. Hwang, A. Motamed, and M. Ismail, LV oam with rogrammable rail-to- rail constant-gm, IEEE Proc. ISCAS 1997, [12] C. Hwang, A. Motamed, and M. Ismail, Universal constant-gm inut-stage architecture for low-voltage o ams, IEEE Trans. Circuits and Systems-I, vol. 42. no. 11, , November [13] M. Wang, T. L. Mayhugh, Jr., S. H. K. Embabi, and E. Sánchez-Sinencio, Constant-gm rail-to-rail CMOS o-am inut stage with overlaed transition region, IEEE Journal of Solid-State Circuits, vol. 34, no. 2, , February