LTC1152 Rail-to-Rail Input Rail-to-Rail Output Zero-Drift Op Amp DESCRIPTIO

Transcription

1 LTC5 Rail-to-Rail Input Rail-to-Rail Output Zero-Drift Op Amp FEATRES Input Common-Mode Range Includes Both Rails Output Swings Rail to Rail Output Will Drive kω Load No External Components Required Input Offset Voltage: µv Max Input Offset Drift: nv/ C Max Minimum CMRR: 5dB Supply Current:.mA Max Shutdown Pin Drops Supply Current to 5µA Max Output Configurable to Drive Any Capacitive Load Operates from.7v to V Total Supply Voltage O S Rail-to-Rail Amplifiers and Buffers High Resolution Data Acquisition Systems Supply Current Sensing in Either Rail Low Supply Voltage Transducer Amplifiers High Accuracy Instrumentation Single Negative Supply Operation DESCRIPTIO The LTC 5 is a high performance, low power zero-drift op amp featuring an input stage that common modes to both power supply rails and an output stage that provides rail-to-rail swing, even into heavy loads. The wide input common-mode range is achieved with a high frequency on-board charge pump. This technique eliminates the crossover distortion and limited CMRR imposed by competing technologies. The LTC5 is a C-Load TM of amp, enabling it to drive any capacitive load. The LTC5 shares the excellent DC performance specs of LTC s other zero-drift amplifiers. Typical offset voltage is µv and typical offset drift is nv/ C. CMRR and PSRR are db and db and open-loop gain is db. Input noise voltage is µv P-P from.hz to Hz. Gain-bandwidth product is.7mhz and slew rate is.5v/µs, all with supply current of.ma max over temperature. The LTC5 also includes a shutdown feature which drops supply current to µa and puts the output stage in a high impedance state. The LTC5 is available in 8-pin PDIP and 8-pin SO packages and uses the standard op amp pinout, allowing it to be a plug-in replacement for many standard op amps., LTC and LT are registered trademarks of Linear Technology Corporation. C-Load is trademark of Linear Technology Corporation. TYPICAL O Rail-to-Rail Buffer Input and Output Waveforms 5V 7 5V V OT V/DIV IN LTC5 OT V 5V V IN V/DIV 5 TA V 5 TA

2 LTC5 ABSOLTE AXI RATI GS W W W Total Supply Voltage (V to V )... V Input Voltage... V.V to V.V Output Short-Circuit Duration (Pin )... Indefinite Operating Temperature Range LTC5C... C to 7 C LTC5I... C to 85 C Storage Temperature Range... 5 C to 5 C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR SHDN IN IN V TOP VIEW N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO 8 CP 7 V OT 5 COMP T JMAX = C, θ JA = C/ W (N8) T JMAX = C, θ JA = C/ W (S8) W ATIO ORDER PART NMBER LTC5CN8 LTC5CS8 LTC5IN8 LTC5IS8 5 5I S8 PART MARKING Consult factory for Military grade parts. ELECTRICAL CHARA CTERISTICS V S = 5V, T A = operating temperature range, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage T A = 5 C (Note ) ± ± µv V OS Average Input Offset Drift (Note ) ± ± nv/ C Long-Term Offset Drift ±5 nv/ Mo I B Input Bias Current T A = 5 C (Note ) ± ± pa ± pa I OS Input Offset Current T A = 5 C (Note ) ± ± pa ±5 pa e n Input Noise Voltage (Note ) R S = Ω,.Hz to Hz µv P-P R S = Ω,.Hz to Hz.5 µv P-P i n Input Noise Current f = Hz. fa/ Hz CMRR Common-Mode Rejection Ratio V CM = V to 5V 5 db PSRR Power Supply Rejection Ratio V S = V to V db 5 db A VOL Large-Signal Voltage Gain R L = k, V OT =.5V to.5v db V OT Maximum Output Voltage Swing (Note ) R L = k, V S = Single 5V.. V R L = k, V S = ±.5V ±.. V R L = k, V S = ±.5V ±.9 V SR Slew Rate R L = k, C L = 5pF, V S = ±.5V.5 V/µs GBW Gain-Bandwidth Product R L = k, C L = 5pF, V S = ±.5V.7 MHz I S Supply Current No Load.. ma Shutdown = V 5 µa I OSD Output Leakage Current Shutdown = V ± ± na V CP Charge Pump Output Voltage I CP = 7. V V IL Shutdown Pin Input Low Voltage.5 V V IH Shutdown Pin Input High Voltage V I IN Shutdown Pin Input Current V SHDN = V 5 µa f CP Internal Charge Pump T A = 5 C.7 MHz f SMPL Internal Sampling T A = 5 C. khz

3 LTC5 ELECTRICAL CHARA CTERISTICS V S = V, T A = operating temperature range, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Input Offset Voltage T A = 5 C (Note ) ± ± µv V OS Average Input Offset Drift (Note ) ± ± nv/ C I B Input Bias Current T A = 5 C (Note ) ±5 ± pa ± pa I OS Input Offset Current T A = 5 C (Note ) ± ± pa ±5 pa e n Input Noise Voltage (Note ) R S = Ω,.Hz to Hz µv P-P R S = Ω,.Hz to Hz.75 µv P-P i n Input Noise Current f = Hz. fa/ Hz CMRR Common-Mode Rejection Ratio V CM = V to V db A VOL Large-Signal Voltage Gain R L = k, V OT =.5V to.5v db V OT Maximum Output Voltage Swing (Note ) R L = k, V S = Single V..5 V R L = k, V S = ±.5V ±.8 V SR Slew Rate R L = k, C L = 5pF, V S = ±.5V. V/µs GBW Gain-Bandwidth Product R L = k, C L = 5pF, V S = ±.5V.5 MHz I S Supply Current No Load.8.5 ma Shutdown = V 5 µa I OSD Output Leakage Current Shutdown = V ± na V CP Charge Pump Output Voltage I CP =.5 V V IL Shutdown Pin Input Low Voltage. V V IH Shutdown Pin Input High Voltage. V I IN Shutdown Pin Input Current V SHDN = V µa f CP Internal Charge Pump T A = 5 C. MHz f SMPL Internal Sampling T A = 5 C. khz The denotes specifications which apply over the full operating temperature range. Note : These parameters are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels during automated testing. Note : At T C these parameters are guaranteed by design and not tested. Note :.Hz to Hz noise is specified DC coupled in a -sec window;.hz to Hz noise is specified in a -sec window with an RC highpass filter at.hz. Contact LTC factory for sample tested or % tested noise parts. Note : All output swing measurements are taken with the load resistor connected from output to ground. For single supply tests, only the positive swing is specified (negative swing will be V due to the pull-down effect of the load resistor). For dual supply operation, both positive and negative swing are specified.

4 LTC5 TYPICAL PERFORMANCE CHARACTERISTICS W COMMON-MODE RANGE LIMIT (V) 8 Common-Mode Range vs Supply Voltage SPPLY CRRENT (ma) Supply Current vs Supply Voltage. T A = 5 C.5..5 POWER SPPLY CRRENT (ma) Supply Current vs Temperature. V S = 5V POWER SPPLY VOLTAGE (±V). 8 TOTAL SPPLY VOLTAGE (V) TEMPERATRE ( C) 75 5 G 5 G 5 G OTPT SWING (±V) Output Swing vs Load Resistance T A = 5 C V S = SINGLE 5V 5 V S = SINGLE V V S = ±.5V V S = ±.5V OTPT SHORT-CIRCIT CRRENT (ma) Output Short-Circuit Current vs Supply Voltage T A = 5 C SORCE SINK OPEN-LOOP OTPT RESISTANCE (Ω) 5 5 Open-Loop Output Resistance vs Supply Voltage T A = 5 C LOAD RESISTANCE (kω) 8 TOTAL SPPLY VOLTAGE (V) 8 TOTAL SPPLY VOLTAGE (V) 5 G 5 G5 5 G CHARGE PMP VOLTAGE, V CP V (V) Charge Pump Voltage vs Supply Voltage T A = 5 C CHARGE PMP VOLTAGE, VCP V (V) Charge Pump Voltage vs Load Current T A = 5 C V S = 5V INPT BIAS CRRENT (±pa) Input Bias Current vs Temperature V S = 5V 8 TOTAL SPPLY VOLTAGE (V) 8 LOAD CRRENT (µa) TEMPERATRE ( C) 5 G7 5 G8 5 G9

5 LTC5 TYPICAL PERFORMANCE CHARACTERISTICS W VOLTAGE GAIN (db) 7 5 Gain and Phase Shift vs PHASE GAIN T A = 5 C V S = ±.5V PIN 5 = NC 8 PHASE SHIFT (DEG) COMMON-MODE REJECTION RATIO (db) Common-Mode Rejection Ratio vs T A = 5 C V S = ±.5V POWER SPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs 8 T A = 5 C 7 5 PSRR PSRR k k k M M FREQENCY (Hz) 5 G. FREQENCY (khz) 5 G k k k M FREQENCY (Hz) 5 G VOLTAGE GAIN (db) 7 5 Gain and Phase Shift vs PHASE GAIN T A = 5 C V S = ±.5V C COMP = pf 8 PHASE SHIFT (DEG) VOLTAGE NOISE (nv/ Hz) Voltage Noise vs (µv).hz to Hz Input Noise k k k M M FREQENCY (Hz) k k FREQENCY (Hz) 8 TIME (SEC) 5 G 5 G5 5 G8 VOLTAGE GAIN (db) 5. Gain and Phase Shift vs T A = 5 C V S = ±.5V C COMP =.µf PHASE GAIN. FREQENCY (khz) 5 G 8 8 PHASE SHIFT (DEG) Small-Signal Transient Response V S = ±.5V A V = 5 G Large-Signal Transient Response V S = ±.5V A V = 5 G7 5

6 LTC5 O S I FOR W ATIO Rail-to-Rail Operation The LTC5 is a rail-to-rail input common-mode range, rail-to-rail output swing op amp. Most CMOS op amps, including the entire LTC zero-drift amplifier line, and even a few bipolar op amps, can and do, claim rail-to-rail output swing. One obvious use for such a device is to provide a unity-gain buffer for V to 5V signals running from a single 5V power supply. This is not possible with the vast majority of so-called rail-to-rail op amps; although the output can swing to both rails, the negative input (which is connected to the output) will exceed the common-mode input range of the device at some point (generally about.5v below the positive supply), opening the feedback loop and causing unpredictable and sometimes bizarre behavior. The LTC5 is an exception to this rule. It features both rail-to-rail output swing and rail-to-rail input commonmode range (CMR); the input CMR actually extends beyond either rail by about.v. This allows unity-gain buffer circuits to operate with any input signal within the power supply rails; input signal swing is limited only by the output stage swing into the load. Additionally, signals occurring at either rail (power supply current sensing, for example) can be amplified without any special circuitry. Internal Charge Pump The LTC5 achieves its rail-to-rail input CMR by using a charge pump to generate an internal voltage approximately V higher than V. The input stages of the op amp are run from this higher voltage, making signals at V appear to be V below the front end s power supply (Figure ). The charge pump is contained entirely within the LTC5; no external components are required. About µv P-P of residual charge pump switching noise will be present on the output of the LTC5. This feedthrough is at.7mhz, higher than the gain-bandwidth of the LTC5, and will generally not cause any problems. Very sensitive applications can reduce this feedthrough by connecting a capacitor from the CP pin (pin 8) to V (pin 7); a.µf capacitor will reduce charge pump feedthrough to negligible levels. The LTC5 includes an internal diode from pin 8 to pin 7 to prevent external parasitic capacitance from lengthening start-up CP (PIN 8).µF* IN IN V CC V *OPTIONAL EXTERNAL CAPACITOR TO REDCE CHARGE PMP FEEDTHROGH INPT INTERNAL CHARGE PMP V CC (PIN 7) OT Figure. LTC5 Internal Block Diagram OTPT RAIL TO RAIL 5 F time. This diode can stand short-term peak currents of about 5mA, allowing it to quickly charge external capacitance to ground or V. Large capacitors (>µf) should not be connected between pin 8 and ground or V to prevent excessive diode current from flowing at start-up. The LTC5 can withstand continuous short circuits between pin 8 and V ; however, short circuiting pin 8 to ground or V will cause large amounts of current to flow through the diode, destroying the LTC5. Don t do it. Output Drive The LTC5 features an enhanced output stage that can sink and source ma with a single 5V supply while maintaining rail-to-rail output swing under most loading conditions. The output stage can be modeled as a perfect rail-to-rail voltage source with a resistor in series with it; this open-loop output resistance limits the output swing by creating a resistor divider with the output load. The output resistance drops as total power supply voltage increases, as shown in the typical performance curves. It is typically Ω with a single 5V supply, allowing a.v output swing into a k resistor with a single 5V supply. V CC (PIN 7) LTC5 OTPT DRIVER R OT OT (PIN ) Ω AT 5V SPPLY R LOAD 5 F Figure. LTC5 Output Resistance Model

7 LTC5 O S Compensation/Bandwidth Limiting The LTC5 is unity-gain stable with capacitive loads up to pf. Larger capacitive loads can be driven by externally compensating the LTC5. Adding pf between COMP (pin 5) and OT (pin ) allows capacitive loading of up to µf;.µf between pins 5 and allows the LTC5 to drive infinite capacitive load (Figure ). 8 7 V LTC5 V 5 N8* I FOR W C C *OPTIONAL DIODES TO PREVENT LATCH-P WITH C C > µf OTPT N8* ATIO 5 F Figure. Output Compensation Connection Large compensation capacitors can also be used to limit the bandwidth of the LTC5. With.µF from pin 5 to pin, the LTC5 s gain-bandwidth product is reduced from 7kHz to around Hz. Note that compensation capacitors greater than µf can cause latch-up under severe output fault conditions; this can be prevented by clamping pin 5 to each supply with standard signal diodes, as shown in Figure. Shutdown The LTC5 includes a shutdown pin (pin ). When this pin is at V, the LTC5 operates normally. An internal µa pull-up keeps the pin high if it is left floating. When pin is pulled low, the part enters shutdown mode; supply current drops to µa, all internal clocking stops and the output enters a high impedance state. During shutdown the voltage at the CP pin (pin 8) will drop to.5v below V. When pin is brought high again, about µs will elapse before the charge pump regains full voltage. During this time the LTC5 will operate normally, but the input CMR may not include V. Pin is compatible with CMOS logic running from the same supply as the LTC5. Additionally, the input trip levels allow ground referenced CMOS logic signals to interface directly to pin when the LTC5 is running from ±5V or ±V supplies. The internal µa pull-up also allows pin to interface with open-collector/ open-drain devices or discrete transistors. The high impedance output in shutdown allows several LTC5s to be connected together as a MX, with their outputs tied in parallel and the active channel selected by using the shutdown pins. Deselected (shutdown) channels will go to high impedance at the outputs, preventing them from fighting with the active channel. This works best when the individual LTC5s are connected in noninverting feedback configurations to prevent the feedback resistors from passing signals through deselected channels. See the Typical Applications section for a circuit example. Zero-Drift Operation The LTC5 is a zero-drift op amp. Like other LTC zerodrift op amps, it features virtually error-free DC performance, very little drift over time and temperature, and very low noise at low frequencies. The internal nulling clock runs at about.khz (the charge pump frequency of.7mhz divided by 8) and is synchronized to the internal charge pump to prevent beat frequencies from appearing at the output. The self-nulling circuit constantly corrects the input offset voltage, keeping it typically below ±µv over the entire input common-mode range. This has the added benefit of providing exceptional CMRR and PSRR at low frequenciesfar better than competing railto-rail op amps. Because it uses a sampling front end, the LTC5 will exhibit aliasing behavior and clock noise at frequencies near the internal.khz sampling frequency. The LTC5 includes an internal anti-aliasing circuit to keep these error terms to a minimum. As a rule, alias frequencies will be down by (8dB A CLG ) in most standard amplifier configurations, where A CLG is the closed-loop gain of the LTC5 circuit. Clock noise is also dependent on closedloop gain; it will generally consist of spikes of about µv in amplitude, input referred. In general, these error terms are too small to affect most applications. For a more detailed explanation of zero-drift amplifier behavior, see the LTC5/LTC5 data sheet. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7

8 LTC5 O S I FOR W ATIO High Gain Amplifier with ±.5V Supplies.5V Ω k High Precision Three-Input MX.k k IN 7 LTC5.µF OT A V = k = 8dB IN A V = LTC5 SEL 5V.Ω.5V High-Side Power Supply Current Sensing CHANGE SENSE RESISTOR TO CHANGE SENSITIVITY.µF 5 TA TO MEASRED CIRCIT Ω IN A V = k LTC5 OT SEL Ω k LTC5 k k k k LT97 OT V/mA LOAD CRRENT IN MEASRED CIRCIT.µF IN A V = LTC5 SEL SELECT INPTS ARE CMOS LOGIC COMPATIBLE. SELECT ONLY ONE CHANNEL AT ONCE! 5 TA GND GND 5 TA5 PACKAGE DESCRIPTION N8 Package 8-Lead Plastic DIP Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic SOIC.* (.) MAX.89.97* (.8 5.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.5mm)..55 ±.5* (.77 ±.8) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.5mm)..8. ( ).5.57* (.8.988)..5 ( ).9.5 (.9.8) ( ).5 (.5) TYP.5 ±.5 (. ±.8). ±. (.5 ±.5).5.5 (..5). ±.5 (. ±.7).5 (.75) MIN.8 ±. (.57 ±.7).5 (.8) MIN N (..5).. (.5.58) TYP.5.9 (..75)..9 (.55.8).5 (.7) BSC.. (..5) SO8 9 8 LT/GP 95 K PRINTED IN SA Linear Technology Corporation McCarthy Blvd., Milpitas, CA (8) -9 FAX: (8) -57 TELEX: LINEAR TECHNOLOGY CORPORATION 995