LP62S Series. Document Title. 16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM. Revision History. Rev. No. History Issue Date Remark
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1 Preliminary 16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM Document Title 16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 20, 2014 Preliminary PRELIMINARY (November, 2014, Version 0.0) AMIC Technology, Corp.
2 Preliminary 16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM Features Operating voltage: 2.7V to 3.6V Access times: 55/70 ns (max.) Current: Very low power version: Operating: 50mA (max.) Standby: 20μA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using three-state output Data retention voltage: 2.0V (min.) Available in 48-pin TSOP (I) and 48-ball CSP (6 x 8 mm) packages All Pb-free (Lead-free) products are RoHS2.0 compliant The TSOP (I) package configurable as 1M x 16 or 2M x 8 Static RAM - BYTE fixed to HIGH, LB controlled I/O0 - I/O7, HB controlled I/O8 - I/O15 - BYTE fixed to LOW, I/O15 used as address pin, while I/O8 - I/O14 pins not used General Description The LP62S is a low operating current 16,777,216- bit static random access memory organized as 1,048,576 words by 16 bits and operates on low power voltage from 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family Operating Temperature VCC Range Speed Data Retention (ICCDR, Typ.) Power Dissipation Standby (ISB1, Typ.) Operating (ICC2, Typ.) LP62S C ~ +70 C 2.7V~3.6V 55ns / 70ns 0.3μA 0.5μA 4mA LP62S161024(I) -40 C ~ +85 C 2.7V~3.6V 55ns / 70ns 0.3μA 0.5μA 4mA 1. Typical values are measured at VCC = 3.0V, TA = 25 C and not 100% tested. 2. Data retention current VCC = 2.0V. Package Type 48 TSOP (I) 48-ball CSP 48 TSOP (I) 48-ball CSP PRELIMINARY (November, 2014, Version 0.0) 2 AMIC Technology, Corp.
3 Pin Configurations TSOP (I) A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CS2 NC HB LB A18 A17 A7 A6 A5 A4 A3 A2 A LP62S161024V 48 A16 47 BYTE 46 GND 45 I/O15/A20 44 I/O7 43 I/O14 42 I/O6 41 I/O13 40 I/O5 39 I/O12 38 I/O4 37 VCC 36 I/O11 35 I/O3 34 I/O10 33 I/O2 32 I/O I/O1 I/O8 29 I/O0 28 OE 27 GND 26 CS A0 CSP (Chip Size Package) 48-pin Top View A LB OE A0 A1 A2 CS2 B I/O8 HB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC Note: The BYTE pin in the 48-pin TSOP (I) package must be tied HIGH to use the device as a 1M x 16 SRAM. The 48-pin TSOP (I) package can also be used as a 2M x 8 SRAM by tied the BYTE signal LOW. In the 2M x 8 configuration, pin 45 is A20, while HB, LB and I/O8 to I/O14 pins are not used (NC). PRELIMINARY (November, 2014, Version 0.0) 3 AMIC Technology, Corp.
4 Block Diagram A0 VCC GND A18 DECODER 1M X 16 / 2M X 8 MEMORY ARRAY A19 I/O0 I/O8 INPUT DATA CIRCUIT COLUMN I/O INPUT DATA CIRCUIT I/O7 I/O15/A20 LB CS1 CS2 LB HB OE WE BYTE CONTROL CIRCUIT PRELIMINARY (November, 2014, Version 0.0) 4 AMIC Technology, Corp.
5 Pin Descriptions Symbol Description Symbol Description A0 A19 Address Inputs (Word Mode) HB Higher Byte Enable Input (I/O8 - I/O15) A0 A20 Address Inputs (Byte Mode) BYTE Byte Enable CS 1, Chip Enable CS2 OE Output Enable I/O1 - I/O16 Data Input/Output VCC Power Supply WE Write Enable Input GND Ground LB Byte Enable Input (I/O0 - I/O7) NC No Connection Recommended DC Operating Conditions (TA = 0 C to +70 C or -40 C to +85 C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GND Ground V VIH Input High Voltage VCC V VIL Input Low Voltage V CL Output Load pf TTL Output Load PRELIMINARY (November, 2014, Version 0.0) 5 AMIC Technology, Corp.
6 Absolute Maximum Ratings* VCC to GND V to +4.0V IN, IN/OUT Volt to GND V to VCC + 0.5V Operating Temperature, Topr C to +70 C or -40 C to +85 C Storage Temperature, Tstg C to +125 C Power Dissipation, PT W *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = 0 C to +70 C or -40 C to +85 C, VCC = 2.7V to 3.6V, GND = 0V) Symbol Parameter LP62S /70LL(I) Unit Conditions Min. Max. ILI Input Leakage Current - 1 μa VIN = GND to VCC ILO Output Leakage Current - 1 μa CS 1 = VIH or CS2 = VIL or LB = HB = VIH VI/O = GND to VCC ICC Active Power Supply Current - 5 ma CS 1 = VIL, CS2 = VIH, LB = VIL or HB = VIL, II/O = 0mA ICC1-50 ma Dynamic Operating Current ICC2-8 ma ISB - 1 ma Standby Current ISB1-20 μa Min. Cycle, Duty = 100%, CS 1 = VIL, CS2 = VIH, LB = VIL or HB = VIL II/O = 0mA CS 1 0.2V, CS2 VCC-0.2V, LB 0.2V or HB 0.2V f = 1MHz, II/O = 0mA CS 1 = VIH or CS2 = VIL or LB = HB = VIH CS 1 VCC - 0.2V or CS2 0.2V or LB = HB VCC-0.2V VIN VCC-0.2V or VIN 0.2V VOL Output Low Voltage V IOL = 2.1 ma VOH Output High Voltage V IOH = -1.0 ma PRELIMINARY (November, 2014, Version 0.0) 6 AMIC Technology, Corp.
7 Truth Table CS 1 CS2 OE WE LB HB I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current H X X X X X High - Z High - Z ISB1, ISB X L X X X X High - Z High - Z ISB1, ISB X X X X H H High - Z High - Z ISB1, ISB L L Read Read ICC1, ICC2, ICC L H L H L H Read High - Z ICC1, ICC2, ICC H L High - Z Read ICC1, ICC2, ICC L L Write Write ICC1, ICC2, ICC L H X L L H Write High - Z ICC1, ICC2, ICC H L High - Z Write ICC1, ICC2, ICC L H H H L X High - Z High - Z ICC1, ICC2, ICC L H H H X L High - Z High - Z ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25 C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pf VIN = 0V CI/O* Input/Output Capacitance 8 pf VI/O = 0V * These parameters are sampled and not 100% tested. PRELIMINARY (November, 2014, Version 0.0) 7 AMIC Technology, Corp.
8 AC Characteristics (TA = 0 C to +70 C or -40 C to +85 C, VCC = 2.7V to 3.6V) Symbol Parameter LP62S LL(I) LP62S LL(I) Unit Max. Min. Min. Max. Read Cycle trc Read Cycle Time ns taa Address Access Time ns tacs1, tacs2 Chip Enable Access Time ns tbe Byte Enable Access Time ns toe Output Enable to Output Valid ns tclz1, tclz2 Chip Enable to Output in Low Z ns tblz Byte Enable to Output in Low Z ns tolz Output Enable to Output in Low Z ns tchz1, tchz2 Chip Disable to Output in High Z ns tbhz Byte Disable to Output in High Z ns tohz Output Disable to Output in High Z ns toh Output Hold from Address Change ns Write Cycle twc Write Cycle Time ns tcw1, tcw2 Chip Enable to End of Write ns tbw Byte Enable to End of Write ns tas Address Setup Time ns taw Address Valid to End of Write ns twp Write Pulse Width ns twr Write Recovery Time ns twhz Write to Output in High Z ns tdw Data to Write Time Overlap ns tdh Data Hold from Write Time ns tow Output Active from End of Write ns Note: tclz1, tclz2, tblz, tolz, tchz1, tchz2, tbhz and tohz and twhz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (November, 2014, Version 0.0) 8 AMIC Technology, Corp.
9 Timing Waveforms (1, 2, 4) Read Cycle 1 trc Address taa toh toh DOUT (1, 2, 3) Read Cycle 2 trc Address taa CS1 CS2 tclz1, tclz2 tacs1, tacs2 tchz1, tchz2 HB, LB tbe tblz 5 tbhz 5 OE tolz 5 toe 5 tohz DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CS 1 = VIL, or CS2 = VIH, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CS 1 and (HB and, or LB ) transition low or CS2 transition High. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (November, 2014, Version 0.0) 9 AMIC Technology, Corp.
10 Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) twc Address taw twr 3 tcw CS1 CS2 tbw HB, LB tas 1 twp 2 WE tdw tdh DATA IN twhz 4 tow DATA OUT PRELIMINARY (November, 2014, Version 0.0) 10 AMIC Technology, Corp.
11 Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) twc Address tas 1 taw tcw 1, tcw 2 twr 3 CS1 CS2 tbw HB, LB twp WE tdw tdh DATA IN twhz 4 tow DATA OUT PRELIMINARY (November, 2014, Version 0.0) 11 AMIC Technology, Corp.
12 Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) twc Address taw tcw1, tcw2 CS1 tas 1 tbw 2 twr 3 CS2 HB, LB twp WE tdw tdh DATA IN twhz 4 tow DATA OUT Notes: 1. tas is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (twp, tbw) of a low CS 1, WE and ( HB and, or LB ) or a high CS2. 3. twr is measured from the earliest of CS 1 or WE or ( HB and, or LB ) going high or CS2 going Low to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (November, 2014, Version 0.0) 12 AMIC Technology, Corp.
13 AC Test Conditions Input Pulse Levels 0.4V to 2.4V Input Rise And Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 TTL TTL CL 30pF CL 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tclz1, tclz2, tbhz, tblz, tolz, tchz1, tchz2, tohz, twhz, and tow Data Retention Characteristics (TA = 0 C to +70 C or -40 C to 85 C) Symbol Parameter Min. Max. Unit Conditions VDR VCC for Data Retention V ICCDR Data Retention Current - 6* μa CS 1 VCC - 0.2V or CS2 0.2V or LB = HB VCC-0.2V VCC = 2.0V, CS 1 VCC - 0.2V or CS2 0.2V or LB = HB VCC-0.2V VIN VCC-0.2V or VIN 0.2V tcdr Chip Disable to Data Retention Time 0 - ns tr Operation Recovery Time trc - ns tvr VCC Rising Time from Data Retention Voltage to Operating Voltage 5 - ms See Retention Waveform * LP62S /70LL(I) ICCDR: max. 1μA at TA = 25 C (3μA at TA = 0 C to +40 C ) PRELIMINARY (November, 2014, Version 0.0) 13 AMIC Technology, Corp.
14 Low VCC Data Retention Waveform (1) ( CS1 Controlled) DATA RETENTION MODE VCC 2.7V 2.7V tcdr VDR 2.0V tr tvr CS1 VIH VIH CS1 VDR - 0.2V Low VCC Data Retention Waveform (2) (CS2 Controlled) DATA RETENTION MODE VCC 2.7V 2.7V tcdr VDR 2.0V tr tvr CS2 VIL VIL CS2 0.2V Ordering Information Part No. Access Time(ns) Operating Current Max.(mA) Standby Current Max.(uA) Package LP62S161024V-55LL(I)F LP62S161024U-55LL(I)F LP62S161024V-70LL(I)F LP62S161024U-70LL(I)F L Pb-Free TSOP (I) 48L Pb-Free CSP 48L Pb-Free TSOP (I) 48L Pb-Free CSP PRELIMINARY (November, 2014, Version 0.0) 14 AMIC Technology, Corp.
15 Package Information TSOP 48L (Type I) Outline Dimensions unit: inches/mm D D E A2 A S b A1 D c e y Detail "A" 0.25 L θ Detail "A" Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A Symbol A b c D D E e BASIC 0.50 BASIC L S Typ Typ. y θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. PRELIMINARY (November, 2014, Version 0.0) 15 AMIC Technology, Corp.
16 Package Information 48LD CSP (6 x 8 mm) Outline Dimensions (48TFBGA) unit: mm TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (48X) A B C D E F G H A B C D E F G H SIDE VIEW C SEATING PLANE A1 A E E1 e B e D1 A D 0.10 C 0.20(4X) Note: Symbol Dimensions in mm MIN. NOM. MAX. A A D E D E e b THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD) PRELIMINARY (November, 2014, Version 0.0) 16 AMIC Technology, Corp.
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