MAPware-7000 Ladder Logic Guide

Transcription

1 APware-7000 Ladder Logic Guide aple ystems Inc th treet, uite 120 Everett, A Phone: (425) maple@maplesystems.com eb: aple ystems Inc. All rights reserved.

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3 i APware-7000 Ladder Logic Guide Table of Contents Logic lock Instructions... 1 Overview... 1 Ladder Instruction Table... 1 Input/Output Instructions... 1 Data Transfer Instructions... 2 ath Instructions... 4 Compare Instructions... 5 Logic Instructions... 6 Conversion Instructions... 8 Timer Instructions... 9 Counter Instructions Program Control Instructions Functions Instructions pecial Instructions Instructions Defined Instruction 1- NO Contact Instruction 2- NC Contact Instruction 3- Output Instruction 4- Rising Edge (Transitional Contact) Instruction 5- Falling Edge (Transitional Contact) Instruction 6- Forced Coil Instruction 7- Inverter Instruction 8- Inverter Coil Instruction 9- Positive Pulse Contact Instruction 10- Negative Pulse Contact Instruction 11- Positive Pulse Coil Instruction 12- Negative Pulse Coil Instruction 13- OV ord Instruction 14- OV Dord... 28

4 APware-7000 Ladder Logic Guide ii Instruction 15- Invert Transfer Instruction 16- Table Initialize Instruction 17- Table lock Transfer Instruction 18- Table Invert Transfer Instruction 19- Data Exchange Instruction 20- ultiplexer Instruction 21- Demultiplexer Instruction 22- Addition Instruction 23- Double-ord Addition Instruction 24- ubtraction Instruction 25- Double-ord ubtraction Instruction 26- ultiplication Instruction 27- Unsigned ultiplication Instruction 28- Division Instruction 29- Unsigned Division Instruction 30- Division Double ord Instruction 31- Addition with carry Instruction 32- ubtraction with carry Instruction 33- Increment Instruction 34- Decrement Instruction 35- Greater Than Instruction 36- Double ord Greater Than Instruction 37- Unsigned ord Greater Than Instruction 38- Greater Than or Equal To Instruction 39- Double ord Greater Than or Equal To Instruction 40- Unsigned Greater Than or Equal To Instruction 41- Equal To Instruction 42- Double ord Equal To Instruction 43- Unsigned Equal To Instruction 44- Not Equal To Instruction 45- Double ord Not Equal To Instruction 46- Unsigned Not Equal To... 82

5 iii APware-7000 Ladder Logic Guide Instruction 47- Less Than Instruction 48- Double ord Less Than Instruction 49- Unsigned Less Than Instruction 50- Less Than or Equal To Instruction 51- Double ord Less Than or Equal To Instruction 52- Unsigned Less Than or Equal To Instruction 53- Logic AND Instruction 54- Logic OR Instruction 55- Logic Exclusive OR Instruction 56- Logic hift 1 bit shift right Instruction 57- Logic hift 1 bit shift left Instruction 58- Logic hift n bits shift right Instruction 59- Logic hift n bits shift left Instruction 60- hift Register Instruction 61- i-directional hift Register Instruction 62-1 bit rotate right Instruction 63-1 bit rotate left Instruction 64- n bit rotate right Instruction 65- n bit rotate left Instruction 66- Hex to ACII Conversion Instruction 67- ACII to Hex Conversion Instruction 68- Absolute Value Instruction 69-2 s Complement Instruction 70- Double-word 2 s Complement Instruction 71-7 egment Decode Instruction 72- ACII Conversion Instruction 73- inary Conversion Instruction 74- CD Conversion Instruction 75- ON Timer Instruction 76- OFF Timer Instruction 78- Counter Instruction 79- Up/Down Counter

6 APware-7000 Ladder Logic Guide iv Instruction 80- ubroutine Call Instruction 81- ubroutine Return Instruction 82- FOR (For next loop) Instruction 83- NET (For-Next loop) Instruction 84- aster Control et/reset Instruction 85- Jump Control et/reset Instruction 86- Enable Interrupt Instruction 87- Disable Interrupt Instruction 88- atchdog timer reset Instruction 89- tep equence Initialize Instruction 90- tep equence Input Instruction 91- tep equence Output Instruction 92- oving Average Instruction 93- Digital Filter Instruction 94- PID Instruction 95- PID Instruction 96- Upper Limit Instruction 97- Lower Limit Instruction 98- aximum Value Instruction 99- inimum Value Instruction 100- Average Value Instruction 101 Function Generator Instruction 102- Device et Instruction 103- Device Reset Instruction 104- Register et Instruction 105- Register Reset Instruction 106- et Carry Instruction 107- Reset Carry Instruction 108- Encode Instruction 109- Decode Instruction 110- it Count Instruction 111- Flip Flop

7 v APware-7000 Ladder Logic Guide Instruction 112- Direct I/O Instruction 112- Direct I/O Instruction 113- et Calendar Instruction 114- Calendar Operation

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9 1 APware-7000 Ladder Logic Guide Logic lock Instructions Overview Logic lock instructions are the commands and instructions used to create the ladder logic routines supported by the HC7000 eries. Over 100 instructions are available making the HC as flexible as using a PLC. The ladder logic can read/write to any internal memory of the HC including memory addresses allocated for use by the I/O expansion modules. Note that although the ladder logic programs cannot directly access any memory of a PLC that is attached to the HC s serial ports, you can still exchange data between the PLC and your ladder logic programs by using the Copy HI lock to HI/PLC lock and Copy HI/PLC lock to HI lock task commands (for more information on using these and other tasks, please read Chapter 8 Task anagement). The previous chapter discusses how to create ladder logic routines as well as the various types of Logic locks supported. This chapter focuses on the ladder logic instructions available and how they work. Ladder Instruction Table The table below is a brief listing of all ladder logic instructions available. The instructions are split into groups according to similarity of purpose. Later in this chapter, each instruction will be dealt with in more detail. Input/Output Instructions These are input instructions (must be located to the left side of the rung) and output instructions (must be located to the right side of the rung). Instruction Name ymbol Description Execution Time (μec) NO Contact {input} Normally Open Contact. 1 μsec NC Contact {input} Output {output} Rising Edge {input} Normally Closed Contact. Output Contact or Relay Coil. Turns ON output for 1 scan when input changes from Off On. 1 μsec 1.1 μsec 1 μsec

10 APware-7000 Ladder Logic Guide 2 Instruction Name ymbol Description Execution Time (μec) Falling Edge {input} Turns ON output for 1 scan when input changes from On Off. 1 μsec Inverter {input} Invert Coil {output} Positive Pulse Contact {input} Negative Pulse Contact {input} Positive Pulse Coil {output} Negative Pulse Coil {output} Inverts the input state. tores the inverse state of the input going into coil. Turns ON output for 1 scan when input is ON and Operand A changes from Off On. Turns ON output for 1 scan when input is ON and Operand A changes from On Off. Turns ON Operand A for 1 scan when input changes from Off On. Turns ON Operand A for 1 scan when input changes from On Off. 0.8 μsec 1.1 μsec 1.3 μsec 1.3 μsec 1.3 μsec 1.3 μsec Data Transfer Instructions These are instructions which can be used to move data from one (or more) memory location(s) to another memory location(s). Instruction Name ymbol Description Execution Time (μec) OV ord OV Dord Transfer data from one 16-bit register to another. Transfer data from one 32-bit register to another. 1.9 μsec 2.2 μsec Invert Transfer Transfers an inverted version of the data in one register (ex. 1 0, and 0 1) to 1.9 μsec

11 3 APware-7000 Ladder Logic Guide another. Instruction Name ymbol Description Execution Time (μec) Table Initialize Transfers a constant value or a value in the specified source register (Operand A) to a series of consecutive registers (1 to 1024) beginning with the target register. (Operand ) 1.8 μsec to μsec Table lock Transfer Table Invert Transfer Data Exchange ultiplexer Demultiplexer Transfers a series of consecutive registers (1 to 1024) beginning with the source register (Operand A) to a series of consecutive registers beginning with the target register. (Operand ) Transfers a series of consecutive registers (1 to 1024) beginning with the source register (Operand A) to a series of consecutive registers beginning with the target register (Operand ). However, the values transferred are inverted. (ex. 1 0, and 0 1). The data values in the two specified registers are exchanged or swapped. A particular register in a range of registers (Operand A) is read and copied to a target register (Operand C). hich register read/copied is determined by the value in Operand register. A register (Operand A) is read and copied to a particular target register selected from a range of registers (determined by Operand C). hich target register selected is determined by the value in Operand register. 1.7 μsec to μsec 1.6 μsec to μsec 2 μsec 2.7 μsec 2.5 μsec

12 APware-7000 Ladder Logic Guide 4 ath Instructions These are instructions which can be used to initialize data or move data from one memory location to another. Instruction Name ymbol Description Execution Time (μec) Addition Adds two signed registers and puts the sum in a third register. 2.9 μsec to 3.2 μsec ubtraction ultiplication Division ord Division Unsigned Dord/ord Addition with Carry ubtraction with Carry ubtracts the value in Operand from the value in Operand A and puts the result in a third register, Operand C. ultiplies the values in two registers and puts the result in a third register. Divides the value in Operand A by the value in Operand and puts the result in a third register, Operand C. Note: the quotient is stored in C and the remainder is stored in C+1. Divides the value in Operand A (32-bit register) by the value in Operand (16- bit register) and puts the result in a 16-bit register, Operand C. Note: the quotient is stored in C and the remainder is stored in C+1. Adds two registers, along with the carry bit (0) and puts the sum in a third register. If the carry bit was set during this operation, the carry flag is turned ON. Use this instruction when adding two unsigned numbers or 32-bit registers. ubtracts the value in Operand, along with the carry bit (0) from the value in Operand A and puts the result in Operand C register. If the carry bit was set during this operation, the carry flag is turned ON. Use this instruction when subtracting two unsigned numbers or 32- bit registers. 1.6 μsec to 3.5 μsec 2.0 μsec to 2.8 μsec 8.8 μsec to 9.5 μsec 9.0 μsec 3.5 μsec 3.5 μsec

13 5 APware-7000 Ladder Logic Guide Instruction Name ymbol Description Execution Time (μec) Increment henever the input to this instruction is ON, the data in the selected register is incremented by μsec Decrement henever the input to this instruction is ON, the data in the selected register is decremented by μsec Log(10) NA Calculates Common Log (base 10) of value in Operand A and puts result in Operand C register. Ex. log 10 A=C Log(e) NA Calculates the Natural Log value (base e) in Operand A and puts the result in Operand C register. Ex. log e A=C Antilog(10) NA Calculates the common antilogarithm (base 10) of value in Operand A and puts the result in Operand C register. TD TD TD Ex. if log 10 x=y, then antilog 10 y=x. Antilog(e) NA Calculates the Natural antilogarithm (base e) in Operand A and puts the result in Operand C register. TD Ex. if log e x=y, then antilog e y=x. Compare Instructions These are instructions which compare the values between two registers and, depending upon the result (i.e. equal, greater than, less than, etc) turns ON the output. Instruction Name ymbol Description Execution Time (μec) Greater than If data in Operand A is greater than data in Operand, the output is turned ON. 2.2 μsec to 2.4 μsec Greater than or equal If data in Operand A is greater than or equal to the data in Operand, the output is turned ON. 2.2 μsec to 2.4 μsec

14 APware-7000 Ladder Logic Guide 6 Instruction Name ymbol Description Execution Time (μec) Equal If data in Operand A is equal to the data in Operand, the output is turned ON. 2.3 μsec to 2.4 μsec Not Equal Less than Less than or equal If data in Operand A is not equal to the data in Operand, the output is turned ON. If data in Operand A is less than data in Operand, the output is turned ON. If data in Operand A is less than or equal to the data in Operand, the output is turned ON. 2.2 μsec to 2.3 μsec 2.1 μsec to 2.4 μsec 2.1 μsec to 2.4 μsec Logic Instructions These are instructions which perform logic operations (i.e. AND, OR, OR, etc.) on the selected data registers. Instruction Name ymbol Description Execution Time (μec) AND The data in Operand A is logic ANDed to the data in Operand and output to Operand C. 2.7 μsec OR Exclusive OR The data in Operand A is logic ORed to the data in Operand and output to Operand C. The data in Operand A is logic ORed to the data in Operand and output to Operand C. 2.7 μsec 2.7 μsec 1 bit shift right The data in the selected register is shifted 1 bit to the right (L direction). The least significant bit is stored in the carry flag. (0) 1 bit shift left The data in the selected register is shifted 1 bit to the left ( direction). The most significant bit is stored in the carry flag. (0) 2 μsec 2 μsec

15 7 APware-7000 Ladder Logic Guide Instruction Name ymbol Description Execution Time (μec) N bits shift right The data in Operand A is shifted n bits (1-16) to the right (L direction) and stored in Operand and the carry bit. Note: the carry bit (0) is the location of the 1 st rightmost bit after the shift. 2.5 μsec N bits shift left The data in Operand A is shifted n bits (1-16) to the left ( direction) and stored in Operand and the carry bit. Note: the carry bit (0) is the location of the 1 st leftmost bit after the shift. 2.5 μsec hift Register i-directional shift register hile the enable input is ON, this instruction shifts the data of the bit table, size n (1 to 64) starting with A, 1 bit to the left (upper address direction) when the shift input is ON. hile the enable input (E) is ON, this instruction shifts the data of the bit table, size n (1 to 64) starting with A, 1 bit when the shift input () is ON. The shift direction is determined by the state of the direction input (L) μsec to 36.6 μsec 21.7 μsec to 42.2 μsec 1 bit rotate right The data in the selected register is shifted 1 bit to the right (L direction). The least significant bit is moved to the most significant bit. 1 bit rotate left The data in the selected register is shifted 1 bit to the left ( direction). The most significant bit is moved to the least significant bit. N bits rotate right The data in Operand A is shifted n bits (1 to 16) to the right (L direction) and stored in Operand. N bits rotate left The data in Operand A is shifted n bits (1 to 16) to the left ( direction) and stored in Operand. 2.1 μsec 2.1 μsec 2.4 μsec 2.4 μsec

16 APware-7000 Ladder Logic Guide 8 Conversion Instructions These are instructions which convert the data from one type of format (ex. CD, Hex, ACII) to another format. Instruction Name ymbol Description Execution Time (μec) Hex to ACII ACII to Hex Absolute Value The hexadecimal data in a series of consecutive registers (1 to 32) beginning with Operand A is converted into ACII characters and stored in consecutive registers starting with Operand. The ACII data in a series of consecutive registers (1 to 64) beginning with Operand A is converted into hexadecimal characters and stored in consecutive registers starting with Operand. Computes the absolute value in Operand A and stores in Operand. 2 s Complement Computes the 2 s complement value in Operand A and stores in Operand. Double-word 2 s Complement Computes the 2 s complement value in Operand A (and register A+1) and stores in Operand (and register +1). 7 egment Decode Converts the lower 4 data bits of Operand A into 7 segment code, and stores it in Operand. The 7 segment code is normally used for a numeric display LED. ACII conversion Converts alphanumeric characters (up to 16) into ACII codes, and stores them in the designated register table, starting with Operand. inary conversion Converts 4 digits of CD data in Operand A into binary and stores in Operand. CD conversion Converts the binary data in Operand A into CD data and stores in Operand. Integer to Float NA Converts integer (16 or 32 bit) value in Operand A into a floating point value (32 bit) and stores in Operand. Float to Integer NA Converts a floating point value (32 bit) in Operand A into an integer (16 or 32 bit) 5.8 μsec to 87.1 μsec 6.5 μsec to 64.9 μsec 1.3 μsec 1.1 μsec 1.6 μsec 1.3 μsec 1.7 μsec to 5.8 μsec 1.7 μsec 11.4 μsec TD TD

17 9 APware-7000 Ladder Logic Guide Timer Instructions These are instructions which run timers. value and stores in Operand. Instruction Name ymbol Description Execution Time (μec) ON timer OFF timer ingle hot timer hile the input is ON, timer updates according to the time specified (hundredths of second) in Operand A. Time elapsed is recorded in Operand. hen time is reached, output is turned ON and the update of Operand stops. hen input is OFF, value in Operand is reset back to 0. hile the input is OFF, timer updates according to the time specified (hundredths of second) in Operand A. Time elapsed is recorded in Operand. hen time is reached, output is turned OFF and the update of Operand stops. hen input is ON, value in Operand is reset back to 0. hen the input is pulsed ON, timer updates according to the time specified (hundredths of second) in Operand A. Time elapsed is recorded in Operand. Output is ON during this time until time is reached, then Output is turned OFF and remains OFF until input is pulsed again. Value in Operand is reset back to 0 if 1) value equals preset value in Operand A and then input is turned OFF or 2) input is turned OFF, value reaches preset value, input is pulsed ON. 6.7 μsec 6.8 μsec 7.1 μsec

18 APware-7000 Ladder Logic Guide 10 Counter Instructions These are instructions which run counters. Instruction Name ymbol Description Execution Time (μec) Counter hen the input is ON, timer will update according to the time specified (hundredths of second) in Operand A. Time elapsed is recorded in Operand. hen time reached, output is turned ON. 4.4 μsec Up/Down Counter hile enable input (E) is ON, this counter increments/decrements the number of cycles (once per scan) while count input (C) is ON, and puts the result in target Counter address. The counter counts up if input (U) is ON, counts down if input (U) is OFF. 1.3 μsec Program Control Instructions These are instructions which do program control. Instruction Name ymbol Description Execution Time (μec) ubroutine call Calls the target subroutine. 2.7 μsec ubroutine return Returns to the calling logic block. FOR NET aster Control et aster Control Reset Jump Control et Jump Control Reset hen input is ON, the segment of logic between the FOR and NET statements. executes repeatedly during a scan until the count is reached. The aster Control et (C) and aster Control Reset (CR) instructions turn. OFF the power rail between these instructions when C input is OFF. Jumps from Jump Control et (JC) to the Jump Control Reset (JCR) when input to JC is ON. 3.3 μsec 2.3 μsec 1.8 μsec Enable Interrupt Allows execution of interrupt programs. 5.2 μsec

19 11 APware-7000 Ladder Logic Guide Instruction Name ymbol Description Execution Time (μec) Disable Interrupt Prevents execution of interrupt programs. atchdog Timer Reset tep equence initialize tep equence input tep equence output The built-in watchdog timer resets the HC7000 if timeout exceeds 200 msec. This instruction extends that time by up to an additional 100 msec. This function initializes a step sequencer. It clears n bit registers starting with Operand A, then sets Operand A. If input to this function is ON and Operand A is ON, then turns the output ON. hen input is ON, this functions resets all bit registers of the step sequencer, then sets Operand A. 1.0 μsec 3.5 μsec to 86.8 μsec 1.2 μsec 1.9 μsec Functions Instructions These are instructions which perform complex functions. Instruction Name ymbol Description Execution Time (μec) oving Average Digital Filter Calculates the average value of last n scan values of A, and stores the result in C. Filters the value of A by filter constant specified by, and stores the result in C. 5.7 to 45.5 μsec 28.4 μsec PID 1,4 Performs PID control (pre-derivative real PID algorithm): Process value (PV): A et value (V): A+1 PID parameters: anipulation value (V): C μsec

20 APware-7000 Ladder Logic Guide 12 Instruction Name ymbol Description Execution Time (μec) Upper Limit Lower Limit aximum Value inimum Value Average Value Function Generator Data Log Upload Compares the current value in a register A with a set value in. If the current value A is less than, then A is stored in result C. If A is greater than, is stored into C. Compares the current value in a register A with a set value in. If the current value A is greater than, then A is stored in result C. If A is less than, is stored into C. earches for the maximum value in a table of registers (of size n), beginning with register A, then stores the maximum value into register. earches for the minimum value in a table of registers (of size n), beginning with register A, then stores the minimum value into register. Computes the mean average value of a table of registers (of size n), beginning with register A, then stores the result into register. Finds f(x) for given x=a, and stores result in C. The function f(x) is defined by parameters stored in a table of registers (of size 2n), beginning with register. Uploads data logger from attached U 2.3 μsec 2.1 μsec 4.0 to 64.6 μsec 3.9 to 61.1 μsec 12.5 to 39.7 μsec 5.2 to 68.8 μsec pecial Instructions These are instructions which include data processing functions, I/O instructions, and RA. Instruction Name ymbol Description Execution Time (μec) Device et ets target coil address to ON. 1.1 μsec Device Reset Clears target coil address to OFF. 1.1 μsec

21 13 APware-7000 Ladder Logic Guide Instruction Name ymbol Description Execution Time (μec) Register et ets target register address to 0xFFFF. 1.1 μsec Register Reset Clears target register address to μsec et Carry ets the carry flag ON. 1.0 μsec Reset Carry Clears the carry flag to OFF. 1.0 μsec Encode Decode it Count Flip-Flop Direct I/O et Calendar Calendar Operation Finds the uppermost ON bit position in the table of coils (of size 2n) beginning with coil A, and stores in coil. ets to ON a target coil address indicated by the lower n bits of address A, and resets all other coil addresses in the table of coils (of size 2n) beginning with coil. Counts the number of ON bits of A and stores result in. ets to ON target address A when input () is ON, and clears to OFF target address A when input (R) is ON. Note: input (R) has top priority. Performs immediate block transfer of n registers starting with A. ets six data registers starting with A into the clock/calendar. Calculates the difference between the present date and time compared to the past date and time stored in six registers starting with A. tores result in six registers starting with. 4.7 to 99.7 μsec 4.3 to 46.8 μsec 4.2 μsec 1.6 μsec 5.6 μsec μsec μsec

22 APware-7000 Ladder Logic Guide 14 Instructions Defined Instruction 1- NO Contact pace Requirement: 1 line x 1 column Location Requirement: Left rail, iddle NO (normally open) contact of device A. hen the input is ON and the device A is ON, the output is turned ON. Input Operation Output OFF Regardless of the state of device A OFF ON hen device A is OFF. OFF hen device A is ON. ON Coil or it Register Constant Index Name T. C. A Device Timing Diagram: Coil 0022 comes on when the devices 0000 and 0001 are both ON.

23 15 APware-7000 Ladder Logic Guide Instruction 2- NC Contact pace Requirement: 1 line x 1 column Location Requirement: Left rail, iddle NC (normally closed) contact of device A. hen the input is ON and the device A is OFF, the output is turned ON. Input Operation Output OFF Regardless of the state of device A OFF ON hen device A is OFF. ON hen device A is ON. OFF Coil or it Register Constant Index Name T. C. A Device Timing Diagram: Coil 0022 comes on when the device 0000 and 0001 are both OFF.

24 APware-7000 Ladder Logic Guide 16 Instruction 3- Output pace Requirement: 1 line x 1 column Location Requirement: Right rail This is the output coil of device A. hen the input is ON, the device A is ON. Input Operation Output OFF ets device A to OFF. -- ON ets device A to ON. -- Coil or it Register Constant Index Name T. C. A Device Timing Diagram: Coil 0005 comes on when the device 0000 is ON.

25 17 APware-7000 Ladder Logic Guide Instruction 4- Rising Edge (Transitional Contact) pace Requirement: 1 line x 1 column Location Requirement: Left rail, iddle hen the input at last scan is OFF and the input at this scan is ON, the output is turned ON. This instruction is used to detect the input changing from OFF to ON. Input Operation Output OFF Regardless of the input state at last scan. OFF ON hen the input state at last scan is OFF. ON hen the input state at last scan is ON. OFF No operand is required. Timing Diagram: Coil 0002 comes ON for only 1 scan when the device 0000 comes ON.

26 APware-7000 Ladder Logic Guide 18 Instruction 5- Falling Edge (Transitional Contact) pace Requirement: 1 line x 1 column Location Requirement: Left rail, iddle hen the input at last scan is ON and the input at this scan is OFF, the output is turned ON. This instruction is used to detect the input changing from ON to OFF Input Operation Output OFF hen the input state at last scan is OFF. OFF hen the input state at last scan is ON. ON ON Regardless of the input state at last scan. OFF No operand is required. Timing Diagram: Coil 0002 comes ON for only 1 scan when the device 0000 comes OFF.

27 19 APware-7000 Ladder Logic Guide Instruction 6- Forced Coil pace Requirement: 1 line x 1 column Location Requirement: Right rail Regardless of the input state, the state of device A is retained. Input Operation Output OFF No operation --- ON No operation --- Coil or it Register Constant Index Name T. C. A Device Timing Diagram: Device 0005 retains the preceding state regardless of the devices 0000 state. Note: The forced coil is a debugging function. The state of a forced coil device can be set ON or OFF by the programming tool.

28 APware-7000 Ladder Logic Guide 20 Instruction 7- Inverter pace Requirement: 1 line x 1 column Location Requirement: Left rail, iddle hen the input is OFF, the output is turned ON, and when the input is ON, the output is turned OFF. This instruction inverts the link state. Input Operation Output OFF Inverts the input state. ON ON Inverts the input state. OFF No operand is required. Timing Diagram: Device 0002 comes ON when 0000 is OFF, and 0002 comes OFF when 0000 is ON.

29 21 APware-7000 Ladder Logic Guide Instruction 8- Inverter Coil pace Requirement: 1 line x 1 column Location Requirement: Right rail hen the input is OFF, the device A is set to ON, and when the input is ON, the device A is set to OFF. This instruction inverts the input state and stores it in device A. Input Operation Output OFF ets device A ON. --- ON ets device A OFF. --- Coil or it Register Constant Index Name T. C. A Device Timing Diagram: Device 0005 comes ON when 0000 is OFF, and 0005 comes OFF when 0000 is ON.

30 APware-7000 Ladder Logic Guide 22 Instruction 9- Positive Pulse Contact pace Requirement: 1 line x 1 column Location Requirement: Left rail, iddle hen the input is ON and the device A is changed from OFF to ON (OFF at last scan and ON at this scan), the output is turned ON. This instruction is used to detect the device changing from OFF to ON. Input Operation Output OFF Regardless of the state of device A. OFF tate of device A is OFF. OFF ON tate of device A is ON. A is OFF at last scan. ON A is ON at last scan. OFF Coil or it Register Constant Index Name T. C. A Device Timing Diagram: 0100 comes ON for only 1 scan when 0000 is ON and 0003 changes to ON.

31 23 APware-7000 Ladder Logic Guide Instruction 10- Negative Pulse Contact pace Requirement: 1 line x 1 column Location Requirement: Left rail, iddle hen the input is ON and the device A is changed from ON to OFF (ON at last scan and OFF at this scan), the output is turned ON. This instruction is used to detect the device changing from ON to OFF. Input Operation Output OFF Regardless of the state of device A. OFF tate of device A is OFF. A is OFF at last scan. OFF ON A is ON at last scan. ON tate of device A is ON. OFF Coil or it Register Constant Index Name T. C. A Device Timing Diagram: 0100 comes ON for only 1 scan when 0000 is ON and 0003 changes to OFF.

32 APware-7000 Ladder Logic Guide 24 Instruction 11- Positive Pulse Coil pace Requirement: 1 line x 1 column Location Requirement: Right rail hen the input is changed from OFF to ON, the device A is set to ON for 1 scan time. This instruction is used to detect the input changing from OFF to ON. Input Operation Output OFF ets device A to OFF. --- ON hen the input at last scan is OFF, sets A to ON. --- hen the input at last scan is OFF, sets A to OFF. --- Coil or it Register Constant Index Name T. C. A Device Timing Diagram: 0101 comes ON for only 1 scan when 0000 is changed from OFF to ON.

33 25 APware-7000 Ladder Logic Guide Instruction 12- Negative Pulse Coil pace Requirement: 1 line x 1 column Location Requirement: Right rail hen the input is changed from ON to OFF, the device A is set to ON for 1 scan time. This instruction is used to detect the input changing from ON to OFF. Input Operation Output OFF hen the input at last scan is OFF, sets A to OFF. --- hen the input at last scan is ON, sets A to ON. --- ON ets device A to OFF. --- Coil or it Register Constant Index Name T. C. A Device Timing Diagram: 0101 comes ON for only 1 scan when 0000 is changed from ON to OFF.

34 APware-7000 Ladder Logic Guide 26 Instruction 13- OV ord pace Requirement: 1 line x 5 column Location Requirement: iddle, Right rail hen the input is ON, the data of A is stored in. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A ource Destination Examples: ample 1- oving a constant value into a register 0010 is ON, a constant data (12345) is stored in D0100 and the output is turned ON. ample 2- Copying a value in a register to another register hen is ON, the data of 030 is stored in 045 and the output is turned ON. If 030 is 500, the data 500 is stored in 045.

35 27 APware-7000 Ladder Logic Guide ample 3- Using the Index Register feature hen 050 is changed from OFF to ON, the data of 008 is stored in the index register I and the data of D(0000+I) is stored in 010. If 008 is 300, the data of D0300 is stored in 010.

36 APware-7000 Ladder Logic Guide 28 Instruction 14- OV Dord pace Requirement: 1 line x 5 column Location Requirement: iddle, Right rail hen the input is ON, the double-word (32-bit) data of A+1 A is stored in double-word register +1. The data range is to Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A ource Destination hen 011 is ON, a double-word data of D0101 D0100 is stored in and the output is turned ON. If D0101 D0100 is , the data is stored in

37 29 APware-7000 Ladder Logic Guide Instruction 15- Invert Transfer pace Requirement: 1 line x 5 column Location Requirement: iddle, Right rail hen the input is ON, the bit-inverted data of A is stored in. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A ource Destination hen 005 is ON, the bit-inverted data of 30 is stored in D0200 and the output is turned ON. If 30 is H4321, the bit-inverted data (HCDE) is stored in D0200.

38 APware-7000 Ladder Logic Guide 30 Instruction 16- Table Initialize pace Requirement: 1 line x 5 column Location Requirement: iddle, Right rail hen the input is ON, the data of A is stored in n registers starting with. The allowable range of the table size n is 1 to 1024 words. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A ource n Table ize tart of Destination hen 010 is ON, a constant data (0) is stored in 100 registers starting with D0200 (D0200 to D0299) and the output is turned ON.

39 31 APware-7000 Ladder Logic Guide Instruction 17- Table lock Transfer pace Requirement: 1 line x 5 column Location Requirement: iddle, Right rail hen the input is ON, the data of n registers starting with A are transferred to n registers starting with in a block. The allowable range of the table size n is 1 to 1024 words. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A tart of ource n Table ize tart of Destination hen 010 is ON, the data of D0500 to D0509 (10 registers) are block transferred to D1000 to D1009, and the output is turned ON. Note: The source and destination tables can overlap.

40 APware-7000 Ladder Logic Guide 32 Instruction 18- Table Invert Transfer pace Requirement: 1 line x 5 column Location Requirement: iddle, Right rail hen the input is ON, the data of n registers starting with A are bit-inverted and transferred to n registers starting with in a block. The allowable range of the table size n is 1 to 1024 words. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A tart of ource n Table ize tart of Destination hen 010 is ON, the data of D0600 to D0604 (5 registers) are bit-inverted and transferred to D0865 to D0869, and the output is turned ON. Note: The source and destination tables can overlap.

41 33 APware-7000 Ladder Logic Guide Instruction 19- Data Exchange pace Requirement: 1 line x 5 column Location Requirement: iddle, Right rail hen the input is ON, the data of A and the data of is exchanged. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A Operation Data Operation Data hen 005 is ON, the data of 23 and D0100 is exchanged. If the original data of 23 is and that of D0100 is 291, the operation result is as follows. efore Operation After Operation

42 APware-7000 Ladder Logic Guide 34 Instruction 20- ultiplexer pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the data of the register which is designated by in the table, size n starting with A, is transferred to C. Input Operation Output OFF No execution OFF ON Normal Execution OFF Pointer Over (no execution) ON Coil or it Register Constant Index Name T. C. A tart of Table n Table ize 1-64 Pointer 0-63 C Destination hen 010 is ON, the register data which is designated by 30 is read from the table D0500 to D0509 (10 registers size), and stored in D0005. If the data of 30 is 7, D0507 data is transferred to D0005.

43 35 APware-7000 Ladder Logic Guide Note: If the pointer data designates outside the table (10 or more in the above example), the transfer is not executed and the output comes ON. The table must be within the effective range of the register address.

44 APware-7000 Ladder Logic Guide 36 Instruction 21- Demultiplexer pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the data of A is transferred to the register which is designated by in the table, size n starting with C. Input Operation Output OFF No execution OFF ON Normal Execution OFF Pointer Over (no execution) ON Coil or it Register Constant Index Name T. C. A ource n Table ize 1-64 Pointer 0-63 C tart of Table hen 011 is ON, the data of 04 is transferred to the register which is designated by 30 in the table D0500 to D0509 (10 registers size). If the data of 30 is 8, 04 data is transferred to D0508.

45 37 APware-7000 Ladder Logic Guide Note: If the pointer data designates outside the table (10 or more in the above example), the transfer is not executed and the output comes ON. The table must be within the effective range of the register address.

46 APware-7000 Ladder Logic Guide 38 Instruction 22- Addition pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the data of A and the data of are added, and the result is stored in C. If the result is greater than 32767, the upper limit value is stored in C, and the output is turned ON. If the result is smaller than , the lower limit value is stored in C, and the output is turned ON. Input Operation Output OFF No execution OFF ON Execution (normal) OFF Execution (overflow or underflow condition) ON Coil or it Register Constant Index Name T. C. A Augend Addent C um hen 005 is ON, the data of D0100 and the constant data 1000 is added, and the result is stored in D0110. If the data of D0100 is 12345, the result is stored in D0110, and 010 is turned OFF.

47 39 APware-7000 Ladder Logic Guide If the data of D0100 is 32700, the result exceeds the limit value, therefore is stored in D0110, and 010 is turned ON.

48 APware-7000 Ladder Logic Guide 40 Instruction 23- Double-ord Addition elect the Addition function and place it in the logic block. elect Dord from the Data Properties selection tab as shown below: Thus by selecting Dord in Data Properties, the Addition function can be changed to Doubleword Addition entry as shown below: pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the double-word data of A+1 A and +1 are added, and the result is stored in C+1 C. The data range is to

49 41 APware-7000 Ladder Logic Guide If the result is greater than , the upper limit value is stored in C+1 C, and the output is turned ON. If the result is smaller than , the lower limit value is stored in C+1 C, and the output is turned ON. Input Operation Output OFF No execution OFF ON Execution (normal) OFF Execution (overflow or underflow condition) ON Coil or it Register Constant Index Name T. C. A Augend Addent C um hen 005 is ON, the data of D0011 D0010 and the constant data is added, and the result is stored in D0101 D0100. If the data of D0011 D0010 is , the result is stored in D0101 D0100, and 010 is turned OFF. (No overflow/underflow).

50 APware-7000 Ladder Logic Guide 42 Instruction 24- ubtraction pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the data of is subtracted from the data of A, and the result is stored in C. If the result is greater than 32767, the upper limit value is stored in C, and the output is turned ON. If the result is smaller than , the lower limit value is stored in C, and the output is turned ON. Input Operation Output OFF No execution OFF ON Execution (normal) OFF Execution (overflow or underflow condition) ON Coil or it Register Constant Index Name T. C. A inuend ubtrahend C Difference hen 005 is ON, the constant data 2500 is subtracted from the data of D0200, and the result is stored in 50. If the data of D0200 is 15000, the result is stored in 50, and 010 is turned OFF.

51 43 APware-7000 Ladder Logic Guide If the data of D0200 is , the result is smaller than the limit value, therefore is stored in 50, and 010 is turned ON.

52 APware-7000 Ladder Logic Guide 44 Instruction 25- Double-ord ubtraction elect the ubtraction function and place it in the logic block. elect Dord from the Data Properties selection tab as shown below: Thus by selecting Dord in Data Properties, the ubtraction function can be changed to Double-word ubtraction as shown below:

53 45 APware-7000 Ladder Logic Guide pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the double-word data of +1 is subtracted from A+1 A, and the result is stored in C+1 C. The data range is to If the result is greater than , the upper limit value is stored in C+1 C, and the output is turned ON. If the result is smaller than , the lower limit value is stored in C+1 C, and the output is turned ON. Input Operation Output OFF No execution OFF ON Execution (normal) OFF Execution (overflow or underflow condition) ON Coil or it Register Constant Index Name T. C. A inuend ubtrahend C Difference hen 005 is ON, the double-word data of is subtracted from the double-word data of D0101 D0100, and the result is stored in D0103 D0102. If the data of D0101 D0100 is and the data of is 80000, the result is stored in D0103 D0102, and 010 is turned OFF. (No overflow/underflow).

54 APware-7000 Ladder Logic Guide 46

55 47 APware-7000 Ladder Logic Guide Instruction 26- ultiplication pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the data of A is multiplied by the data of, and the result is stored in double length register C+1 C. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A ultiplicand ultiplexer C Product hen 005 is ON, the data of D0050 is multiplied by the data of 050, and the result is stored in double length register D0101 D0100 (upper 16-bit in D0101 and lower 16-bit in D0100). If the data of D0050 is 1500 and the data of 05 is 20, the result is stored in D0101 D0100.

56 APware-7000 Ladder Logic Guide 48 Instruction 27- Unsigned ultiplication elect ultiplication function and place it in the logic block. elect Unsigned in the Data Properties selection tab as shown below:

57 49 APware-7000 Ladder Logic Guide Instruction 27- Unsigned ultiplication (continued) pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the unsigned data of A and are multiplied, and the result is stored in double-length register C+1 C. The data range of A and is 0 to (unsigned 16-bit data). Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A ultiplicand ultiplexer C Product hen 010 is ON, the data of D0050 is multiplied by the data of 05, and the result is stored in double length register D0101 D0100 (upper 16-bit in D0101 and lower 16-bit in D0100). If the data of D0050 is and the data of 05 is 30, the result is stored in D0101 D0100. Note: This instruction handles the register data as unsigned integer.

58 APware-7000 Ladder Logic Guide 50 Instruction 28- Division pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the data of A is divided by the data of, and the quotient is stored in C and the remainder in C+1. Input Operation Output ERF OFF No execution OFF --- ON Normal Execution ( 0) ON --- No execution ( = 0) OFF --- Coil or it Register Constant Index Name T. C. A ultiplicand ultiplexer C Product hen 005 is ON, the data of 22 is divided by the constant data 325, and the quotient is stored in 27 and the remainder is stored in 28. If the data of 22 is 2894, the quotient 8 is stored in 27 and the remainder 294 is stored in 28. Note:

59 51 APware-7000 Ladder Logic Guide If the divisor (operand ) is 0, the ERF (instruction error flag = 1010) is set to ON. The ERF (1010) can be reset to OFF by user program, e.g. [ RT 1010 ]. If the index register K is used as operand C, the remainder is ignored. If operand A is and operand is -1, the data is stored in C and 0 is stored in C+1.

60 APware-7000 Ladder Logic Guide 52 Instruction 29- Unsigned Division elect Division function and place it in the logic block. elect Unsigned division from the Data Properties selection tab as shown below:

61 53 APware-7000 Ladder Logic Guide Instruction 29- Unsigned Division (continued) pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the unsigned data of A is divided by the unsigned data of, and the quotient is stored in C and the remainder in C+1. The data range of A and is 0 to (unsigned 16-bit data). Input Operation Output ERF OFF No execution OFF --- ON Normal Execution ( 0) ON --- No execution ( = 0) OFF et Coil or it Register Constant Index Name T. C. A Dividend Divisor C Quotient hen 010 is ON, the data of D0030 is divided by the constant data 300, and the quotient is stored in D0050 and the remainder is stored in D0051. If the data of D0030 is 54321, the quotient 181 is stored in D0050 and the remainder 21 is stored in D0051.

62 APware-7000 Ladder Logic Guide 54 Note: If divisor (operand ) is 0, ERF (instruction error flag = 1010) is set to ON. The ERF (1010) can be reset to OFF by user program, e.g. [ RT 1010 ]. If the index register K is used as operand C, the remainder is ignored. This instruction handles the register data as unsigned integer.

63 55 APware-7000 Ladder Logic Guide Instruction 30- Division Double ord pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the double-word data of A+1 A is divided by the data of, and the quotient is stored in C and the remainder in C+1. The data range of A+1 A is 0 to , and the data range of and C is 0 to If the quotient is greater than (overflow), the limit value is stored in C, 0 is stored in C+1, and the instruction error flag (ERF = 051) is set to ON. Input Operation Output ERF OFF No execution OFF --- Normal Execution ( 0) ON --- ON Overflow ( 0) ON et No execution ( = 0) OFF et Coil or it Register Constant Index Name T. C. A Dividend Divisor C Quotient hen 010 is ON, the double-word data of D0201 D0200 is divided by the constant data 4000, and the quotient is stored in D1000 and the remainder is stored in D1001.

64 APware-7000 Ladder Logic Guide 56 If the data of D0201 D0200 is , the quotient 83 is stored in D1000 and the remainder 257 is stored in D1001. Note: If the divisor (operand ) is 0, the ERF (instruction error flag = 1010) is set to ON. The ERF (1010) can be reset to OFF by user program, e.g. [ RT 1010 ]. If the index register K is used as operand C, the remainder is ignored. This instruction handles the register data as unsigned integer.

65 57 APware-7000 Ladder Logic Guide Instruction 31- Addition with carry pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the data of A, and the carry flag (CF = 976) are added, and the result is stored in C. If the carry occurs in the operation, the carry flag is set to ON. If the result is greater than or smaller than , the output is turned ON. This instruction is used to perform unsigned addition or double-length addition. Input Operation Output ERF OFF No execution OFF --- Normal No Carry OFF Reset ON Execution Carry Occurred OFF et Overflow/ No Carry ON Reset Underflow Carry Occurred ON et Coil or it Register Constant Index Name T. C. A Augend Addend C um

66 APware-7000 Ladder Logic Guide 58 hen 013 is ON, the data of double-length registers D0100 D0101 and are added, and the result is stored in D0201 D0200. The RTC is a instruction to reset the carry flag before starting the calculation. If the data of D0100 D0101 is and is 54322, the result is stored in D0201 D0200.

67 59 APware-7000 Ladder Logic Guide Instruction 32- ubtraction with carry pace Requirement: 1 line x 6 column Location Requirement: iddle, Right rail hen the input is ON, the data of and the carry flag (CF = 976) are subtracted from A, and the result is stored in C. If a borrow occurs in the operation, the carry flag is set to ON. If the result is greater than or smaller than , the output is turned ON. This instruction is used to perform unsigned subtraction or double-length subtraction. Input Operation Output ERF OFF No execution OFF --- Normal No orrow OFF Reset ON Execution orrow Occurred OFF et Overflow/ No orrow ON Reset Underflow orrow Occurred ON et Coil or it Register Constant Index Name T. C. A inuend ubtrahend C Difference

68 APware-7000 Ladder Logic Guide 60 hen 013 is ON, the data of double-length register is subtracted from the data of D0201 D0200, and the result is stored in D0211 D0210. The RTC is a instruction to reset the carry flag before starting the calculation. If the data of D0200 D0201 is and is , the result 5678 is stored in D0210 D0211.

69 61 APware-7000 Ladder Logic Guide Instruction 33- Increment pace Requirement: 1 line x 3 column Location Requirement: iddle, Right rail hen the input is ON, the data of A is increased by 1 and stored in A. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A Operation Data At the rising edge of 004 changes from OFF to ON, the data of D0050 is increased by 1 and stored in D0050. If the data of D0050 is 750 before the execution, it will be 751 after the execution. Note: There is no limit value for this instruction. hen the data of operand A is before the execution, it will be after the execution

70 APware-7000 Ladder Logic Guide 62 Instruction 34- Decrement pace Requirement: 1 line x 3 column Location Requirement: iddle, Right rail hen the input is ON, the data of A is decreased by 1 and stored in A. Input Operation Output OFF No execution OFF ON Execution ON Coil or it Register Constant Index Name T. C. A Operation Data At the rising edge of 005 changes from OFF to ON, the data of D0050 is decreased by 1 and stored in D0050. If the data of D0050 is 1022 before the execution, it will be 1021 after the execution. Note: There is no limit value for this instruction. hen the data of operand A is before the execution, it will be after the execution