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1 Data Sheet Summary MC68HC98QYSM/D Rev.., / MC68HC98QY, MC68HC98QT, MC68HC98QY, MC68HC98QT, MC68HC98QY, MC68HC98QT Introduction General Description This document provides an overview of the MC68HC98QY, MC68HC98QT, MC68HC98QY, MC68HC98QT, MC68HC98QY, and MC68HC98QT devices. For complete details refer to the MC68HC98QY Data Sheet (Motorola document order number MC68HC98QY/D). The MC68HC98QY is a member of the low-cost, high-performance M68HC8 Family of 8-bit microcontroller units (MCUs). The M68HC8 Family is a Complex Instruction Set Computer (CISC) with a Von Neumann architecture. All MCUs in the family use the enhanced M68HC8 central processor unit (CPU8) and are available with a variety of modules, memory sizes and types, and package types. Table. MC Order Numbers MC Order Number ADC FLASH Memory Package MC68HC98QY 6 bytes MC68HC98QY Yes 6 bytes MC68HC98QY Yes 96 bytes MC68HC98QT 6 bytes MC68HC98QT Yes 6 bytes MC68HC98QT Yes 96 bytes Temperature and package designators: C = C to +8 C V = C to + C (available for V DD = V only) M = C to + C (available for V DD = V only) P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC) DT = Thin shrink small outline package (TSSOP) FQ = Dual flat no lead (DFN) 6-pins PDIP, SOIC, and TSSOP 8-pins PDIP, SOIC, and DFN This product incorporates SuperFlash technology licensed from SST.

2 MC68HC98QYSM/D Features Features include: High-performance M68HC8 CPU core Fully upward-compatible object code with M68HC Family -V and -V operating voltages (V DD ) 8-MHz internal bus operation at V, -MHz at V Trimmable internal oscillator. MHz internal bus operation 8-bit trim capability, ± % trimmed Auto wakeup from STOP capability Configuration (CONFIG) register for MCU configuration options, including low-voltage inhibit (LVI) trip point In-system FLASH programming FLASH security () On-chip in-application programmable FLASH memory (with internal program/erase voltage generation) MC68HC98QY and MC68HC98QT 96 bytes MC68HC98QY, MC68HC98QY, MC68HC98QT, and MC68HC98QT 6 bytes 8 bytes of on-chip random-access memory (RAM) -channel, 6-bit timer interface module (TIM) -channel, 8-bit analog-to-digital converter (ADC) on MC68HC98QY, MC68HC98QY, MC68HC98QT, and MC68HC98QT or bidirectional input/output (I/O) lines and one input only: High current sink/source capability on all port pins Selectable pullups on all ports, selectable on an individual bit basis 6-bit keyboard interrupt with wakeup feature (KBI) Low-voltage inhibit (LVI) module features software selectable trip point in CONFIG register. No security feature is absolutely secure. However, Motorola s strategy is to make reading or copying the FLASH diicult for unauthorized users. Data Sheet Summary MC68HC98QY/QT Family Rev.. Features

3 MC68HC98QYSM/D MCU Block Diagram MCU Block Diagram Memory System protection features: Computer operating properly (COP) watchdog Low-voltage detection with reset Illegal opcode detection with reset Illegal aress detection with reset External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose input pin Master asynchronous reset pin (RST) shared with general-purpose I/O pin Power-on reset Internal pullups on IRQ and RST to reduce external components Memory mapped I/O registers Power saving stop and wait modes MC68HC98QY, MC68HC98QY, and MC68HC98QY are available in these packages: 6-pin plastic dual in-line package (PDIP) 6-pin small outline integrated circuit (SOIC) package 6-pin thin shrink small outline package (TSSOP) MC68HC98QT, MC68HC98QT, and MC68HC98QT are available in these packages: 8-pin PDIP 8-pin SOIC 8-pin dual flat no lead (DFN) See Figure. The central processor unit (CPU8) can aress 6 Kbytes of memory space. The memory map is shown in Figure. Aresses $ $F, shown in Figure, contain most of the control, status, and data registers. The vector aresses are shown in Table. MC68HC98QY/QT Family Rev.. MCU Block Diagram Data Sheet Summary

4 MC68HC98QYSM/D V DD V SS POWER SUPPLY CLOCK GENERATOR SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 6-BIT TIMER MODULE COP MODULE MONITOR ROM PTB[:7] PTB DDRB PTA/AD/TCH/KBI CPU CONTROL ALU 68HC8 CPU ACCUMULATOR CPU REGISTERS INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER V H I N Z C 8-BIT ADC PTA DDRA PTA/AD/TCH/KBI PTA/IRQ/KBI PTA/RST/KBI PTA/OSC/AD/KBI PTA/OSC/AD/KBI 8 BYTES RAM MC68HC98QY AND MC68HC98QT: 96 BYTES MC68HC98QY, MC68HC98QY, MC68HC98QT, AND MC68HC98QT: 6 BYTES USER FLASH RST, IRQ: Pins have internal (about K Ohms) pull up PTA[:]: High current sink and source capability PTA[:]: Pins have programmable keyboard interrupt and pull up PTB[:7]: Not available on 8-pin devices MC68HC98QT, MC68HC98QT, and MC68HC98QT Figure. Block Diagram Data Sheet Summary MC68HC98QY/QT Family Rev.. Memory

5 MC68HC98QYSM/D Pin Assignments Pin Assignments V DD 8 V SS V DD 8 V SS PTA/OSC/KBI 7 PTA/TCH/KBI PTA/OSC/AD/KBI 7 PTA/AD/TCH/KBI PTA/OSC/KBI 6 PTA/TCH/KBI PTA/OSC/AD/KBI 6 PTA/AD/TCH/KBI PTA/RST/KBI PTA/IRQ/KBI PTA/RST/KBI PTA/IRQ/KBI 8-PIN ASSIGNMENT MC68HC98QT PDIP/SOIC 8-PIN ASSIGNMENT MC68HC98QT AND MC68HC98QT PDIP/SOIC V DD PTB7 PTB6 PTA/OSC/KBI PTA/OSC/KBI PTB PTB PTA/RST/KBI PTA/TCH/KBI PTB PTB V SS V DD PTB7 PTB6 PTA/OSC/KBI PIN ASSIGNMENT MC68HC98QY PDIP/SOIC PIN ASSIGNMENT MC68HC98QY TSSOP 9 9 V SS PTB PTB PTA/TCH/KBI PTA/TCH/KBI PTB PTB PTA/IRQ/KBI PTA/TCH/KBI PTB PTB PTA/IRQ/KBI PTA/RST/KBI PTB PTB PTA/OSC/KBI V DD PTB7 PTB6 PTA/OSC/AD/KBI PTA/OSC/AD/KBI PTB PTB PTA/RST/KBI V SS PTB PTB PTA/AD/TCH/KBI PTA/AD/TCH/KBI PTB PTB PTA/IRQ/KBI 6-PIN ASSIGNMENT MC68HC98QY AND MC68HC98QY PDIP/SOIC PTA/AD/TCH/KBI PTB PTB V SS V DD PTB7 PTB6 PTA/OSC/AD/KBI PTA/AD/TCH/KBI PTB PTB PTA/IRQ/KBI PTA/RST/KBI PTB PTB PTA/OSC/AD/KBI 6-PIN ASSIGNMENT MC68HC98QY AND MC68HC98QY TSSOP 6 9 PTA/TCH/KBI 8 PTA/TCH/KBI PTA/AD/TCH/KBI 8 PTA/AD/TCH/KBI V SS 7 PTA/IRQ/KBI V SS 7 PTA/IRQ/KBI V DD 6 PTA/RST/KBI V DD 6 PTA/RST/KBI PTA/OSC/KB PTA/OSC/KBI PTA//OSC/AD/KB PTA/OSC/AD/KBI 8-PIN ASSIGNMENT MC68HC98QT DFN 8-PIN ASSIGNMENT MC68HC98QT AND MC68HC98QT DFN Figure. MCU Pin Assignments MC68HC98QY/QT Family Rev.. Pin Assignments Data Sheet Summary

6 MC68HC98QYSM/D Pin Functions Pin Name Table provides a description of the pin functions. Table. Pin Functions Description Input/Output V DD Power supply Power V SS Power supply ground Power PTA PTA PTA PTA PTA PTA PTA General purpose I/O port AD A/D channel input TCH Timer Channel I/O KBI Keyboard interrupt input PTA General purpose I/O port AD A/D channel input TCH Timer Channel I/O KBI Keyboard interrupt input PTA General purpose input-only port IRQ External interrupt with programmable pullup and Schmitt trigger input KBI Keyboard interrupt input PTA General purpose I/O port RST Reset input, active low with internal pullup and Schmitt trigger KBI Keyboard interrupt input PTA General purpose I/O port OSC XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSCEN = in PTAPUE register) AD A/D channel input KBI Keyboard interrupt input PTA General purpose I/O port OSC XTAL, RC, or external oscillator input AD A/D channel input KBI Keyboard interrupt input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input Input Input Input/Output Input Input Input/Output Output Output Input Input Input/Output PTB[:7] () 8 general-purpose I/O ports. Input/Output Input Input Input. The PTB pins are not available on the 8-pin packages. Data Sheet Summary MC68HC98QY/QT Family Rev.. Pin Functions

7 MC68HC98QYSM/D Pin Functions $ $F $ $7F $8 $FF $ $7FF $8 $DFF $E $EDFF $EE $FDFF $FE $FE $FE $FE $FE $FE $FE6 $FE7 $FE8 $FE9 $FEA $FEB $FEC $FED $FEF $FE $FFAF $FFB $FFBD $FFBE $FFBF $FFC $FFC $FFC $FFCF $FFD $FFFF I/O REGISTERS 6 BYTES RESERVED () 6 BYTES RAM 8 BYTES UNIMPLEMENTED () 998 BYTES AUXILIARY ROM 6 BYTES UNIMPLEMENTED () 9 BYTES FLASH MEMORY MC68HC98QT AND MC68HC98QY 96 BYTES BREAK STATUS REGISTER (BSR) RESET STATUS REGISTER (SRSR) BREAK AUXILIARY REGISTER (BRKAR) BREAK FLAG CONTROL REGISTER (BFCR) INTERRUPT STATUS REGISTER (INT) INTERRUPT STATUS REGISTER (INT) INTERRUPT STATUS REGISTER (INT) RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR) FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS HIGH REGISTER (BRKH) BREAK ADDRESS LOW REGISTER (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVISR RESERVED FOR FLASH TEST BYTES MONITOR ROM 6 BYTES FLASH BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) RESERVED FLASH INTERNAL OSCILLATOR TRIM VALUE RESERVED FLASH FLASH BYTES USER VECTORS 8 BYTES Figure. Memory Map Note. Attempts to execute code from aresses in this range will generate an illegal aress reset. UNIMPLEMENTED 7 BYTES FLASH MEMORY 6 BYTES MC68HC98QT, MC68HC98QT, MC68HC98QY, and MC68HC98QY Memory Map $E $F7FF $F8 $FDFF MC68HC98QY/QT Family Rev.. Data Sheet Summary Pin Functions

8 MC68HC98QYSM/D Ar. Register Bit 7 6 Bit $ PTA R AWUL PTA PTA PTA PTA PTA PTA $ PTB PTB7 PTB6 PTB PTB PTB PTB PTB PTB $ Unimplemented $ Unimplemented $ DDRA R R DDRA DDRA DDRA DDRA DDRA $6 DDRB DDRB7 DDRB6 DDRB DDRB DDRB DDRB DDRB DDRB $7 $A Unimplemented Unimplemented $B PTAPUE OSCEN PTAPUE PTAPUE PTAPUE PTAPUE PTAPUE PTAPUE $C PTBPUE PTBPUE7 PTBPUE6 PTBPUE PTBPUE PTBPUE PTBPUE PTBPUE PTBPUE $D $9 Unimplemented Unimplemented $A KBSCR KEYF ACKK IMASKK MODEK $B KBIER AWUIE KBIE KBIE KBIE KBIE KBIE KBIE $C Unimplemented $D INTSCR IRQF ACK IMASK MODE $E CONFIG IRQPUD IRQEN OSCOPT OSCOPT RSTEN $F CONFIG COPRS LVISTOP LVIRSTD LVIPWRD LVIOR SSREC STOP COPD $ TSC TOF TOIE TSTOP TRST PS PS PS $ TCNTH Bit Bit Bit Bit Bit Bit Bit 9 Bit 8 $ TCNTL Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit $ TMODH Bit Bit Bit Bit Bit Bit Bit 9 Bit 8 $ TMODL Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit $ TSC CHF CHIE MSB MSA ELSB ELSA TOV CHMAX $6 TCHH Bit Bit Bit Bit Bit Bit Bit 9 Bit 8 $7 TCHL Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit $8 TSC CHF CHIE MSA ELSB ELSA TOV CHMAX $9 TCHH Bit Bit Bit Bit Bit Bit Bit 9 Bit 8 $A TCHL Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit $B $ Unimplemented Unimplemented $6 OSCSTAT ECGON ECGST $7 Unimplemented $8 OSCTRIM TRIM7 TRIM6 TRIM TRIM TRIM TRIM TRIM TRIM $9 $B Unimplemented Unimplemented $C ADSCR COCO AIEN ADCO CH CH CH CH CH $D Unimplemented $E ADR AD7 AD6 AD AD AD AD AD AD $F ADICLK ADIV ADIV ADIV = Unimplemented or Reserved Figure. Control, Status, and Data Registers (Sheet of ) Data Sheet Summary MC68HC98QY/QT Family Rev.. Pin Functions

9 MC68HC98QYSM/D Pin Functions Ar. Register Bit 7 6 Bit $FE BSR SBSW $FE SRSR POR PIN COP ILOP ILAD MODRST LVI $FE BRKAR BDCOP $FE BFCR BCFE $FE INT IF IF IF IF $FE INT IF $FE6 INT IF $FE7 Reserved $FE8 FLCR HVEN MASS ERASE PGM $FE9 BRKH Bit Bit Bit Bit Bit Bit Bit 9 Bit 8 $FEA BRKL Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit $FEB BRKSCR BRKE BRKA $FEC LVISR LVIOUT $FED $FEF Reserved for FLASH Test Reserved for FLASH Test $FFBE FLBPR BPR7 BPR6 BPR BPR BPR BPR BPR BPR $FFBF Reserved $FFC TRIMLOC NON-VOLATILE TRIM ADJUSTMENT VALUE $FFC Reserved $FFFF COPCTL WRITE ANY VALUE TO RESET COP WATCHDOG. = Unimplemented or Reserved Figure. Control, Status, and Data Registers (Sheet of ) Table. Vector Aresses Vector Priority Vector Aress Vector Lowest $FFDE ADC conversion complete vector (high) IF $FFDF ADC conversion complete vector (low) IF $FFE Keyboard vector (high) $FFE Keyboard vector (low) IF through IF6 Not used IF $FFF TIM overflow vector (high) $FFF TIM overflow vector (low) IF $FFF TIM Channel vector (high) $FFF TIM Channel vector (low) IF $FFF6 TIM Channel vector (high) $FFF7 TIM Channel vector (low) IF Not used IF $FFFA IRQ vector (high) $FFFB IRQ vector (low) $FFFC SWI vector (high) $FFFD SWI vector (low) $FFFE Reset vector (high) Highest $FFFF Reset vector (low) MC68HC98QY/QT Family Rev.. Pin Functions Data Sheet Summary

10 MC68HC98QYSM/D FLASH Module FLASH Control Register The FLASH memory consists of an array of 96 or 6 bytes with an aitional 8 bytes for user vectors and miscellaneous. The minimum size of FLASH memory that can be erased is 6 bytes; and the maximum size of FLASH memory that can be programmed in a program cycle is bytes (a row). Program and erase operations are facilitated through control bits in the FLASH control register (FLCR). Details for these operations appear later in this section. The aress ranges for the user memory and vectors are: $EE $FDFF; user memory, 96 bytes: MC68HC98QY and MC68HC98QT $F8 $FDFF; user memory, 6 bytes: MC68HC98QY, MC68HC98QT, MC68HC98QY and MC68HC98QT $FFB $FFFF; user interrupt vectors etc., 8 bytes. NOTE: An erased bit reads as logic and a programmed bit reads as logic. A security feature prevents unauthorized viewing of the FLASH contents. The FLASH control register (FLCR) controls FLASH program and erase operations. $FE8 Bit 7 6 Bit HVEN MASS ERASE PGM Reset: Figure. FLASH Control Register (FLCR) HVEN High Voltage Enable Bit = High voltage enabled to array and charge pump on MASS Mass Erase Control Bit = Mass Erase operation selected ERASE Erase Control Bit = Erase operation selected PGM Program Control Bit = Program operation selected FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 6 consecutive bytes starting from aresses $XX, $XX, $XX8, or $XXC. The 8-byte user interrupt vectors area includes two pages ($FFB $FFBF and $FFC $FFFF). Any FLASH memory page can be erased alone.. Set the ERASE bit and clear the MASS bit in the FLASH control register.. Read the FLASH block protect register ($FFBE). Data Sheet Summary MC68HC98QY/QT Family Rev.. FLASH Module

11 MC68HC98QYSM/D FLASH Module FLASH Program Operation NOTE: NOTE:. Write any data to any FLASH location within the aress range of the block to be erased.. Wait for a time, t nvs (minimum µs).. Set the HVEN bit. 6. Wait for a time, t Erase (minimum ms or ms). 7. Clear the ERASE and MASS bits. 8. Wait for a time, t nvh (minimum µs). 9. Clear the HVEN bit.. After time, t rcv (typical µs), the memory can be accessed in read mode again. Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. These operations must be performed in the order as shown, but other unrelated operations may occur between the steps. In applications that need up to, program/erase cycles, use the ms page erase specification to get improved long-term reliability. Any application can use this ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than times, and speed is important, use the ms page erase specification to get a lower minimum erase time. Programming of the FLASH memory is done on a row basis. A row consists of consecutive bytes starting from aresses $XX, $XX, $XX, $XX6, $XX8, $XXA, $XXC, or $XXE. Use the following step-by-step procedure to program a row of FLASH memory. Only bytes which are currently $FF may be programmed.. Set the PGM bit. This configures the memory for program operation and enables the latching of aress and data for programming.. Read from the FLASH block protect register ($FFBE).. Write any data to any FLASH location within the aress range desired.. Wait for a time, t nvs (minimum µs).. Set the HVEN bit. 6. Wait for a time, t pgs (minimum µs). 7. Write data to the FLASH aress being programmed (). 8. Wait for time, t PROG (minimum µs). 9. Repeat step 6 and 7 until desired bytes within the row are programmed.. Clear the PGM bit ().. The time between each FLASH aress change, or the time between the last FLASH aress programmed to clearing PGM bit, must not exceed the maximum programming time, t PROG maximum. MC68HC98QY/QT Family Rev.. Data Sheet Summary FLASH Module

12 MC68HC98QYSM/D. Wait for time, t nvh (minimum µs).. Clear the HVEN bit.. After time, t rcv (typical µs), the memory can be accessed in read mode again. NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. These operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed t PROG maximum. FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore it is programmed using a FLASH memory byteprogramming operation. The value in this register determines the starting aress of the protected range within the FLASH memory. The FLASH is protected from this aress to the end of FLASH memory at $FFFF. $FFBE Bit 7 6 Bit Reset: BPR7 BPR6 BPR BPR BPR BPR BPR BPR Unaected by reset. Initial value from factory is all s. Figure 6. FLASH Block Protect Register (FLBPR) BPR[7:] FLASH Protection Register Bits [7:] START ADDRESS OF PROTECTED FLASH BLOCK BPR[7:] $ $B8 Figure 7. FLASH Block Protect Start Aress Table. Examples of Protect Start Aress Start of Aress of Protect Range The entire FLASH memory is protected. $B9 ( ) $EE ( ) $BA ( ) $EE8 ( ) $BB ( ) $EEC ( ) $BC ( ) $EF ( ) and so on... $DE ( ) $F78 ( ) $DF ( ) $F7C ( ) $FE ( ) $FF 6-BIT MEMORY ADDRESS FLBPR VALUE $FF8 ( ) FLBPR, OSCTRIM, and vectors are protected The entire FLASH memory is not protected. Data Sheet Summary MC68HC98QY/QT Family Rev.. FLASH Module

13 MC68HC98QYSM/D Configuration Registers (CONFIG, CONFIG) Configuration Registers (CONFIG, CONFIG) The configuration registers are used to initialize various options. The configuration registers can each be written once after each reset. Most of the configuration register bits are cleared during reset. Since the various options aect the operation of the microcontroller unit (MCU) it is recommended that these registers be written immediately after reset. The configuration registers are located at $E and $F, and may be read at anytime. $E Bit 7 6 Bit NOTE: Reset: POR: IRQPUD IRQEN R OSCOPT OSCOPT R R RSTEN IRQPUD IRQ Pin Pullup Disable Control Bit = Internal pullup is connected between IRQ pin and V DD (if IRQEN = ) IRQEN IRQ Pin Function Selection Bit = PTA/IRQ/KBI pin configured for IRQ function = Pin configured for PTA or KBI function OSCOPT:OSCOPT Selection Bits for Oscillator Option (:) Internal oscillator (:) External oscillator (:) External RC oscillator (:) External XTAL oscillator RSTEN RST Pin Function Selection = PTA/RST/KBI pin configured for RESET function = Pin configured for PTA or KBI function R = Reserved U = Unaected Figure 8 Configuration Register (CONFIG) The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaected. $F Bit 7 6 Bit Reset: POR: COPRS LVISTOP LVIRSTD LVIPWRD LVIOR SSREC STOP COPD U = Unaected COPRS (Out of STOP Mode) COP Reset Period Selection Bit = COP reset short cycle = ( ) x BUSCLKX = COP reset long cycle = ( 8 ) x BUSCLKX To prevent a reset due to a COP watchdog timeout, write any value to COPCTL ($FFFF) before the COP timer reaches the selected timeout. Figure 9 Configuration Register (CONFIG) U U MC68HC98QY/QT Family Rev.. Data Sheet Summary Configuration Registers (CONFIG, CONFIG)

14 MC68HC98QYSM/D NOTE: NOTE: LVI Status Register COPRS (In STOP Mode) Auto Wakeup Period Selection Bit = Auto wakeup short cycle = approximately 6 ms = Auto wakeup long cycle = approximately 6 ms LVISTOP LVI Enable in Stop Mode Bit = LVI enabled during stop mode = LVI disabled during stop mode LVIRSTD LVI Reset Disable Bit = LVI module resets disabled = LVI module resets enabled LVIPWRD LVI Power Disable Bit = LVI module power disabled LVIOR LVI -V or -V Operating Mode Bit = LVI operates in -V mode = LVI operates in -V mode The LVIOR bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaected. SSREC Short Stop Recovery Bit = Stop mode recovery after BUSCLKX cycles = Stop mode recovery after 96 BUSCLKX cycles Exiting stop mode by an LVI reset will result in the long stop recovery. STOP STOP Instruction Enable Bit = STOP instruction enabled = STOP instruction treated as illegal opcode COPD COP Disable Bit = COP module disabled (does not force resets) The LVI status register (LVISR) indicates if the V DD voltage was detected below the V TRIPF level while LVI resets have been disabled. $FEC Bit 7 6 Bit LVIOUT R Reset: R = Reserved LVIOUT LVI Output Bit Figure. LVI Status Register (LVISR) This read-only flag becomes set when the V DD voltage falls below the V TRIPF trip voltage and is cleared when V DD voltage rises above V TRIPR. Data Sheet Summary MC68HC98QY/QT Family Rev.. LVI Status Register

15 MC68HC98QYSM/D IRQ Status and Control Register IRQ Status and Control Register $D Bit 7 6 Bit IRQF ACK IMASK MODE Reset: Figure. IRQ Status and Control Register (INTSCR) SIM Reset Status Register IRQF IRQ Flag This read-only status bit is high when the IRQ interrupt is pending. = IRQ interrupt pending ACK IRQ Interrupt Request Acknowledge Bit Writing a logic to this write-only bit clears the IRQ latch. ACK always reads as logic. IMASK IRQ Interrupt Mask Bit = IRQ interrupt requests disabled MODE IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. = IRQ interrupt requests on falling edges and low levels = IRQ interrupt requests on falling edges only This register contains seven flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. $FE Bit 7 6 Bit POR PIN COP ILOP ILAD MODRST LVI POR: Figure. SIM Reset Status Register (SRSR) POR Power-On Reset Bit = Last reset caused by POR circuit PIN External Reset Bit = Last reset caused by external reset pin (RST) COP Computer Operating Properly Reset Bit = Last reset caused by COP timeout ILOP Illegal Opcode Reset Bit = Last reset caused by an illegal opcode MC68HC98QY/QT Family Rev.. Data Sheet Summary IRQ Status and Control Register

16 MC68HC98QYSM/D ILAD Illegal Aress Reset Bit (illegal attempt to fetch an opcode from an unimplemented aress) = Last reset caused by an opcode fetch from an illegal aress MODRST Monitor Mode Entry Module Reset Bit = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while PTA/IRQ = V DD LVI Low Voltage Inhibit Reset Bit = Last reset caused by LVI circuit Interrupt Status Registers (INT, INT, INT) These three registers include status flags which indicate which interrupt sources currently have pending requests. See Table. $FE Bit 7 6 Bit IF IF IF IF Reset: Source: TOF TCH TCH IRQ Figure. Interrupt Status Register (INT) $FE Bit 7 6 Bit IF Reset: Source: KBI Figure. Interrupt Status Register (INT) $FE6 Bit 7 6 Bit IF Reset: Source: Figure. Interrupt Status Register (INT) ADC IFxx Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown below the corresponding IFxx bit. = Interrupt request pending = No interrupt request present Data Sheet Summary MC68HC98QY/QT Family Rev.. Interrupt Status Registers (INT, INT, INT)

17 MC68HC98QYSM/D Central Processor Unit (CPU) Central Processor Unit (CPU) Figure 6 shows the five CPU registers. CPU registers are not part of the memory map. 7 ACCUMULATOR (A) H X INDEX REGISTER (H:X) 7 V H I N Z C STACK POINTER (SP) Figure 6. CPU Registers PROGRAM COUNTER (PC) CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO S COMPLEMENT OVERFLOW FLAG MC68HC98QY/QT Family Rev.. Central Processor Unit (CPU) Data Sheet Summary

18 MC68HC98QYSM/D Instruction Set Summary Table provides a summary of the M68HC8 instruction set. Table. Instruction Set Summary (Sheet of 7) Source Form Operation Description Eect on CCR VH I NZC Aress Mode Opcode Operand Cycles ADC #opr ADC opr ADC opr ADC opr,x ADC opr,x ADC,X ADC opr,sp ADC opr,sp ADD #opr ADD opr ADD opr ADD opr,x ADD opr,x ADD,X ADD opr,sp ADD opr,sp A with Carry A (A) + (M) + (C)!!!!! A without Carry A (A) + (M)!!!!! IMM EXT SP SP IMM EXT SP SP A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB AIS #opr A Immediate Value (Signed) to SP SP (SP) + (6 «M) IMM A7 ii A #opr A Immediate Value (Signed) to H:X H:X (H:X) + (6 «M) IMM AF ii AND #opr AND opr AND opr AND opr,x AND opr,x AND,X AND opr,sp AND opr,sp ASL opr ASLA ASLX ASL opr,x ASL,X ASL opr,sp ASR opr ASRA ASRX ASR opr,x ASR opr,x ASR opr,sp Logical AND A (A) & (M)!! Arithmetic Shift Left (Same as LSL) C!!!! Arithmetic Shift Right C!!!! b7 b b7 b IMM EXT SP SP SP SP A B C D E F 9EE 9ED E E67 ii hh ll ee ee ii hh ll ee ee ii hh ll ee ee BCC rel Branch if Carry Bit Clear PC (PC) + + rel? (C) = REL rr BCLR n, opr Clear Bit n in M Mn (b) (b) (b) (b) (b) (b) (b6) (b7) 7 9 B D F BCS rel Branch if Carry Bit Set (Same as BLO) PC (PC) + + rel? (C) = REL rr Data Sheet Summary MC68HC98QY/QT Family Rev.. Instruction Set Summary

19 MC68HC98QYSM/D Instruction Set Summary Table. Instruction Set Summary (Sheet of 7) Source Form Operation Description Eect on CCR VH I NZC Aress Mode Opcode Operand Cycles BEQ rel Branch if Equal PC (PC) + + rel? (Z) = REL 7 rr BGE opr BGT opr Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) PC (PC) + + rel? (N V) = REL 9 rr PC (PC) + + rel? (Z) (N V) = REL 9 rr BHCC rel Branch if Half Carry Bit Clear PC (PC) + + rel? (H) = REL 8 rr BHCS rel Branch if Half Carry Bit Set PC (PC) + + rel? (H) = REL 9 rr BHI rel Branch if Higher PC (PC) + + rel? (C) (Z) = REL rr BHS rel Branch if Higher or Same (Same as BCC) PC (PC) + + rel? (C) = REL rr BIH rel Branch if IRQ Pin High PC (PC) + + rel? IRQ = REL F rr BIL rel Branch if IRQ Pin Low PC (PC) + + rel? IRQ = REL E rr BIT #opr BIT opr BIT opr BIT opr,x BIT opr,x BIT,X BIT opr,sp BIT opr,sp BLE opr Bit Test (A) & (M)!! Branch if Less Than or Equal To (Signed Operands) IMM EXT SP SP A B C D E F 9EE 9ED ii hh ll ee ee PC (PC) + + rel? (Z) (N V) = REL 9 rr BLO rel Branch if Lower (Same as BCS) PC (PC) + + rel? (C) = REL rr BLS rel Branch if Lower or Same PC (PC) + + rel? (C) (Z) = REL rr BLT opr Branch if Less Than (Signed Operands) PC (PC) + + rel? (N V) = REL 9 rr BMC rel Branch if Interrupt Mask Clear PC (PC) + + rel? (I) = REL C rr BMI rel Branch if Minus PC (PC) + + rel? (N) = REL B rr BMS rel Branch if Interrupt Mask Set PC (PC) + + rel? (I) = REL D rr BNE rel Branch if Not Equal PC (PC) + + rel? (Z) = REL 6 rr BPL rel Branch if Plus PC (PC) + + rel? (N) = REL A rr BRA rel Branch Always PC (PC) + + rel REL rr BRCLR n,opr,rel Branch if Bit n in M Clear PC (PC) + + rel? (Mn) =! (b) (b) (b) (b) (b) (b) (b6) (b7) 7 9 B D F rr rr rr rr rr rr rr rr BRN rel Branch Never PC (PC) + REL rr MC68HC98QY/QT Family Rev.. Instruction Set Summary Data Sheet Summary

20 MC68HC98QYSM/D Table. Instruction Set Summary (Sheet of 7) Source Form Operation Description Eect on CCR VH I NZC Aress Mode Opcode Operand Cycles BRSET n,opr,rel Branch if Bit n in M Set PC (PC) + + rel? (Mn) =! (b) (b) (b) (b) (b) (b) (b6) (b7) 6 8 A C E rr rr rr rr rr rr rr rr BSET n,opr Set Bit n in M Mn BSR rel CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,x+,rel CBEQ X+,rel CBEQ opr,sp,rel Branch to Subroutine Compare and Branch if Equal PC (PC) + ; push (PCL) SP (SP) ; push (PCH) SP (SP) PC (PC) + rel PC (PC) + + rel? (A) (M) = $ PC (PC) + + rel? (A) (M) = $ PC (PC) + + rel? (X) (M) = $ PC (PC) + + rel? (A) (M) = $ PC (PC) + + rel? (A) (M) = $ PC (PC) + + rel? (A) (M) = $ (b) (b) (b) (b) (b) (b) (b6) (b7) 6 8 A C E REL AD rr CLC Clear Carry Bit C 98 CLI Clear Interrupt Mask I 9A CLR opr CLRA CLRX CLRH CLR opr,x CLR,X CLR opr,sp CMP #opr CMP opr CMP opr CMP opr,x CMP opr,x CMP,X CMP opr,sp CMP opr,sp Clear M $ A $ X $ H $ M $ M $ M $ Compare A with M (A) (M)!!!! IMM IMM + + SP SP IMM EXT SP SP 6 7 9E6 F F F 8C 6F 7F 9E6F A B C D E F 9EE 9ED rr ii rr ii rr rr rr rr ii hh ll ee ee 6 COM opr COMA COMX COM opr,x COM,X COM opr,sp Complement (One s Complement) M (M) = $FF (M) A (A) = $FF (M) X (X) = $FF (M) M (M) = $FF (M) M (M) = $FF (M) M (M) = $FF (M)!! SP 6 7 9E6 CPHX #opr CPHX opr Compare H:X with M (H:X) (M:M + )!!!! IMM 6 7 ii ii+ Data Sheet Summary MC68HC98QY/QT Family Rev.. Instruction Set Summary

21 MC68HC98QYSM/D Instruction Set Summary Table. Instruction Set Summary (Sheet of 7) Source Form Operation Description Eect on CCR VH I NZC Aress Mode Opcode Operand Cycles CPX #opr CPX opr CPX opr CPX,X CPX opr,x CPX opr,x CPX opr,sp CPX opr,sp Compare X with M (X) (M)!!!! IMM EXT SP SP A B C D E F 9EE 9ED ii hh ll ee ee DAA Decimal Adjust A (A) U!!! 7 DBNZ opr,rel DBNZA rel DBNZX rel DBNZ opr,x,rel DBNZ X,rel DBNZ opr,sp,rel DEC opr DECA DECX DEC opr,x DEC,X DEC opr,sp DIV EOR #opr EOR opr EOR opr EOR opr,x EOR opr,x EOR,X EOR opr,sp EOR opr,sp INC opr INCA INCX INC opr,x INC,X INC opr,sp JMP opr JMP opr JMP opr,x JMP opr,x JMP,X Decrement and Branch if Not Zero Decrement Divide A (A) or M (M) or X (X) PC (PC) + + rel? (result) PC (PC) + + rel? (result) PC (PC) + + rel? (result) PC (PC) + + rel? (result) PC (PC) + + rel? (result) PC (PC) + + rel? (result) M (M) A (A) X (X) M (M) M (M) M (M) A (H:A)/(X) H Remainder!!! Exclusive OR M with A A (A M)!! Increment M (M) + A (A) + X (X) + M (M) + M (M) + M (M) + SP SP B B B 6B 7B 9E6B A A A 6A 7A 9E6A rr rr rr rr rr rr!! 7!!! Jump PC Jump Aress IMM EXT SP SP SP EXT A8 B8 C8 D8 E8 F8 9EE8 9ED8 C C C 6C 7C 9E6C BC CC DC EC FC ii hh ll ee ee hh ll ee 6 JSR opr JSR opr JSR opr,x JSR opr,x JSR,X Jump to Subroutine PC (PC) + n (n =,, or ) Push (PCL); SP (SP) Push (PCH); SP (SP) PC Unconditional Aress EXT BD CD DD ED FD hh ll ee 6 LDA #opr LDA opr LDA opr LDA opr,x LDA opr,x LDA,X LDA opr,sp LDA opr,sp Load A from M A (M)!! IMM EXT SP SP A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii hh ll ee ee MC68HC98QY/QT Family Rev.. Instruction Set Summary Data Sheet Summary

22 MC68HC98QYSM/D Table. Instruction Set Summary (Sheet of 7) Source Form Operation Description Eect on CCR VH I NZC Aress Mode Opcode Operand Cycles LDHX #opr LDHX opr Load H:X from M H:X (M:M + )!! IMM ii jj LDX #opr LDX opr LDX opr LDX opr,x LDX opr,x LDX,X LDX opr,sp LDX opr,sp LSL opr LSLA LSLX LSL opr,x LSL,X LSL opr,sp LSR opr LSRA LSRX LSR opr,x LSR,X LSR opr,sp MOV opr,opr MOV opr,x+ MOV #opr,opr MOV X+,opr Load X from M X (M)!! Logical Shift Left (Same as ASL)!!!! Logical Shift Right C!!! b7 b Move (M) Destination (M) Source H:X (H:X) + (+D, D+)!! IMM EXT SP SP SP SP DD D+ IMD +D AE BE CE DE EE FE 9EEE 9EDE MUL Unsigned multiply X:A (X) (A) NEG opr NEGA NEGX NEG opr,x NEG,X NEG opr,sp Negate (Two s Complement) M (M) = $ (M) A (A) = $ (A) X (X) = $ (X) M (M) = $ (M) M (M) = $ (M)!!!! NOP No Operation None 9D NSA Nibble Swap A A (A[:]:A[7:]) 6 ORA #opr ORA opr ORA opr ORA opr,x ORA opr,x ORA,X ORA opr,sp ORA opr,sp C Inclusive OR A and M A (A) (M)!! b7 b SP IMM EXT SP SP E E6 E E 6E 7E 6 7 9E6 AA BA CA DA EA FA 9EEA 9EDA ii hh ll ee ee ii ii hh ll ee ee PSHA Push A onto Stack Push (A); SP (SP) 87 PSHH Push H onto Stack Push (H); SP (SP) 8B PSHX Push X onto Stack Push (X); SP (SP) 89 PULA Pull A from Stack SP (SP + ); Pull (A) 86 PULH Pull H from Stack SP (SP + ); Pull (H) 8A PULX Pull X from Stack SP (SP + ); Pull (X) 88 Data Sheet Summary MC68HC98QY/QT Family Rev.. Instruction Set Summary

23 MC68HC98QYSM/D Instruction Set Summary Table. Instruction Set Summary (Sheet 6 of 7) Source Form Operation Description Eect on CCR VH I NZC Aress Mode Opcode Operand Cycles ROL opr ROLA ROLX ROL opr,x ROL,X ROL opr,sp Rotate Left through Carry C!!!! b7 b SP E69 ROR opr RORA RORX ROR opr,x ROR,X ROR opr,sp Rotate Right through Carry C!!!! b7 b RSP Reset Stack Pointer SP $FF 9C RTI RTS SBC #opr SBC opr SBC opr SBC opr,x SBC opr,x SBC,X SBC opr,sp SBC opr,sp Return from Interrupt Return from Subroutine SP (SP) + ; Pull (CCR) SP (SP) + ; Pull (A) SP (SP) + ; Pull (X) SP (SP) + ; Pull (PCH) SP (SP) + ; Pull (PCL) SP SP + ; Pull (PCH) SP SP + ; Pull (PCL) Subtract with Carry A (A) (M) (C)!!!! SP E66!!!!!! SEC Set Carry Bit C 99 SEI Set Interrupt Mask I 9B STA opr STA opr STA opr,x STA opr,x STA,X STA opr,sp STA opr,sp Store A in M M (A)!! STHX opr Store H:X in M (M:M + ) (H:X)!! STOP Enable IRQ Pin; Stop Oscillator I ; Stop Oscillator 8E IMM EXT SP SP EXT SP SP A B C D E F 9EE 9ED B7 C7 D7 E7 F7 9EE7 9ED7 ii hh ll ee ee hh ll ee ee STX opr STX opr STX opr,x STX opr,x STX,X STX opr,sp STX opr,sp Store X in M M (X)!! EXT SP SP BF CF DF EF FF 9EEF 9EDF hh ll ee ee SUB #opr SUB opr SUB opr SUB opr,x SUB opr,x SUB,X SUB opr,sp SUB opr,sp Subtract A (A) (M)!!!! IMM EXT SP SP A B C D E F 9EE 9ED ii hh ll ee ee MC68HC98QY/QT Family Rev.. Instruction Set Summary Data Sheet Summary

24 MC68HC98QYSM/D Table. Instruction Set Summary (Sheet 7 of 7) Source Form Operation Description Eect on CCR VH I NZC Aress Mode Opcode Operand Cycles SWI Software Interrupt PC (PC) + ; Push (PCL) SP (SP) ; Push (PCH) SP (SP) ; Push (X) SP (SP) ; Push (A) SP (SP) ; Push (CCR) SP (SP) ; I PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte 8 9 TAP Transfer A to CCR CCR (A)!!!!!! 8 TAX Transfer A to X X (A) 97 TPA Transfer CCR to A A (CCR) 8 TST opr TSTA TSTX TST opr,x TST,X TST opr,sp Test for Negative or Zero (A) $ or (X) $ or (M) $!! TSX Transfer SP to H:X H:X (SP) + 9 TXA Transfer X to A A (X) 9F TXS Transfer H:X to SP (SP) (H:X) 9 A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter Direct aress of operand PCH Program counter high byte rr Direct aress of operand and relative oset of branch instruction PCL Program counter low byte DD Direct to direct aressing mode REL Relative aressing mode Direct aressing mode rel Relative program counter oset byte D+ Direct to indexed with post increment aressing mode rr Relative program counter oset byte ee High and low bytes of oset in indexed, 6-bit oset aressing SP Stack pointer, 8-bit oset aressing mode EXT Extended aressing mode SP Stack pointer 6-bit oset aressing mode Oset byte in indexed, 8-bit oset aressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand aress in extended aressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct destination aressing mode Logical OR IMM Immediate aressing mode Logical EXCLUSIVE OR Inherent aressing mode ( ) Contents of Indexed, no oset aressing mode ( ) Negation (two s complement) + Indexed, no oset, post increment aressing mode # Immediate value +D Indexed with post increment to direct aressing mode «Sign extend Indexed, 8-bit oset aressing mode Loaded with + Indexed, 8-bit oset, post increment aressing mode? If Indexed, 6-bit oset aressing mode : Concatenated with M Memory location! Set or cleared N Negative bit Not aected SP D D D 6D 7D 9E6D Data Sheet Summary MC68HC98QY/QT Family Rev.. Instruction Set Summary

25 MC68HC98QYSM/D Oscillator Module (OSC) Oscillator Module (OSC) The oscillator has these four clock source options available: Internal to External Clock Switching NOTE:. Internal oscillator: An internally generated, fixed frequency clock, trimmable to ± % in steps of approximately.%. This is the default option out of reset.. External oscillator: An external clock that can be driven directly into OSC.. External RC: A built-in oscillator module (RC oscillator) that requires an external R connection only on one pin. The capacitor will be internal to the chip.. External crystal: A built-in oscillator module (XTAL oscillator) that requires an external crystal or ceramic-resonator on two pins. When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following steps:. For External crystal circuits only, OSCOPT[:] = :: To help precharge an external crystal oscillator, set PTA (OSC) as an output and drive high for several cycles. Before writing OSCOPT[:], the crystal will see a sharp falling edge at startup.. Set CONFIG bits OSCOPT[:] according to Table 7. The oscillator module control logic will then set OSC as an external clock input and, if the external crystal option is selected, OSC will also be set as the clock output.. Create a software delay to wait the stabilization time needed for the selected clock source (crystal, resonator, RC) as recommended by the component manufacturer. A good rule of thumb for crystal oscillators is to wait 96 cycles of the crystal frequency, i.e., for a -MHz crystal, wait approximately msec.. After this delay has elapsed, the ECGON bit in the OSC status register (OSCSTAT) should be set by the user software.. After ECGON set is detected, the OSC module checks for oscillator activity by waiting two external clock rising edges. 6. The OSC module than switches to the external clock. Logic provides a glitch free transition. 7. The OSC module sets the ECGST bit in the OSCSTAT register and then stops the internal oscillator. Once transition to the external clock is done, the internal oscillator will only be reactivated with reset. Clock does not switch back to internal if external clock stops. MC68HC98QY/QT Family Rev.. Oscillator Module (OSC) Data Sheet Summary

26 MC68HC98QYSM/D FROM SIM BUSCLKX TO SIM BUSCLKX TO SIM SIMOSCEN XTALCLK MCU PTA/OSC/AD/KBI R B PTA/OSC/AD/KBI FROM SIM SIMOSCEN MCU X R S () C C Note. R S can be zero (shorted) when used with higher-frequency crystals. Refer to crystal manufacturer s data. Figure 7. XTAL Oscillator External Connections EN EXTERNAL RC OSCILLATOR INTCLK RCCLK OSCRCOPT TO SIM BUSCLKX TO SIM BUSCLKX PTA I/O PTA OSCEN PTA/OSC/AD/KBI PTA/OSC/AD/KBI V DD R EXT Figure 8. RC Oscillator External Connections Data Sheet Summary MC68HC98QY/QT Family Rev.. Oscillator Module (OSC)

27 MC68HC98QYSM/D Oscillator Module (OSC) Oscillator Status Register The oscillator status register (OSCSTAT) contains the bits for switching from internal to external clock sources $6 Bit 7 6 Bit R R R R R R ECGON ECGST Reset: R = Reserved Figure 9. Oscillator Status Register (OSCSTAT) Oscillator Trim Register (OSCTRIM) ECGON External Clock Generator On Bit = External clock generator enabled ECGST External Clock Status Bit = An external clock source engaged $8 Bit 7 6 Bit TRIM7 TRIM6 TRIM TRIM TRIM TRIM TRIM7 TRIM Reset: Figure. Oscillator Trim Register (OSCTRIM) TRIM7 TRIM Internal Oscillator Trim Factor Bits These read/write bits change the size of the internal capacitor used by the internal oscillator. By testing the frequency of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine tuned. Increasing (decreasing) this factor by one increases (decreases) the period by approximately.% of the untrimmed period (the period for trim = $8). The trimmed frequency is guaranteed not to vary by more than ±% over the full specified range of temperature and voltage. The reset value is $8 which sets the frequency to. MHz ± % (bus rate). A trim adjustment factor can be programmed into FLASH memory at TRIMLOC ($FFC). During the application initialization routine, this value can be read from TRIMLOC and be stored to OSCTRIM ($8) to fine tune the internal oscillator frequency. MC68HC98QY/QT Family Rev.. Data Sheet Summary Oscillator Module (OSC)

28 MC68HC98QYSM/D Timer Interface Module (TIM) INTERNAL BUS INTERNAL BUS CLOCK TSTOP TRST 6-BIT COUNTER Features of the TIM include the following: PRESCALER 6-BIT COMPARATOR TMODH:TMODL CHANNEL 6-BIT COMPARATOR TCHH:TCHL 6-BIT LATCH CHANNEL 6-BIT COMPARATOR TCHH:TCHL 6-BIT LATCH Two input capture/output compare channels Rising-edge, falling-edge, or any-edge input capture trigger Set, clear, or toggle output compare action Buered and unbuered pulse width modulation (PWM) signal generation Programmable TIM clock input with 7-frequency internal bus clock prescaler selection Free-running or modulo up-count operation Optional toggle of any channel pin on overflow TIM counter stop and reset bits ELSB ELSB MSA MSA PRESCALER SELECT,,, 8, 6,, OR 6 PS PS PS ELSA ELSA CHF MSB CHF TOF TOIE TOGGLE TOV CHMAX CHIE TOV CHMAX CHIE INTERRUPT LOGIC PORT LOGIC INTERRUPT LOGIC PORT LOGIC INTERRUPT LOGIC TCH TCH Figure. TIM Block Diagram Data Sheet Summary MC68HC98QY/QT Family Rev.. Timer Interface Module (TIM)

29 MC68HC98QYSM/D Timer Interface Module (TIM) PWM Initialization TIM Status and Control Register NOTE: Recommended initialization procedure for unbuered or buered PWM signals.. In TSC: a. Stop the TIM counter by setting TSTOP. b. Reset the TIM counter and prescaler by setting TRST.. Write TMODH:TMODL to set the required PWM period.. Write TCHxH:TCHxL to set the required pulse width.. Write TIM channel x status and control register (TSCx) to select the desired function: a. Write : (for unbuered output compare or PWM signals) or : (for buered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 7. b. Write to the toggle-on-overflow bit, TOVx. c. Write : (to clear output on compare) or : (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 7.. Clear TSTOP in the TIM status control register (TSC). $ Bit 7 6 Bit TOF TOIE TSTOP TRST PS PS PS Reset: TOF TIM Overflow Flag Bit TOF is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic to TOF. = TIM counter has reached modulo value TOIE TIM Overflow Interrupt Enable Bit = TIM overflow interrupts enabled TSTOP TIM Stop Bit = TIM counter stopped TRST TIM Reset Bit Figure. TIM Status and Control Register (TSC) Setting this write-only bit resets the TIM counter and the TIM prescaler. TRST is cleared automatically after the TIM counter is reset and always reads as logic. = Prescaler and TIM counter cleared Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $. MC68HC98QY/QT Family Rev.. Data Sheet Summary Timer Interface Module (TIM)

30 MC68HC98QYSM/D PS[:] Prescaler Select Bits Table 6. Prescaler Selection TIM Counter Registers TIM Counter Modulo Registers PS PS PS TIM Clock Source Internal bus clock Internal bus clock Internal bus clock Internal bus clock 8 Internal bus clock 6 Internal bus clock Internal bus clock 6 Reserved The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buer. Subsequent reads of TCNTH do not aect the latched TCNTL value until TCNTL is read. TCNTH $ Bit 7 6 Bit Bit Bit Bit Bit Bit Bit Bit 9 Bit 8 Reset: TCNTL $ Bit 7 6 Bit Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit Reset: Figure. TIM Counter Registers (TCNTH:TCNTL) When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $ at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. TMODH $ Bit 7 6 Bit Bit Bit Bit Bit Bit Bit Bit9 Bit8 Reset: TMODL $ Bit 7 6 Bit Bit7 Bit6 Bit Bit Bit Bit Bit Bit Reset: Figure. TIM Counter Modulo Registers (TMODH:TMODL) Data Sheet Summary MC68HC98QY/QT Family Rev.. Timer Interface Module (TIM)

31 MC68HC98QYSM/D Timer Interface Module (TIM) TIM Channel Status and Control Registers NOTE: TSC $ Bit 7 6 Bit CHF CHIE MSB MSA ELSB ELSA TOV CHMAX Reset: TSC $8 Bit 7 6 Bit CHF CHIE MSA ELSB ELSA TOV CHMAX Reset: CHxF Channel x Flag Bit Figure. TIM Channel Status and Control Registers (TSC, TSC) When channel x is an input capture channel, CHxF is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a logic to CHxF. = Input capture or output compare on channel x CHxIE Channel x Interrupt Enable Bit = Channel x CPU interrupt requests enabled MSxB, MSxA, ELSxB, and ELSxA Table 7. Mode, Edge, and Level Selection MSxB MSxA ELSxB ELSxA Mode Configuration X X Output preset TOVx Toggle-On-Overflow Bit = Channel x pin toggles on TIM counter overflow. Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Input capture Capture on falling edge only Capture on rising or falling edge Toggle output on compare Output compare Clear output on compare or PWM Set output on compare X Buered Toggle output on compare X output Clear output on compare compare or X buered PWM Set output on compare When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. MC68HC98QY/QT Family Rev.. Timer Interface Module (TIM) Data Sheet Summary

32 MC68HC98QYSM/D CHxMAX Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic, setting the CHxMAX bit forces the duty cycle of buered and unbuered PWM signals to %. The CHxMAX bit takes eect in the cycle after it is set or cleared. The output stays at the % duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD TCHx TIM Channel Registers CHxMAX OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 6. CHxMAX Latency OUTPUT COMPARE In input capture mode (MSxB:MSxA = :), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA :), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. TCHH $6 Bit 7 6 Bit Reset: Bit Bit Bit Bit Bit Bit Bit 9 Bit 8 Indeterminate after reset TCHL $7 Bit 7 6 Bit Reset: Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit Indeterminate after reset TCHH $9 Bit 7 6 Bit Reset: Bit Bit Bit Bit Bit Bit Bit 9 Bit 8 Indeterminate after reset TCHL $A Bit 7 6 Bit Reset: Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit Indeterminate after reset Figure 7. TIM Channel Registers (TCHH:L, TCHH:L) Data Sheet Summary MC68HC98QY/QT Family Rev.. Timer Interface Module (TIM)

33 MC68HC98QYSM/D Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) INTERNAL DATA BUS INTERRUPT LOGIC AIEN COCO The ADC is an 8-bit, -channel analog-to-digital converter. The ADC module is only available on the MC68HC98QY, MC68HC98QT, MC68HC98QY, and MC68HC98QT. Features of the ADC module include: CONVERSION COMPLETE BUS CLOCK channels with multiplexed input Linear successive approximation with monotonicity 8-bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock ADC DATA REGISTER ADC ADC CLOCK CLOCK GENERATOR ADIV[:] ADC VOLTAGE IN ADCVIN Figure 8. ADC Block Diagram A/D PIN INPUTS AD[:] CHANNEL SELECT ( OF CHANNELS) CH[:] Conversion Time Conversion Time = 6 ADC Clock Cycles ADC Clock Frequency Number of Bus Cycles = Conversion Time Bus Frequency MC68HC98QY/QT Family Rev.. Analog-to-Digital Converter (ADC) Data Sheet Summary

34 MC68HC98QYSM/D ADC Status and Control Register NOTE: $C Bit 7 6 Bit COCO AIEN ADCO CH CH CH CH CH Reset: Figure 9. ADC Status and Control Register (ADSCR) COCO Conversions Complete Bit When the AIEN bit is a logic, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever ADSCR is written or whenever the ADR is read. When the AIEN bit is a logic (CPU interrupt enabled), COCO will always be logic when read. = Conversion completed (AIEN = ) AIEN ADC Interrupt Enable Bit = ADC interrupt enabled ADCO ADC Continuous Conversion Bit = Continuous ADC conversion = Single ADC conversion CH[:] ADC Channel Select Bits Startup from the ADC power o state requires one conversion cycle to stabilize. Table 8. MUX Channel Select CH CH CH CH CH ADC Channel Input Select AD PTA AD PTA AD PTA AD PTA Unused () Reserved Unused V DDA () V SSA () ADC power o. If any unused channels are selected, the resulting ADC conversion will be unknown.. The voltage levels supplied from internal reference nodes, as specified in the table, are used to verify the operation of the ADC converter both in production test and for user applications. Data Sheet Summary MC68HC98QY/QT Family Rev.. Analog-to-Digital Converter (ADC)

35 MC68HC98QYSM/D Input/Output (I/O) Ports ADC Data Register This register is updated each time an ADC conversion completes. ADC Input Clock Register Input/Output (I/O) Ports Port A NOTE: $E Bit 7 6 Bit Reset: ADIV ADIV ADC Clock Prescaler Bits Port A is an 6-bit special function port that shares all six of its pins with the keyboard interrupt (KBI) module. Each port A pin also has a software configurable pullup device if the corresponding port pin is configured as a general-purpose input port, a KBI input, or the IRQ input. PTA has a fixed pullup device when configured as RST. PTA is input only. AD7 AD6 AD AD AD AD AD AD Indeterminate after reset Figure. ADC Data Register (ADR) $F Bit 7 6 Bit ADIV ADIV ADIV Reset: Figure. ADC Input Clock Register (ADICLK) Table 9. ADC Clock Divide Ratio ADIV ADIV ADIV ADC Clock Rate Bus clock Bus clock Bus clock Bus clock 8 X X Bus clock 6 X = don t care Port A Data Register $ Bit 7 6 Bit Reset: Aitional Functions: R AWUL PTA PTA PTA PTA PTA PTA R = Reserved KBI AD OSC Unaected by reset KBI AD OSC KBI RST Figure. Port A Data Register (PTA) KBI IRQ KBI AD TCH KBI AD TCH MC68HC98QY/QT Family Rev.. Input/Output (I/O) Ports Data Sheet Summary

36 MC68HC98QYSM/D PTA[:] Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A (PTA is input only). Reset has no eect on port A data. AWUL Auto Wakeup Latch Data Bit This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup request signal is generated internally. Data Direction Register A Port A Input Pullup Enable Register $ Bit 7 6 Bit R R DDRA DDRA DDRA DDRA DDRA Reset: R = Reserved Figure. Data Direction Register A (DDRA) DDRA[:] Data Direction Register A Bits = Corresponding port A pin configured as output = Corresponding port A pin configured as input $B Bit 7 6 Bit OSCEN OSCEN Enable Clock Output on OSC Pin PTAPUE PTAPUE PTAPUE PTAPUE PTAPUE PTAPUE Reset: Figure. Port A Input Pullup Enable Register (PTAPUE) This read/write bit configures the OSC pin function as a reference frequency output when internal oscillator or RC oscillator option is selected. This bit has no eect for the XTAL oscillator or external oscillator options. = OSC pin outputs the internal or RC oscillator clock (BUSCLKX) PTAPUE[:] Port A Input Pullup Enable Bits = Corresponding port A pin configured to have internal pull if its DDRA bit is set to and no alternate function such as KBI, IRQ, or timer controls the pin. Data Sheet Summary MC68HC98QY/QT Family Rev.. Input/Output (I/O) Ports