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1 MC68HC08GP32A MC68HC08GP16A Data Sheet M68HC08 Microcontrollers MC68HC08GP32A Rev. 1,0 03/2006 freescale.com

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3 MC68HC08GP32A MC68HC08GP16A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date March, 200 July, 2005 March, 2006 Revision Level N/A Initial release Description Page Number(s) 0.1 Updated to meet Freescale identity guidelines. Throughout Clock Generator Module (CGM) Updated description to remove erroneous information CGM Component Specifications Updated to reflect correct values Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. Freescale Semiconductor, Inc., 200, All rights reserved. Freescale Semiconductor 3

4 Revision History Freescale Semiconductor

5 List of Chapters Chapter 1 General Description Chapter 2 Memory Chapter 3 Analog-to-Digital Converter (ADC) Chapter Clock Generator Module (CGM) Chapter 5 Computer Operating Properly (COP) Chapter 6 Central Processor Unit (CPU) Chapter 7 External Interrupt (IRQ) Chapter 8 Keyboard Interrupt (KBI) Module Chapter 9 Low-Power Modes Chapter 10 Low-Voltage Inhibit (LVI) Chapter 11 Mask Option Registers (MOR2 and MOR1) Chapter 12 Input/Output (I/O) Ports Chapter 13 Resets and Interrupts Chapter 1 Serial Communications Interface (SCI) Module Chapter 15 System Integration Module (SIM) Chapter 16 Serial Peripheral Interface (SPI) Module Chapter 17 Timebase Module (TBM) Chapter 18 Timer Interface Modules (TIM1 and TIM2) Chapter 19 Development Support Chapter 20 Electrical Specifications Chapter 21 Ordering Information and Mechanical Specifications Freescale Semiconductor 5

6 List of Chapters 6 Freescale Semiconductor

7 Table of Contents Chapter 1 General Description 1.1 Introduction Features Standard Features of the MC68HC08GP32A and MC68HC08GP16A Features of the CPU MCU Block Diagram Pin Assignments Pin Functions Power Supply Pins (V DD and V SS ) Oscillator Pins (OSC1 and OSC2) External Reset Pin (RST) External Interrupt Pin (IRQ) CGM Power Supply Pins (V DDA and V SSA ) External Filter Capacitor Pin (CGMXFC) ADC Power Supply/Reference Pins (V DDAD /V REFH and V SSAD /V REFL ) Port A Input/Output (I/O) Pins (PTA7/KBD7 PTA0/KBD0) Port B I/O Pins (PTB7/AD7 PTB0/AD0) Port C I/O Pins (PTC6 PTC0) Port D I/O Pins (PTD7/T2CH1 PTD0/SS) Port E I/O Pins (PTE1/RxD PTE0/TxD) Chapter 2 Memory 2.1 Introduction Unimplemented Memory Locations Reserved Memory Locations Input/Output (I/O) Section Random-Access Memory (RAM) Read-Only Memory (ROM) Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction Features Functional Description ADC Port I/O Pins Voltage Conversion Conversion Time Conversion Accuracy and Precision Freescale Semiconductor 7

8 Table of Contents 3. Interrupts Low-Power Modes Wait Mode Stop Mode I/O Signals ADC Analog Power Pin (V DDAD )/ADC Voltage Reference High Pin (V REFH ) ADC Analog Ground Pin (V SSAD )/ADC Voltage Reference Low Pin (V REFL ) ADC Voltage In (V ADIN ) I/O Registers ADC Status and Control Register ADC Data Register ADC Clock Register Chapter Clock Generator Module (CGM).1 Introduction Features Functional Description Crystal Oscillator Circuit Phase-Locked Loop Circuit (PLL) PLL Circuits Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Programming the PLL Special Programming Exceptions Base Clock Selector Circuit CGM External Connections I/O Signals Crystal Amplifier Input Pin (OSC1) Crystal Amplifier Output Pin (OSC2) External Filter Capacitor Pin (CGMXFC) PLL Analog Power Pin (V DDA ) PLL Analog Ground Pin (V SSA ) Oscillator Enable Signal (SIMOSCEN) Oscillator Stop Mode Enable Bit (OSCSTOPENB) Crystal Output Frequency Signal (CGMXCLK) CGM Base Clock Output (CGMOUT) CGM CPU Interrupt (CGMINT) CGM Registers PLL Control Register PLL Bandwidth Control Register PLL Multiplier Select Register High PLL Multiplier Select Register Low PLL VCO Range Select Register PLL Reference Divider Select Register Interrupts Freescale Semiconductor

9 .7 Special Modes Wait Mode Stop Mode CGM During Break Interrupts Acquisition/Lock Time Specifications Acquisition/Lock Time Definitions Parametric Influences on Reaction Time Choosing a Filter Chapter 5 Computer Operating Properly (COP) 5.1 Introduction Functional Description I/O Signals CGMXCLK STOP Instruction COPCTL Write Power-On Reset Internal Reset COPD (COP Disable) COPRS (COP Rate Select) COP Control Register Interrupts Monitor Mode Low-Power Modes Wait Mode Stop Mode COP Module During Break Mode Chapter 6 Central Processor Unit (CPU) 6.1 Introduction Features CPU Registers Accumulator Index Register Stack Pointer Program Counter Condition Code Register Arithmetic/Logic Unit (ALU) Low-Power Modes Wait Mode Stop Mode CPU During Break Interrupts Instruction Set Summary Opcode Map Freescale Semiconductor 9

10 Table of Contents Chapter 7 External Interrupt (IRQ) 7.1 Introduction Features Functional Description IRQ Pin IRQ Module During Break Interrupts IRQ Status and Control Register Chapter 8 Keyboard Interrupt (KBI) Module 8.1 Introduction Features Functional Description Keyboard Initialization Low-Power Modes Wait Mode Stop Mode Keyboard Module During Break Interrupts I/O Registers Keyboard Status and Control Register Keyboard Interrupt Enable Register Chapter 9 Low-Power Modes 9.1 Introduction Wait Mode Stop Mode Analog-to-Digital Converter (ADC) Wait Mode Stop Mode Break Module (BRK) Wait Mode Stop Mode Central Processor Unit (CPU) Wait Mode Stop Mode Clock Generator Module (CGM) Wait Mode Stop Mode Computer Operating Properly Module (COP) Wait Mode Stop Mode Freescale Semiconductor

11 9.7 External Interrupt Module (IRQ) Wait Mode Stop Mode Keyboard Interrupt Module (KBI) Wait Mode Stop Mode Low-Voltage Inhibit Module (LVI) Wait Mode Stop Mode Serial Communications Interface Module (SCI) Wait Mode Stop Mode Serial Peripheral Interface Module (SPI) Wait Mode Stop Mode Timer Interface Module (TIM1 and TIM2) Wait Mode Stop Mode Timebase Module (TBM) Wait Mode Stop Mode Exiting Wait Mode Exiting Stop Mode Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction Features Functional Description Polled LVI Operation Forced Reset Operation Voltage Hysteresis Protection LVI Trip Selection LVI Status Register LVI Interrupts Low-Power Modes Wait Mode Stop Mode Chapter 11 Mask Option Registers (MOR2 and MOR1) 11.1 Introduction Mask Option Registers Freescale Semiconductor 11

12 Table of Contents Chapter 12 Input/Output (I/O) Ports 12.1 Introduction Port A Port A Data Register Data Direction Register A Port A Input Pullup Enable Register Port B Port B Data Register Data Direction Register B Port C Port C Data Register Data Direction Register C Port C Input Pullup Enable Register Port D Port D Data Register Data Direction Register D Port D Input Pullup Enable Register Port E Port E Data Register Data Direction Register E Chapter 13 Resets and Interrupts 13.1 Introduction Resets Effects External Reset Internal Reset Power-On Reset COP Reset Low-Voltage Inhibit Reset Illegal Opcode Reset Illegal Address Reset SIM Reset Status Register Interrupts Effects Sources SWI Instruction Break Interrupt IRQ Pin CGM TIM TIM SPI SCI KBD0 KBD7 Pins Freescale Semiconductor

13 ADC (Analog-to-Digital Converter) TBM (Timebase Module) Interrupt Status Registers Interrupt Status Register Interrupt Status Register Interrupt Status Register Chapter 1 Serial Communications Interface (SCI) Module 1.1 Introduction Features Pin Name Conventions Functional Description Data Format Transmitter Character Length Character Transmission Break Characters Idle Characters Inversion of Transmitted Output Transmitter Interrupts Receiver Character Length Character Reception Data Sampling Framing Errors Baud Rate Tolerance Receiver Wakeup Receiver Interrupts Error Interrupts Low-Power Modes Wait Mode Stop Mode SCI During Break Module Interrupts I/O Signals PTE0/TxD (Transmit Data) PTE1/RxD (Receive Data) I/O Registers SCI Control Register SCI Control Register SCI Control Register SCI Status Register SCI Status Register SCI Data Register SCI Baud Rate Register Freescale Semiconductor 13

14 Table of Contents Chapter 15 System Integration Module (SIM) 15.1 Introduction SIM Bus Clock Control and Generation Bus Timing Clock Startup from POR or LVI Reset Clocks in Stop Mode and Wait Mode Reset and System Initialization External Pin Reset Active Resets from Internal Sources Power-On Reset Computer Operating Properly (COP) Reset Illegal Opcode Reset Illegal Address Reset Low-Voltage Inhibit (LVI) Reset SIM Counter SIM Counter During Power-On Reset SIM Counter During Stop Mode Recovery SIM Counter and Reset States Exception Control Interrupts Hardware Interrupts SWI Instruction Interrupt Status Registers Reset Break Interrupts Status Flag Protection in Break Mode Low-Power Modes Wait Mode Stop Mode SIM Registers SIM Break Status Register SIM Reset Status Register SIM Break Flag Control Register Chapter 16 Serial Peripheral Interface (SPI) Module 16.1 Introduction Features Functional Description Master Mode Slave Mode Transmission Formats Clock Phase and Polarity Controls Transmission Format When CPHA = Transmission Format When CPHA = Transmission Initiation Latency Freescale Semiconductor

15 16.5 Queuing Transmission Data Error Conditions Overflow Error Mode Fault Error Interrupts Resetting the SPI Low-Power Modes Wait Mode Stop Mode SPI During Break Interrupts I/O Signals MISO (Master In/Slave Out) MOSI (Master Out/Slave In) SPSCK (Serial Clock) SS (Slave Select) I/O Registers SPI Control Register SPI Status and Control Register SPI Data Register Chapter 17 Timebase Module (TBM) 17.1 Introduction Features Functional Description Interrupts TBM Interrupt Rate Low-Power Modes Wait Mode Stop Mode Timebase Control Register Chapter 18 Timer Interface Modules (TIM1 and TIM2) 18.1 Introduction Features Pin Name Conventions Functional Description TIM Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Buffered Output Compare Pulse Width Modulation (PWM) Unbuffered PWM Signal Generation Buffered PWM Signal Generation PWM Initialization Freescale Semiconductor 15

16 Table of Contents 18.5 Interrupts Low-Power Modes Wait Mode Stop Mode TIM During Break Interrupts I/O Signals I/O Registers TIM Status and Control Register TIM Counter Registers TIM Counter Modulo Registers TIM Channel Status and Control Registers TIM Channel Registers Chapter 19 Development Support 19.1 Introduction Break Module (BRK) Functional Description Flag Protection During Break Interrupts TIM During Break Interrupts COP During Break Interrupts Break Module Registers Break Status and Control Register Break Address Registers Break Status Register Break Flag Control Register Low-Power Modes Monitor Module (MON) Functional Description Monitor Mode Entry Monitor Vectors Data Format Break Signal Commands Security Baud Rate Chapter 20 Electrical Specifications 20.1 Introduction Absolute Maximum Ratings Functional Operating Range Thermal Characteristics V DC Electrical Characteristics V DC Electrical Characteristics V Control Timing Freescale Semiconductor

17 V Control Timing Output High-Voltage Characteristics Output Low-Voltage Characteristics Typical Supply Currents ADC Characteristics V SPI Characteristics V SPI Characteristics Timer Interface Module Characteristics Clock Generation Module Characteristics CGM Component Specifications CGM Electrical Specifications Memory Characteristics Chapter 21 Ordering Information and Mechanical Specifications 21.1 Introduction MC Order Numbers Freescale Semiconductor 17

18 Table of Contents 18 Freescale Semiconductor

19 Chapter 1 General Description 1.1 Introduction The MC68HC08GP32A and MC68HC08GP16A are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.2 Features For convenience, features have been organized to reflect: Standard features of the MC68HC08GP32A and MC68HC08GP16A Features of the CPU Standard Features of the MC68HC08GP32A and MC68HC08GP16A High-performance M68HC08 architecture optimized for C-compilers Fully upward-compatible object code with M6805, M16805, and M68HC05 Families 8-MHz internal bus frequency System protection features: Optional computer operating properly (COP) reset Low-voltage detection with optional reset and selectable trip points for 3.0-V and 5.0-V operation Illegal opcode detection with reset Illegal address detection with reset Low-power design; fully static with stop and wait modes Standard low-power modes of operation: Wait mode Stop mode Master reset pin and power-on reset (POR) On-chip read-only memory (ROM) MC68HC08GP32A 32,256 bytes MC68HC08GP16A 15,872 bytes 512 bytes of on-chip random-access memory (RAM) Serial peripheral interface module (SPI) Serial communications interface module (SCI) Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and PWM capability on each channel Freescale Semiconductor 19

20 General Description 8-channel, 8-bit successive approximation analog-to-digital converter (ADC) BREAK module (BRK) to allow single breakpoint setting during in-circuit debugging Internal pullups on IRQ and RST to reduce customer system cost Clock generator module with on-chip 32-kHz crystal compatible PLL (phase-lock loop) Up to 33 general-purpose input/output (I/O) pins, including: 26 shared-function I/O pins Five or seven dedicated I/O pins, depending on package choice Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis. During output mode, pullups are disengaged. High current 10-mA sink/10-ma source capability on all port pins Higher current 15-mA sink/source capability on PTC0 PTC Timebase module with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source during stop mode for periodic wakeup from stop using an external 32-kHz crystal 8-bit keyboard wakeup port 5-mA maximum current injection on all port pins to maintain input protection Available packages: 2-pin shrink dual-in-line package (SDIP) and -pin quad flat pack (QFP) Specific features of the 2-pin SDIP Port C is only 5 bits: PTC0 PTC Specific features of the -pin QFP Port C is 7 bits: PTC0 PTC Features of the CPU08 Features of the CPU08 include: Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Efficient C language support 1. MCU Block Diagram Figure 1-1 shows the structure of the MC68HC08GP32A and MC68HC08GP16A. 20 Freescale Semiconductor

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