Test Circuit for Vectorless Open Lead Detection of CMOS ICs

Size: px

Start display at page:

Download "Test Circuit for Vectorless Open Lead Detection of CMOS ICs"

Brittney Tamsyn Quinn
10 years ago
Views:

1 Test Circuit for Vectorless Open Lead Detection of CMOS ICs M.Hashizume ( ), M.Ichimiya ( ), A.Ono ( ), H.Yotsuyanagi ( ) :The Univ. of Tokushima, JAPAN :Takuma National College of Technology, JAPAN Slide 1

2 Outline 1. Background 2. Our targeted problems: =open lead detection in CMOS logic circuits 3. Our supply current test method 4. Our test circuit 5. Feasibility check by experiments 6. Conclusion Slide 2

3 Background It is demanded to develop electronic equipments of small size. (ex.)mobile phones, notebooks, PDAs Many logic circuits are implemented with fine-pitch ICs and a PCB of fine line layout. solder bridging pattern short peeling-off pattern open lead Defects occur more frequently in soldering process. Targeted defect Slide 3

fine-pitch ICs and a PCB of fine line layout.

4 Conv. Tests for Open Leads Test based on image processing techniques [Limitation] Geometrically good connection can not always assure electrically good connection. Logical test (ex.) boundary scan etc. Electrical test (ex.) in-circuit test etc. Slide 4

always assure electrically good connection. Logical test (ex.

5 Difficulty of Logical Test [Measured characteristic parameter] Voltage of leads and/or interconnection lines [Difficulty] Behaviors generated by open lead can not be estimated precisely and controlled. a open b H L Which logic level? modeling When it will be propagated? a R VDD C2 b C1 R=?,C1=?,C2=? vb can not be controlled. Slide 5

be estimated precisely and controlled. a open b H L Which logic level?

6 Electrical Tests for Open Leads Measured characteristic parameter: Resistance between lead and pad(hioki) Capacitance between lead to pad (Teradyne,HP) DC current through protection or parasitic diode (Teradyne, Hioki) Induced AC voltage M v? at lead(teradyne) M I? M R?, Magnetic field C? Difficulty: low resolution PCB GND lead We proposed an electrical test method.[icep01] Slide 6

parasitic diode (Teradyne, Hioki) Induced AC voltage M v? at lead(teradyne) M I? M R?

7 Our Test Method Proposed in ICEP 01 Test based on supply current flowing when time-varying electric field is provided from the outside of CMOS ICs Test vector idd(t) VDD electrodes CMOS logic IC Electric Field ve(t) If idd(t) Ith, CUT is determined as having open leads. Slide 7

of CMOS ICs Test vector idd(t) VDD electrodes CMOS logic IC Electric

8 Property Used in Our Test If CMOS IC to be tested is defect-free, IDD=0 If Vi1<Vi<Vi2, supply current flows in CMOS ICs. nmos:off pmos:off VDD IDD Vo Vo IDD IDD Vi Vo (a)measurement Circuit Vi1 Vth Vi Vi2 (b)dc characteristics Slide 8

9 Principle of Open Lead Detection nmos:off pmos:off VDD H a b L ve(t) Electric Field Vo Vo IDD IDD H VDD a L Rf C2 b C1 RE idd(t) ve(t) pmos:off vb(t) nmos:off Vi2 Vi1 idd(t) Ith IDDQ 0 Vi1 Vth Vi2 Vi VDD t t Slide 9

10 Test Stimuli for Our Test Method test input vector: [IEICE Trans.2003] time-varying electric field: v E (t) depends on package configurations of targeted ICs and faulty position. v E (t) may be larger than 100V. IC can be destroyed. VDD idd(t) Test vector electrode electric field ve(t) electrode Slide 10

of targeted ICs and faulty position. v E (t) may be larger than 100V.

11 Our Test Method Proposed in EBTW 06 Test method: [1]Contact a test probe to the top of a targeted IC lead [2]If i DD (t) I th, it is concluded as faulty. Feature: Open leads will be detected with AC signal of smaller amplitude supplied. v s >> v TS V DD /2 Test vectors should be provided. electrode idd(t) IC#1 IC#2 vs(t) electrode VDD lead open (a) Test method in ICEP 01 v TS CTS IC#1 RTS v TS V DD /2 Test Stimulus Generator test probe IC#2 lead open (b) Test method in EBT 06 VDD idd(t) Slide 11

v s >> v TS V DD /2 Test vectors should be provided.

12 Our New Approach Our new targeted tests: Tests in subcontract factories Detailed information required for test generation are not provided from ordering manufactures. Test vector generation may not be able to be performed. Soldering process should be optimized for each kinds of circuits. [Requirements] a powerful tester test vectors and/or test generation for locating open leads Development of vectorless test method Slide 12

Test vector generation may not be able to be performed.

13 New Test Method and The Test Circuit Test based on supply current of our test circuit Test process: [1]Attach a test probe to a targeted input lead [2]Provide AC signal [3]Measure i DDT (t) [4]If Eq.(1) is satisfied, an open occurs at the targeted input lead. i DDT (t) I th (1) Measured supply current VDD idd(t) (rms)open at an output lead is detected as open at an input lead. Slide 13

(t) [4]If Eq.(1) is satisfied, an open occurs at the targeted input lead.

14 Principle of Open Detection When an open occurs at an input lead, v INV (t) will depend on v s (t) regardless of logic value of b When V i1 <v INV (t)<v i2, elevated i DD (t) will flow. (a)test of open lead (b)i DDT (t) waveforms Slide 14

value of b When V i1 <v INV (t)<v i2, elevated i DD (t)

15 Tests of Defect-free Circuits v INV (t) depends on output voltage from IC#i-1. i DDT (t) is almost zero. (a)when L is outputted (b)when H is outputted Slide 15

16 Good Points of Our New Test Method High resolution Robust test Opens will be detected by low pressure probing. Test vector generation is not needed. Simple test circuit Development of low price testers DUT (a)test circuit (b)attachment of test probe (c)equivalent circuit Slide 16

17 Test Circuit for Detecting Opens Purpose: detect more than one lead simultaneously (a)test circuit for locating open (b)test circuit for detecting open Slide 17

18 Necessity of R T When opens do not occur at targeted leads, elevated current may flow and the CUT may be destroyed. R T s makes this current small. Slide 18

19 Experimental Evaluation Purpose: Feasibility of our tests with our test circuit 1k 100k (b)test Probe used (a)experimental Circuit (c)setting up Slide 19

20 i DDT Waveforms Measured CK iddt(t) [ma] CK iddt(t) [ma] V SD vs(t) 1.75 [V] V SD vs(t) 0 [V] Vpp 1KHz t [ms] (a)defect-free circuit t [ms] (b)defective circuit i DDT (t) of about 1mA flows in the faulty circuit. The open lead is detected. The elevated current appears when CK=H and CK=L. Test vector generation is not needed. ( Open leads in a LSI of QFP type are detected like in SSIs. ) Slide 20

0 t [ms] (a)defect-free circuit 0 0.5 1.0 1.5 2.

21 Test Speed?IDD[mA] RT=30k RT=3M RT=10M RT=1M fs[khz] where?idd=max(i DDT (t)) Test speed depends on R T. RT=300k RT=100k The open lead is detected with v s (t) of 200kHz and R T of 100kO. = Targeted leads are tested per 5µsec. Slide 21

22 Conclusion A new test circuit for detecting open leads of CMOS ICs [features] Open lead detection with small AC voltage supplied Simple test circuit Vectorless test method Robust test Evaluation by experiments Targeted faults: an open lead in DIP ICs, LSIs of QFP package Open leads are detected per 5µsec with our test circuit Development of test probes Examination of test speed Future works Slide 22

ICS379. Quad PLL with VCXO Quick Turn Clock. Description. Features. Block Diagram

ICS379. Quad PLL with VCXO Quick Turn Clock. Description. Features. Block Diagram Quad PLL with VCXO Quick Turn Clock Description The ICS379 QTClock TM generates up to 9 high quality, high frequency clock outputs including a reference from a low frequency pullable crystal. It is designed