Validation of Quasi-Analytical and Statistical Simulation Techniques for Multi-Gigabit Interconnect Channels

Transcription

1 DesignCon 2010 Validation of Quasi-Analytical and Statistical Simulation Techniques for Multi-Gigabit Interconnect Channels Chad Morgan, Tyco Electronics

2 Abstract Because today s high-speed, high-density backplane and I/O interconnects are pushing speeds well beyond 10 Gbps, accurate simulation of such systems requires the inclusion of long bit patterns, jitter, equalization, and crosstalk. To include these criteria and increase simulation speed, digital designers are migrating from traditional SPICE and convolution simulations to faster quasi-analytical or statistical simulations when possible. This paper will examine correlation between public-domain tools, EDA vendor tools, and test data using various highspeed interconnects as case studies. The paper will summarize how well simulation tools optimize equalization and predict system performance to low probability levels. Author Biography Chad Morgan earned his degree in Electrical Engineering from the Pennsylvania State University, University Park, in For the past 14 years, he has worked in the Circuits & Design group of Tyco Electronics as a signal integrity engineer, specializing in the analysis & design of high-speed, high-density components. Currently, he is a Principal Engineer at Tyco Electronics, where he focuses on high-frequency measurement & characterization of components & materials, full-wave electromagnetic modeling of high-speed interconnects, and the simulation of digital systems. Mr. Morgan's responsibilities at Tyco Electronics include numerous research activities, and he has presented multiple papers at both DesignCon and the International Microwave Symposium. Publications include: A Signal Integrity Comparison of 25 Gbps Backplane Systems Using Varying High- Density Connector Performance Levels, DesignCon09, Track 7-TA4. Solutions for Causal Modeling and a Technique for Measuring Causal, Broadband Dielectric Properties, DesignCon08, Track 5-TA4. The Need for Impulse Response Models and an Accurate Method for Impulse Generation from Band-Limited S-Parameters, DesignCon08, Track 7-WA1. Transition to Surface-Mount: An Analysis of Signal Integrity Improvement versus Manufacturing Concerns in Multi-Gigabit Systems Using High-Density Connectors, DesignCon05 TecForum. Obtaining Accurate Device-Only S-Parameter Data to GHz Using In-Fixture Measurement Techniques, DesignCon04, Track 7-TP1. The Impact of PWB Construction on High-Speed Signals, DesignCon99, Track H412. 2

3 Introduction In the past, parallel bus and serial digital systems ran at slow enough speeds such that their electrical response was only a few bits long. Also enough channel bandwidth was available at these speeds to utilize encoding schemes, such as 8b/10b encoding. As a result, simulation tools could easily analyze the worst-case performance of a system using only a short pseudo-random bit sequence (PRBS); typically a 128-bit PRBS 2 7 sequence. With such a short bit sequence and without the requirement to simulate jitter or complex digital equalization, traditional tools such as SPICE or transient convolution were capable of adequately predicting system performance. Today s high-speed, high-density backplane and I/O interconnects need to be designed to run at speeds well beyond 10 Gbps. At these speeds, the signal s bit width is much shorter than the channel response, such that inter-symbol interference (ISI) must be considered from many bits away. Further, most interconnects have little bandwidth to spare, so designers try to avoid the overhead associated with signal encoding. As a result, simulation tools are now required that can simulate very long PRBS patterns or even random data. These tools must also be able to analyze jitter, as even small amounts of jitter now impact narrow bit-widths dramatically. Finally, these tools must be able to quickly analyze and optimize complex digital equalization schemes, as they are mandatory in high-speed systems. To be able to simulate long bit patterns, including jitter and equalization, digital designers can no longer use traditional SPICE or transient convolution simulators, as they are too slow. Rather, designers are migrating to two types of faster simulation techniques that are applicable for linear, time-invariant (LTI) systems: quasi-analytical and statistical simulation. In both techniques, traditional simulation methods are still used to predict the system s step or pulse response. However, in order to predict the behavior of long bit sequences, quasi-analytical and statistical methods then take advantage of superposition principles. Specifically, quasi-analytical analysis time-shifts and adds pulse responses in order to simulate very long PRBS patterns quickly. Statistical analysis, on the other hand, simulates a random bit pattern (worst-case) by using only the statistics of baud-spaced cursor voltages to predict the system eye pattern. The purpose of this paper is not only to compare quasi-analytical and statistical simulation results between available tools, but more importantly to validate quasi-analytical and statistical simulation results by examining traditional simulation results and measured data. For LTI systems, theory says that quasi-analytical and statistical simulation results should correlate well to test data and be much faster to simulate than traditional SPICE or transient convolution techniques. Also, quasi-analytical and statistical simulation results should yield the same results for very long bit patterns. Therefore, since statistical simulation techniques are faster, quasianalytical techniques should only be necessary when one wants to simulate the effect of specific, shorter-length bit sequences. In order to validate quasi-analytical and statistical simulation results, multiple backplane channels have been measured. Specifically, short (10 ) and long (30 ) backplane channels using the Tyco Electronics Z-PACK HM-Zd connector have been measured. Also, short (11.5 ) and long (27 ) backplane channels using the Tyco Electronics STRADA Whisper connector have been measured. Z-PACK HM-Zd channels and STRADA Whisper channels were chosen in order to provide a range of data in terms of the levels of reflections and crosstalk. The details of 3

4 the actual channels are not necessarily important for the sake of validation. It is only important to know that, for each channel, S-parameters were directly measured for the channel (including cables) and then used in the channel simulators. This simulated time data is then compared to direct time-domain measurements of the exact same system. This is shown in Figure 1. Figure 1: Backplane Channel Setup for S-parameters (20 GHz) & Time-Domain Data (Includes Cables) Data from the described channels is used in accomplishing three primary goals. The first goal is ensure that simulation results from faster quasi-analytical and statistical simulators not only correlate to one another but also to slower traditional simulations, such as transient convolution. The second goal is then to validate simulation results against directly measured time-domain results, where possible. Finally, the third goal of the paper is to highlight any test equipment and simulator requirements that need to be addressed. Besides validating the accuracy and speed of quasi-analytical and statistical simulation techniques, the paper also examines how various tools handle jitter, digital equalization, and crosstalk. There is currently some debate on how to quickly and accurately simulate jitter, and there is also some debate on the optimal way to find coefficient values for feed-forward equalization (FFE) and decision-feedback equalization (DFE). This paper measures both jitter and equalization for the constructed channels and compares the results to those predicted by several quasi-analytical and statistical simulation tools. The paper also attempts to compare measured synchronous and asynchronous crosstalk to the simulated results from various tools. Note that transient convolution and quasi-analytical (bit-by-bit) analysis are done throughout the paper in Agilent Advanced Design System (ADS) 2009, Update 1. Statistical simulations are done in both the ADS 2009, Update 1 channel simulator and also in Stateye All timedomain measured data is taken using a BERTScope Si 25000C 25 Gbps generator and BERT. Validation Results In this section of the paper, data and conclusions will be given showing inter-tool correlation and agreement between simulated and measured results. In order to isolate various capabilities of the newer simulators, throughput, crosstalk, equalization, and jitter are all examined individually. Throughput-Only The first step in ensuring that quasi-analytical and statistical simulators are accurate is to make sure that the tools agree with each other and with traditional simulation results. In order to verify that this is the case, measured S-parameters from the STRADA Whisper 27 system were run at 6.25 Gbps through various simulators without the presence of crosstalk, equalization, or jitter. The results are shown in Table 1. 4

5 Table 1: Correlation of Time-Domain Simulators (STRADA Whisper Gbps) As Table 1 shows, there is perfect agreement between transient convolution and quasi-analytical bit-by-bit simulations for a PRBS 2 15 bit pattern of 32,678 bits. In this case, the quasi-analytical simulation was over 3 times faster than transient convolution, though this speed increase can be far more dramatic for longer bit patterns. For example, the PRBS 2 23 pattern listed in Table 1 consisted of over 8 million bits. This simulation ran in the quasi-analytical simulator in under an hour but was not practical to run in transient convolution as it would have taken at least several days. It is clear that quasi-analytical simulations agree precisely with traditional simulations and run much more quickly. To go one step further, a worst-case bit pattern was then emulated by running a statistical simulation. Not only was the result slightly worse than the 2 23 result, as expected, but the simulation ran in only 5 seconds! It is clear that the linear time-invariant (LTI) superposition principles assumed by quasi-analytical and statistical simulators are valid for passive backplane channels. Correlation is very good and the new simulators run very quickly. The next goal is validate simulation results against measured data. As explained previously, simulations are completed by measuring the S-parameters (to 20 GHz) of a system with its cables and then running that data through a channel simulator to create time-domain results. These simulated results can then be compared to measurements of the identical system at the identical bit rate. Note that all simulations for the remainder of the paper use statistical methods to emulate a worst-case bit pattern. As a result, all measurements drive a bit pattern to create a high-degree of inter-symbol interference (ISI). Before completing simulation and measurement comparisons, there is one last task that must be completed. Specifically, it is critical to ensure that simulation driver and receiver characteristics match those of the measurement equipment. For example, one must be sure that the simulated driver has an edge rate and inherent jitter that matches the test equipment itself. Further, simulations must account for real-life driver and receiver parasitics that cause extra system reflections. To derive simulation driver and receiver characteristics, several steps were taken. First, short, high-quality cables were used to connect the generator directly to the receiver. Eye patterns were then measured at multiple speeds. S-parameters from the short cables were then placed in the channel simulator, and data patterns were driven at the same speeds as the measurements. Finally, edge rate, jitter, and parasitic values were optimized until the best match possible was obtained between measured and simulated results. Figure 2 shows measured eye patterns at various speeds overlaid with simulated random eye patterns run through the short cables. Ultimately, a good match between simulated and measured edge rate and jitter was obtained. However, it was far more difficult to emulate the driver and receiver parasitics. For example, it is clear, especially in the 15 Gbps waveform, that there is a large irregularity in the measured transmitter output waveform. 5

6 Rear Yellow/Red Data from BERTScope, Front Blue/Green Data from ADS Statistical Sim 10 Gbps 15 Gbps 20 Gbps 25 Gbps ADS Driver = 20ps (0-100%) with RJ rms =1ps Stateye Driver = Single-pole 20 GHz w/ RJ rms =1ps Tx/Rx Parasitics = 39 Ohm End Section Figure 2: Simulation/Measurement Agreement through Short Cables & Simulation Driver/Receiver Settings As Figure 2 shows, good correlation between inherent equipment jitter and simulated jitter was obtained by using RJ rms = 1 ps in the simulated driver. Also, good correlation between measured and simulated edge rate was obtained by using a 20 ps (0-100%) edge in the ADS statistical simulator and by using a low-pass filter with a single pole at 20 GHz in Stateye. Through many attempts, test equipment driver and receiver parasitics were emulated using a short lowimpedance model at each side of the channel. However, perfect correlation proved difficult. Figure 3 shows a comparison of low-probability contours for one of the better correlation results, which occurred at 25 Gbps. ADS Contours (Blue) Stateye Contours Figure 3: BER Contour Correlation at 25 Gbps through Short Cables Once the simulated driver and receiver have been optimized to emulate the test equipment, comparisons between simulations and measurements can be made. Figure 4 begins by comparing throughput-only data at 6.25 Gbps and 12.5 Gbps for the short, high-quality STRADA Whisper 11.5 channel (with cables). Note that comparisons must be made at lower bit speeds because eye patterns are not open without equalization at speeds above 12.5 Gbps. In Figure 4, data directly measured at 6.25 Gbps and 12.5 Gbps from the BERTScope is shown on the left. The middle column then shows statistically simulated ADS data directly overlaid on the test data. Finally, the right column shows simulation data from Stateye directly overlaid on the test data. All eye height and eye width data listed in Figure 4 is from the BER = probability contour. This contour is shown in yellow with the measured data, red with the ADS data, and as the innermost contour for the Stateye data. 6

7 Examining the high probability data displayed in Figure 4, it is clear that measured and simulated results agree extremely well. However, there are some notable differences between various data sources at the BER = level. For example, at 6.25 Gbps ADS and Stateye agree fairly well for eye height / width (ADS = 40% / 74%, Stateye = 43% / 76%). However, measured data is significantly more closed with height / width being 33% / 63%. It is likely that there are two reasons for the discrepancy. First, as seen with previous data from the short cables, it was difficult to emulate driver/receiver parasitics perfectly, so simulated results are likely to be more optimistic than measured results. Second, it is likely that there is some degree of amplitude noise (i.e. additive white Gaussian noise - AWGN) in the measured data that cannot be emulated in simulation. The 12.5 Gbps simulations in Figure 4 show similar results, with measured data being more closed at BER = than simulated results. This trend at low probability levels was consistent across numerous channels that were measured and simulated. BERTScope ADS Overlay (Red Contour) Stateye Overlay 6.25 Gbps Height: 33% Width: 63% Height: 40% Width: 74% Height: 43% Width: 76% 12.5 Gbps Height: Closed Width: Closed Height: 6% Width: 28% Height: 13% Width: 40% Figure 4: Simulation/Measurement Agreement for 11.5 STRADA Whisper System As another example, Figure 5 shows measured and simulated data for the longer 27 STRADA Whisper channel (with cables) at Gbps and 6.25 Gbps. As with the shorter channel, ADS and Stateye values agree well, while measured data shows a more closed eye at BER = BERTScope ADS Overlay (Red Contour) Stateye Overlay Gbps Height: 37% Width: 66% Height: 42% Width: 76% Height: 43% Width: 77% 6.25 Gbps Height: 4% Width: 21% Height: 7% Width: 30% Height: 9% Width: 32% Figure 5: Simulation/Measurement Agreement for 27 STRADA Whisper System 7

8 Although ADS statistical simulations and Stateye statistical simulations agree fairly well in Figures 4 and 5, it is necessary to explain why there is any difference at all. The first reason is that ADS simulations are run with a 20 ps (0-100%) piece-wise linear (PWL) edge while Stateye simulations are run with a 7.6 ps PWL edge passed through a low-pass filter. These two input edge rates are both close to 20 ps, but not exactly the same; this results in a minor difference in ADS and Stateye simulated results. The second, and much more important, reason for the difference in results stems from how the simulators handle band-limited S-parameter data. In Stateye 4.2.3, S-parameter data that is band-limited at 20 GHz is simply truncated and zeropadded to 66 GHz. In the ADS channel simulator, a sophisticated causal spectrum extrapolation technique [1] is used to estimate required data at higher frequencies. To find out which technique for handling band-limited S-parameters is more accurate, a simple experiment was carried out. As Figure 6 shows, a short transmission line was simulated to 50 GHz. A statistical channel simulation was then run in both ADS and Stateye at 25 Gbps using the 50 GHz data to get a true result. S-parameter data was then truncated at 20 GHz and re-run through the two tools to see the error introduced by band-limited data in each tool. The results are shown in Table 2. Figure 6: Simple Low-loss Circuit Used to Examine Channel Simulator Handling of Band-limited Data Table 2: Comparison Data for ADS and Stateye Handling of Band-limited Data It should be evident from Table 2 that ADS is more effective in handling band-limited data than Stateye. On average, ADS 20 GHz eye height error is 1.25% while Stateye eye height error is 4.80%. It is important to note that, even though ADS is more effective, there is some degree of error caused by band-limited data in all tools. Therefore, though S-parameter data is most often taken to 20 GHz, it will become increasingly important in the future to consider ways to get data to higher frequencies such as 50 GHz. As systems get shorter, less lossy, and use more equalization, the error introduced from band-limited S-parameters will grow. This is why, for example, the error between Stateye and ADS is higher for the short channel of Figure 4 than it is for the longer channel of Figure 5. 8

9 Crosstalk When simulating crosstalk in high-speed channels, it is important to understand how crosstalk is implemented in the tool being used. There are many options for calculating crosstalk, including whether crosstalk is calculated directly or statistically, whether crosstalk is correlated or uncorrelated to a specific bit sequence, and finally whether the crosstalk is synchronous (fixed) or asynchronous (random) to the throughput bit pattern. Within the ADS channel simulator, all crosstalk options are available to the user. To determine the type of crosstalk calculated in Stateye, an experiment was run, as shown in Figure 7. Figure 7: High Crosstalk Example for Examining ADS and Stateye Crosstalk Figure 7 shows a short channel where crosstalk magnitude is high and long in duration. This allows one to easily see the crosstalk in a channel simulation. The data from the circuit in Figure 7 was run in the ADS statistical channel simulator in both synchronous and asynchronous mode at a very low speed (1 Gbps) in order to visualize the crosstalk. The same data was then run in Stateye, which gives no crosstalk options, to determine the type of crosstalk calculated. The results are shown in Figure 8. Note that all crosstalk data is inherently uncorrelated to the throughput data when calculated in ADS statistical mode or Stateye. ADS Synchronous ADS Asynchronous Stateye Figure 8: Crosstalk Example Results at 1 Gbps (Eyes all 79.7% vertical opening) It should be clear from Figure 8 that Stateye inherently calculates synchronous (fixed) crosstalk. At 1 Gbps, Stateye lists eye height at 79.7%, which agrees with both the ADS synchronous and asynchronous results. As it turns out, the peak magnitude of synchronous and asynchronous crosstalk is the same. The difference is that asynchronous crosstalk can occur anywhere on the eye unit interval, and it has a different statistical distribution than synchronous crosstalk. 9

10 Interestingly, ADS and Stateye agree at lower bit rates, but their results diverge for the example shown in Figure 7 at higher bit rates. Table 3 shows this result. Table 3: Crosstalk Example Results at Increasing Bit Speeds The natural question that arises is whether ADS or Stateye calculates the correct result. Further study showed that ADS crosstalk results matched transient simulation results, as well as results from other EDA statistical simulators, and test data (as will be shown). As a result, it is clear that there are two problems with Stateye simulations that consider crosstalk. First, at bit rates above 10 Gbps, it appears that Stateye estimates crosstalk too low and provides eye openings that are too optimistic. Second, Stateye only provides synchronous crosstalk, which leaves the possibility that numerous aggressor peak crosstalk magnitudes may not line up to give true worst-case eye closure. Remaining crosstalk examples focus on ADS statistical calculation of crosstalk, as it appears to be correct. As an example of synchronous crosstalk correlation between the ADS statistical simulator and test data, consider in-row near- and far-end crosstalk at 6.25 Gbps from the Z-PACK HM-Zd short (10 ) system, as shown in Figure 9. The agreement between simulated and measured data is excellent. Both ADS and measurement show peak-to-peak near-end crosstalk of 5%, and both ADS and measurement show peak-to-peak far-end crosstalk of 4%. Measured NEXT ADS NEXT ADS Overlaid on Test Data Both 5%p-p NEXT Measured FEXT ADS FEXT ADS Overlaid on Test Data Both 4%p-p FEXT Figure 9: Simulation/Measurement Synchronous Crosstalk Correlation at 6.25 Gbps 10

11 As an example of asynchronous crosstalk correlation between the ADS statistical simulator and test data, consider in-row near- and far-end crosstalk at 6.25 Gbps from the Z-PACK HM-Zd short (10 ) system, as shown in Figure 10. The agreement between simulated and measured data is excellent. Both ADS and measurement show peak-to-peak near-end crosstalk of 5%, and both ADS and measurement show peak-to-peak far-end crosstalk of 4%. Note that, as mentioned previously, the peak value of asynchronous crosstalk matches that of synchronous crosstalk, but it occurs at all times across the unit interval (with some statistical relief at each time). Measured NEXT ADS NEXT ADS Overlaid on Test Data Both 5%p-p NEXT Measured FEXT ADS FEXT ADS Overlaid on Test Data Both 4%p-p FEXT Figure 10: Simulation/Measurement Asynchronous Crosstalk Correlation at 6.25 Gbps As speeds rise toward 25 Gbps, agreement between measured data and ADS-predicted data remains acceptable. As Table 4 shows, values are slightly different between simulation and measurement at higher bit rates, which is likely caused by simulator handling of band-limited data. Even so, results are within 1% (peak-to-peak). Table 4: Peak-to-peak Asynchronous Noise Magnitude at 25 Gbps Equalization There are two steps in making sure that a channel simulator is applying digital equalization correctly. The first is to validate that, for a given set of feed-forward equalizer (FFE) or decision-feedback equalizer (DFE) tap values, simulation and measurement agree. The second step is to verify that automatic tap calculation completed by the simulator yields the most open eye pattern possible. In order to validate digital equalization in the ADS channel simulator and Stateye, the Digital Pre-Emphasis Processor (DPP) from Synthesys Research was used to implement feed-forward 11

12 equalization. This add-on box to the BERTScope can physically implement up to 4 baud-spaced taps to 12.5 Gbps. Unfortunately, adequate hardware for decision-feedback equalization was not available in order to complete simulator DFE validation. Moving forward with FFE validation, a 3-tap FFE was implemented in the ADS channel simulator s driver. Note that the three tap values were somewhat arbitrary. The driver was then simulated running short test cables at 6.25 Gbps. The DPP was then used, with the same 3 tap values, to run 6.25 Gbps data through the same test cables. Results are shown in Figure 11. Figure 11: Measured (white) and Simulated (blue) De-emphasized Eye Pattern at 6.25 Gbps through Test Cables As Figure 11 shows, when using the same tap values for both measurement and simulation, correlation is excellent. Both de-emphasized waveforms show a similar rise-time, and both methods keep the same rise-time for both full-swing and partial-swing bits in the pattern. To further illustrate FFE equalization, Figure 12 shows results at 6.25 Gbps and 12.5 Gbps through the STRADA Whisper 11.5 channel. In this case, optimal tap values are automatically calculated within the ADS channel simulator and Stateye. When only an FFE is present, the tap values from Stateye and ADS agree well. Note that eyes are open at 12.5 Gbps, but higher bitrate correlation could not be shown, since the DPP only goes to 12.5 Gbps Gbps t(0) = t(1) = t(2) = BERTScope ADS Overlay (Red Contour) Stateye Overlay Height: 39% Height: 46% Height: 47% Width: 82% Width: 85% Width: 87% 12.5 Gbps t(0) = t(1) = t(2) = Height: 21% Width: 63% Height: 23% Width: 68% Height: 29% Width: 72% Figure 12: 3-Tap FFE Measurement & Simulation Correlation for STRADA Whisper 11.5 Channel 12

13 As with throughput-only data, correlation of equalized data, as shown in Figure 12, is excellent between ADS and Stateye. Measured eye patterns are once again more closed that simulated values, but interestingly, not as much as for throughput-only measurements. It appears as though the DPP driver output is somewhat cleaner than the BERTScope itself. Another example of equalized throughput validation is shown in Figure 13 for the STRADA Whisper 27 system Gbps t(0) = t(1) = t(2) = BERTScope ADS Overlay (Red Contour) Stateye Overlay Height: 41% Height: 46% Height: 46% Width: 79% Width: 88% Width: 90% 6.25 Gbps t(0) = t(1) = t(2) = Height: 20% Width: 62% Height: 27% Width: 76% Height: 28% Width: 76% Figure 13: 3-Tap FFE Measurement & Simulation Correlation for STRADA Whisper 27 Channel Besides verifying that simulation and measurement agree for a given set of tap values, it is also important to verify that the automatic tap optimization of a simulator does indeed produce the most open eye possible. Because a hardware DFE solution doesn t exist, verifying optimum tap optimization when both an FFE and DFE are present is best done through inter-tool comparisons. As an example, Figure 14 shows 20 Gbps equalized results from both the ADS channel simulator and Stateye when running the 27 STRADA Whisper system with a 3-tap FFE and a 5-tap DFE. Whisper 27 System 20 Gbps, Random Pat Post-FFE, Pre-DFE Post-FFE, Post-DFE Stateye Overlay ADS Statistical Optimization Stateye Optimization Figure 14: FFE/DFE Tap Optimization Comparison between Stateye and ADS Channel Simulator 13

14 As Figure 14 shows, the tap values calculated by Stateye produce a more open eye pattern than the tap values calculated by receiver optimization of FFE and DFE tap values in the ADS statistical channel simulator. The reason for this is that Stateye optimizes FFE and DFE tap values simultaneously while the ADS channel simulator s statistical-mode optimization optimizes the FFE first and then the DFE second. As proven in Figure 14, it turns out that a suboptimal FFE combined with a sub-optimal DFE can produce optimal results. When Stateyecalculated FFE & DFE tap values are used in the ADS channel simulator, the eye opening precisely matches that of Stateye. Note that there is a method for getting optimal tap values within the ADS channel simulator. When running quasi-analytical analysis in bit-by-bit mode, the ADS channel simulator can use a least mean squares (LMS) or minimum mean square error (MMSE) method to complete adaptive equalization. One can use adaptive equalization in ADS bit-by-bit mode to find optimal tap values for an FFE and DFE combination. This can be done for a PRBS 2 15 sequence in a reasonable amount of time. One must be certain, however, to feed the calculated tap values manually back into the ADS statistical channel simulator in order to simulate a worst-case random bit pattern with these optimal equalization tap values. As a final note on equalization, notice that all FFE and DFE tap values in this paper have been passive. The ADS channel simulator will calculate active tap values during statistical-mode automatic tap optimization. Because it is currently unclear the level to which chip vendors are able or willing to complete broadband amplification, it is recommended to renormalize all active tap values by dividing them by the absolute sum of all FFE taps. Jitter The last channel simulator feature to validate is jitter injection on high-speed signals. Generally, jitter from channel ISI or crosstalk is already handled during simulation. However, stress such as random jitter (RJ), periodic jitter (PJ), and duty-cycle distortion (DCD), all inherent in active devices, needs to be accounted for separately in simulation drivers. Note that one will find numerous types of jitter offered in different simulators and test equipment. However, random jitter, periodic jitter (a.k.a. sinusoidal jitter), and duty-cycle distortion are very common. In Stateye, high-probability peak-to-peak jitter is represented as deterministic jitter (DJ). This type of jitter is not available in BERTScope equipment or in ADS. However, simulations have shown that PJ, which is available on the BERTScope and in ADS, emulates DJ bounds fairly well. To examine the validity of simulator RJ injection, consider the Z-PACK HM-Zd 10 system and the STRADA Whisper 11.5 system results shown in Figure 15. In both cases, peak-to-peak RJ (BER = ) of 0.15 UI was injected into the systems for both simulation and measurement. For the Z-PACK HM-Zd 10 system running at Gbps, correlation between simulation and measurement is reasonable, though measured eye widths are about 10% more closed than those simulated by ADS and Stateye. This may be caused by amplitude noise in measurement that can t currently be accounted for in simulation. For the STRADA Whisper 11.5 system running at 6.25 Gbps, correlation between simulation and measurement is unacceptable. Examination of the low-probability contours on the right side of the eye pattern shows that measured results are far too pessimistic. There appears to be a problem with measured RJ injection above 3.25 Gbps, and this will be discussed in more detail later. 14

15 HM-Zd 10 RJ p-p = 0.15 UI (RJ RMS = 3.02 ps) Gbps BERTScope ADS Overlay (Red Contour) Stateye Overlay Height: 61.1% Height: 62.0% Height: 59.9% Width: 62.9% Width: 73.0% Width: 73.0% Whisper 11.5 RJ p-p = 0.15 UI (RJ RMS = 1.51 ps) 6.25 Gbps Height: 31.1% Width: 47.1% Height: 37.1% Width: 62.0% Height: 38.0% Width: 64.0% Figure 15: Random Jitter (RJ) Comparison of Simulation and Measurement Figure 16 shows correlation results for periodic jitter. In this case, data is shown for the STRADA Whisper system at 6.25 Gbps and for test cables at 12.5 Gbps. At 6.25 Gbps, correlation between simulations and measurement is reasonable, though measured data is again about 10% more closed horizontally than simulated data. This result is similar to that seen in RJ in Figure 15 and might be caused by test data amplitude noise non-existent in simulations. At 12.5 Gbps, correlation between simulated results and measurement is unacceptable. As with RJ measurements at 6.25 Gbps, PJ measurements at 12.5 Gbps are clearly erroneous. The lowprobability contours on the right side of the eye pattern are far too pessimistic when PJ is injected above 6.25 Gbps. Whisper 11.5 PJ AMP = 3 ps PJ FREQ = 40 MHz 6.25 Gbps Test Cables PJ AMP = 6 ps PJ FREQ = 40 MHz 12.5 Gbps BERTScope ADS Overlay (Red Contour) Stateye (DJ) Overlay Height: 32.8% Width: 60.5% Height: 39.8% Width: 70.5% Height: 42.2% Width: 73.0% Height: 50.0% Height: 70.1% Height: 61.6% Width: 34.8% Width: 63.5% Width: 65.0% Figure 16: Periodic Jitter (PJ) Comparison of Simulation and Measurement Note that in Figures 15 and 16, correlation between Stateye and ADS simulation results is very good. One might notice, however, that ADS simulations always report a more closed horizontal eye than does Stateye. This result is expected, because ADS uses a different jitter calculation algorithm than does Stateye. Agilent has shown, through comparison with long Monte Carlo simulations, that this new method to handle jitter is more accurate than the Stateye method [2]. 15

16 As Figures 15 and 16 show, there are clearly some current jitter injection issues with test data. It is important to mention that, due to test equipment availability, jitter injection was completed during measurement in a somewhat unusual fashion. At the time of measurement, no 25 Gbps generators were available with built-in jitter injection. Therefore, a separate generator with jitter injection capabilities was used to inject jitter into a second BERTScope. Though this should work, it is clear that the method worked at lower bit rates but not at higher bit rates. It is possible that regular BERTScope boxes, with built-in jitter injection, do not show this issue. At the time of this publication, the issue is under investigation. Before concluding this section on jitter, it is also worthwhile to examine another source of nonjitter transmit stress, which is duty-cycle distortion (DCD). Figure 17 shows a 12.5 Gbps signal, injected with 9% DCD, through measurement cables. Figure 17: Duty Cycle Distortion (DCD) Comparison of Simulation and Measurement It should be clear in Figure 17 that the measured data is incorrect. Because there is no inherent setting in the BERTScope for DCD, creation of DCD was attempted using data output symmetry control. Given that this didn t work properly, it is currently under investigation whether or not DCD injection is possible or not with the BERTScope. As for simulated data, ADS and Stateye results agree very well. It is worth noting that Stateye does not display the data correctly, because it only calculates one half of an eye pattern and then flips it to show the other half. Even so, the eye height and zero-crossing width reported by Stateye appear to be correct. Validation Conclusions The first goal of the paper was to correlate fast new quasi-analytical and statistical simulators to traditional transient convolution simulations. It is clear that the fast simulators agree very well with traditional simulation results, so long as simulated channels meet LTI requirements. It is important to note that the accuracy of any channel simulation, especially at higher bit rates and with lower-loss channels, depends heavily on how a simulator handles band-limited frequency data. Data has shown that ADS uses an advanced algorithm that handles this issue effectively. 16

17 The second goal of the paper was to validate fast simulator results against measured test data. Data presented in the paper show that high-probability eye pattern results correlate extremely well between simulation and measurement. However, it is also clear that achieving perfect correlation of low-probability contours (BER = 10-9, 10-12, ) is not a trivial task. To achieve low-probability contour correlation, one must be able to emulate driver and receiver characteristics precisely. Further, it appears that one needs to be able inject amplitude noise in simulation. Note that this paper only shows a small portion of overall test data examined. The third goal of the paper was to highlight test equipment and simulation needs if necessary. After attempting to complete high-speed validation, it is clear that there are still numerous capabilities that need to be expanded in with both measurement equipment and simulation tools. These issues are highlighted in the bulleted lists below: Test Equipment Needs: Resolve RJ/PJ/DCD injection issues along with choppy contour issues Extend FFE hardware beyond 12.5 Gbps to Gbps where equalization is required Add hardware or software DFE solution to Gbps Decrease driver edge rate from current ~20 ps rise time down to 10 ps rise time or less Provide better test equipment specifications to help with simulation: o Specific edge rate for transmitter and FFE outputs o Specific jitter and amplitude noise information for transmitter and FFE outputs o Driver and receiver input parasitics (as lumped circuits or differential return loss) o IBIS AMI models? Channel Simulator Needs: (Stateye is no longer supported by OIF, so focusing on ADS channel simulator) Ability to include IBIS AMI driver models (already planned for future inclusion) Ability to inject peak-to-peak deterministic jitter (already planned for future inclusion) Ability to inject amplitude noise Improved equalization optimization scheme o Simultaneous FFE/DFE tap optimization in statistical-mode auto optimization o Options for making all taps passive and running CTE/FFE/DFE at the same time 25 Gbps Channel Simulations After completing correlation work between Stateye and ADS, along with validation of the tools versus test data, it is clear that the ADS channel simulator is preferred to Stateye in completing high-speed channel simulations. Besides the fact that Stateye is no longer supported by the Optical Interconnect Forum (OIF), the ADS channel simulator offers a number of distinct advantages. Specifically, the ADS channel simulator runs worst-case bit patterns very quickly, it handles band-limited frequency data well, it provides numerous options for calculating crosstalk, it provides state-of-the-art capabilities for jitter calculation, and it provides several options for digital equalization optimization. When using the ADS channel simulator, one must be careful to implement the tool properly for given simulation needs. In order to emulate worst-case bit patterns, statistical mode must be 17

18 used, as it emulates a totally random pattern. When completing digital equalization with both an FFE and a DFE, one must be careful in determining optimal tap values, as there are several methods to do so, and not all of them are optimal. Finally, when implementing channel crosstalk, one must choose between asynchronous (random) crosstalk and synchronous (fixed) crosstalk. The use of synchronous crosstalk is somewhat dangerous as peak noise values may not align across multiple aggressors to give worst-case eye closure. The use of asynchronous crosstalk ensures that peak eye closure is shown across the throughput eye pattern s entire unit interval (with some statistical relief). Past Channels During DesignCon09, simulated channel data was shown for the Tyco Electronics STRADA Whisper connector, running at 25 Gbps in Stateye [3]. It is worthwhile to re-visit these simulations now using the more accurate ADS channel simulator. The channels that were simulated previously are shown in Figure 18. Figure 18: Short & Long STRADA Whisper Backplane Channels Simulated at 25 Gbps for DesignCon09 Note that there were two incorrect entries in the DesignCon09 paper for the system diagram shown in Figure 18. First, the diagram had listed that simulations used 6 mil traces with 8 mil spacing; however, simulations actually used 8 mil traces with 11 mil spacing. Also, the edge rate had been listed at 20 ps, but further study into the workings of Stateye revealed that the inherent edge rate of the simulations was 7.6 ps (0-100%). This edge rate is a result of the fact that Stateye pads frequency data to 66 GHz. The time-step for such data is 1 / (2*66e9) or ~7.6 ps. Upcoming simulation comparisons of the Figure 18 channel use values of for the trace geometry and 7.6 ps for the edge rate in both Stateye and ADS. Figure 19 shows simulation results for the STRADA Whisper 14.8 channel using 2-tap FFE equalization. As the throughput-only data table shows, the ADS channel simulator produces eye patterns that are more closed than those produced by Stateye. The ADS result is correct, since ADS handles band-limited frequency data and jitter injection more accurately than Stateye. Also, Figure 19 shows that NEXT and FEXT close eye patterns more in ADS than in Stateye. Again, ADS produces the correct result, as it has been shown previously that Stateye does not calculate crosstalk correctly at high data rates. 18

19 ADS & Stateye Throughput with NEXT ADS & Stateye Throughput with FEXT Figure 19: Stateye & ADS Simulation Results for DesignCon STRADA Whisper Channel Figure 20 shows simulation results for the STRADA Whisper 30.8 channel using 5-tap FFE and 7-tap DFE equalization. As the throughput-only data table shows, the ADS channel simulator produces eye patterns that are more closed than those produced by Stateye. The ADS result is correct, since ADS handles band-limited frequency data and jitter injection more accurately than Stateye. Also, Figure 19 shows that NEXT and FEXT close eye patterns more in ADS than in Stateye. Again, ADS produces the correct result, as it has been shown previously that Stateye does not calculate crosstalk correctly at high data rates. ADS & Stateye Throughput with NEXT ADS & Stateye Throughput with FEXT Figure 20: Stateye & ADS Simulation Results for DesignCon STRADA Whisper Channel 19

20 For the most part, Stateye predicted successful 25 Gbps signal transmission for the short and long channels shown by Figure 18. However, it turns out that Stateye was too optimistic in its calculations of jitter and crosstalk. Therefore, when the short and long systems of Figure 18 were re-simulated using the correct jitter and crosstalk calculations of the ADS channel simulator, 25 Gbps transmission results were more pessimistic. As a result, it is worth re-visiting the Figure 18 channels to determine what settings are necessary to achieve successful 25 Gbps operation. Improved Channels Figure 21 shows updated short and long STRADA Whisper channels. These updated channels use 6 mil traces with 8 mil spacing and have a 10 ps (10-90%) edge rate, which is achievable in modern silicon. In order to improve 25 Gbps system performance, the backplane and daughtercard dielectrics have been updated to Panasonic Megtron6, which has an effective dielectric constant of ~3.5 and an effective loss tangent of ~ % UI Figure 21: Improved Short & Long STRADA Whisper Backplane Channels Simulated at 25 Gbps Initial simulations of the updated channels in Figure 21 did not produce successful 25 Gbps channel operation. Even for the short system, application of a 4-tap FFE and 5-tap DFE could not produce an open eye at 25 Gbps. Therefore, one more improvement was necessary to achieve successful 25 Gbps operation. As it turns out, allowing 0.30 UI of total jitter (as shown in Figure 18) in a driver that runs a 10ps edge rate makes the task of meeting a 47.5% horizontal mask requirement very difficult. Therefore, it was clear that jitter tolerances needed to be tightened to achieve successful operation. In the initial system, the driver output was 15% UI of DJ p-p and 15% UI of RJ p-p (BER = ). As Figure 21 shows, these jitter amounts were tightened so that the driver output is now 10% UI of DJ p-p and 10% UI of RJ p-p (BER = ). Note that 10% UI RJ p-p at BER = corresponds to RJ RMS = 0.63% UI. Figure 22 shows 25 Gbps ADS channel simulator results for the STRADA Whisper 14.8 channel with the updated system settings. 20

21 ADS & Stateye Throughput with NEXT ADS & Stateye Throughput with FEXT Figure 22: Stateye & ADS Simulation Results for Improved STRADA Whisper 14.8 Channel Figure 22 makes it clear that 25 Gbps transmission is possible for the improved STRADA Whisper 14.8 channel, even with the presence of full NEXT or FEXT. To reiterate, this performance is made possible, even using only 2 FFE taps, by updating two channel settings. First, the system dielectric is improved to Panasonic Megtron6. Second, jitter tolerances for the driver are tightened from 30% UI p-p to 20% UI p-p. Figure 23 shows 25 Gbps ADS channel simulator results for the STRADA Whisper 30.8 channel with the updated system settings. ADS & Stateye Throughput with NEXT ADS & Stateye Throughput with FEXT Figure 23: Stateye & ADS Simulation Results for Improved STRADA Whisper 30.8 Channel 21

22 Figure 23 shows that 25 Gbps transmission is challenging for a 30.8 backplane system, even using a premium connector and the improved system settings of Figure 21. In this case, 5 FFE taps (2 pre-, 1 main, and 2 post-) and 7 DFE taps are used, but even with this level of digital equalization, performance is marginal. For throughput-only and throughput with full FEXT, the data technically violates the eye mask height. However, both of these scenarios pass the eye mask width, and it would only take a small amount of broadband amplification to make the data pass the mask height. Typically, it is safest to simulate high-speed channels with no equalization gain, as it is not clear how comfortable silicon vendors are with adding broadband amplification. However, in this case, even a small 2x gain would allow the eyes to pass the mask, which may be achievable considering gain-bandwidth limitations of amplifiers. Preliminary discussions with a few vendors indicate that low-amplitude gain might be achievable to high frequency. Channel Simulation Conclusions Ultimately, it is quite evident that successful transmission of 25 Gbps signals across longer backplane channels is challenging. Every aspect of the link must be pushed to achieve premium performance if successful transmission is to be made. These links must use an excellent lowreflection, low-crosstalk connector such as the STRADA Whisper connector from Tyco Electronics. The channels must also use low-loss dielectric materials and possibly smooth copper. Finally, active devices must output fast edge rates, have low package parasitics, and be capable of multi-tap FFE and DFE equalization as well as possible broadband amplification. Note that high-speed channel simulations will be more accurate with higher-frequency S- parameter data for all components (> 20 GHz). Also, it will become critical in these channel simulations to emulate active devices accurately, and this will likely be achieved through vendor generation of IBIS AMI driver models. In the future, work will be done to use the ADS channel simulator to construct premium STRADA Whisper backplane and daughtercard test sets in order to successfully demonstrate 25 Gbps operation with next generation SERDES chips. Also, work will continue with test equipment vendors and software vendors to add necessary capabilities to the tools so that simulation and measurement results can converge. In the future, simulation and measurement tools may ultimately need to incorporate alternate forms of signaling, modulation, and equalization in order to make 25 Gbps signaling reliable across long reach backplane systems. 22

23 Acknowledgements The author would like to thank Fangyi Rao and Sanjeev Gupta of Agilent Technologies EEsof division for assistance with the ADS bit-by-bit and statistical channel simulators. Also, special thanks goes to Synthesys Research for allowing usage of the BERTScope Si 25000C equipment as well as Mike Cina of Tyco Electronics for traveling to the Synthesys Research facility in order to gather large amounts of high-speed channel data. References [1] Fangyi Rao, Optimization of Spectrum Extrapolation for Causal Impulse Response Calculation Using the Hilbert Transform, Patent US 2008/ A1, 2008Nov13. [2] Fangyi Rao, Vuk Borich, Henock Abebe, Ming Yan, Rigorous Modeling of Transmit Jitter for Accurate and Efficient Statistical Eye Simulation, DesignCon2010, Track 8-TP2. [3] Chad Morgan, A Signal Integrity Comparison of 25 Gbps Backplane Systems Using Varying High-Density Connector Performance Levels, DesignCon09, Track 7-TA4. 23