NChannel Enhancement Mode Field Effect Transistor General Description The AOD486 combines advanced trench MOSFET technology with a low resistance package to provide extremely low R DS(ON). This device is ideal for low voltage inverter applications. Features V DS (V) =V I D = 35A R DS(ON) < 5mΩ R DS(ON) < 9mΩ (V GS = V) (V GS = V) (V GS = 4.5V) RoHS Compliant % UIS Tested! Halogen Free % R g Tested! Top View D TO5 DPAK Bottom View D G S G G S S Absolute Maximum Ratings T A =5 C unless otherwise noted Parameter DrainSource Voltage GateSource Voltage Symbol V DS V GS Maximum ± Units V V Continuous Drain T C =5 C 35 Current G I D T C = C 7 A Pulsed Drain Current C I DM 7 Continuous Drain T A =5 C I DSM Current T A =7 C 8 A Avalanche Current C Repetitive avalanche energy L=.mH C I AR E AR 4 9 A mj T C =5 C 5 Power Dissipation B P D T C = C 5 W T A =5 C.5 Power Dissipation A P DSM T A =7 C.6 W Junction and Storage Temperature Range T J, T STG 55 to 75 C Thermal Characteristics Parameter Symbol Typ Max Units Maximum JunctiontoAmbient A t s 6.7 5 C/W R θja Maximum JunctiontoAmbient A D SteadyState 5 C/W Maximum JunctiontoCase SteadyState R θjc.5 3 C/W
Electrical Characteristics (T J =5 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS DrainSource Breakdown Voltage I D =5µA, V GS =V V I DSS Zero Gate Voltage Drain Current V DS =V, V GS =V T J =55 C 5 µa I GSS GateBody leakage current V DS =V, V GS = ±V na V GS(th) Gate Threshold Voltage V DS =V GS I D =5µA.7..7 V I D(ON) On state drain current V GS =V, V DS =5V A V GS =V, I D =A.4 5 R DS(ON) Static DrainSource OnResistance T J =5 C 4 mω V GS =4.5V, I D =5A 4.5 9 mω g FS Forward Transconductance V DS =5V, I D =A 6 S V SD Diode Forward Voltage I S =A,V GS =V.75 V I S Maximum BodyDiode Continuous Current 6 A DYNAMIC PARAMETERS C iss Input Capacitance 78 98 pf C oss Output Capacitance V GS =V, V DS =V, f=mhz 9 3 7 pf C rss Reverse Transfer Capacitance 48 8 pf R g Gate resistance V GS =V, V DS =V, f=mhz.9 3.8 5.7 Ω SWITCHING PARAMETERS Q g (V) Total Gate Charge 3.5 7 nc Q g (4.5V) Total Gate Charge 7 9 nc V GS =V, V DS =V, I D =A Q gs Gate Source Charge.5 3 nc Q gd Gate Drain Charge.7 4.5 6.3 nc t D(on) TurnOn DelayTime 6 ns t r TurnOn Rise Time V GS =V, V DS =V, R L =.Ω, ns t D(off) TurnOff DelayTime R GEN =3Ω 6 ns t f TurnOff Fall Time 7 ns t rr Body Diode Reverse Recovery Time I F =A, di/dt=5a/µs 9 5 ns Q rr Body Diode Reverse Recovery Charge I F =A, di/dt=5a/µs 4 3 38 nc A. The value of R θja is measured with the device mounted on in FR4 board with oz. Copper, in a still air environment with T A =5 C. The Power dissipation P DSM is based on R θja and the maximum allowed junction temperature of 5 C. The value in any given application depends on the user's specific board design, and the maximum temperature of 75 C may be used if the PCB allows it. B. The power dissipation P D is based on T J(MAX) =75 C, using junctiontocase thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C. Repetitive rating, pulse width limited by junction temperature T J(MAX) =75 C. Ratings are based on low frequency and duty cycles to keep initial T J =5 C. D. The R θja is the sum of the thermal impedence from junction to case R θjc and case to ambient. E. The static characteristics in Figures to 6 are obtained using <3µs pulses, duty cycle.5% max. F. These curves are based on the junctiontocase thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX) =75 C. The SOA curve provides a single pulse rating. G. The maximum current rating is limited by bondwires. H. These tests are performed with the device mounted on in FR4 board with oz. Copper, in a still air environment with T A =5 C. Rev : May9 COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 8 V 6V 8 V DS =5V 6 4.5V 6 4V I D (A) I D (A) V GS =3.5V 5 C 5 C 3 4 5 V DS (Volts) Fig : OnRegion Characteristics (Note E) 3 4 5 6 V GS (Volts) Figure : Transfer Characteristics (Note E) R DS(ON) (mω) 8 6 4 V GS =4.5V V GS =V Normalized OnResistance.8.6.4. V GS =V I D =A 7 5 V GS =4.5V I D =5A 8 5 5 5 3 I D (A) Figure 3: OnResistance vs. Drain Current and Gate Voltage (Note E).8 5 5 75 5 5 75 Temperature ( C) Figure 4: OnResistance vs. Junction Temperature 8 (Note E) R DS(ON) (mω) 35 3 5 5 C I D =A I S (A).E.E.E.E.E.E3 5 C 5 C 5 5 C.E4 4 6 8 V GS (Volts) Figure 5: OnResistance vs. GateSource Voltage (Note E).E5...4.6.8.. V SD (Volts) Figure 6: BodyDiode Characteristics (Note E)
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 5 8 V DS =V I D =A C iss V GS (Volts) 6 4 Capacitance (pf) 9 6 C oss 3 5 5 Q g (nc) Figure 7: GateCharge Characteristics C rss 3 V DS (Volts) Figure 8: Capacitance Characteristics. I D (Amps).. R DS(ON) limited T J(Max) =75 C T C =5 C DC µs µs µs ms ms Power (W) 6 8 T J(Max) =75 C 7 T C =5 C 5... V DS (Volts) Figure 9: Maximum Forward Biased Safe Operating Area (Note F).... Figure : Single Pulse Power Rating Junctionto 8 Case (Note F) Z θjc Normalized Transient Thermal Resistance. D=T on /T T J,PK =T C P DM.Z θjc.r θjc R θjc =3 C/W Single Pulse In descending order D=.5,.3,.,.5,.,., single pulse P D T on T...... Figure : Normalized Maximum Transient Thermal Impedance (Note F)
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS I AR (A) Peak Avalanche Current T A =5 C T A =5 C T A = C T A =5 C.... Time in avalanche, t A (s) Figure : Single Pulse Avalanche capability (Note C) Power Dissipation (W) 6 5 3 5 5 75 5 5 75 T CASE ( C) Figure 3: Power Derating (Note F) 6 Current rating I D (A) 5 3 Power (W) T A =5 C 7 5 5 5 75 5 5 75 T CASE ( C) Figure 4: Current Derating (Note F)... 8 Figure 5: Single Pulse Power Rating Junctionto Ambient (Note H) Z θja Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T A P DM.Z θja.r θja R θja =5 C/W Single Pulse In descending order D=.5,.3,.,.5,.,., single pulse T...... Figure 6: Normalized Maximum Transient Thermal Impedance (Note H) P D T on
Gate Charge Test Circuit & Waveform Qg V Qgs Qgd Ig RL Resistive Switching Test Circuit & Waveforms Charge Rg 9% % td(on) t r t d(off) t f t on t off Unclamped Inductive Switching (UIS) Test Circuit & Waveforms L E = / LI AR AR BV DSS Rg Id Id I AR Diode Recovery Test Circuit & Waveforms Q = Idt rr Ig Isd L Isd I F di/dt I RM t rr