Mixed-Signal System-on-a-Chip (SoC) Verification Based on SystemVerilog Model

45th Southeastern Symposium on System Theory Baylor University, Waco, TX, USA, March 11, 2013 Mixed-Signal System-on-a-Chip (SoC) Verification Based on SystemVerilog Model Xiaokun Yang¹, Xinwei Niu¹, Jeffrey Fan¹, Chiu Choi² ¹Department of Electrical and Computer Engineering, Florida International University, FL, USA ²Department of Electrical Engineering, University of North Florida, FL, USA Abstract Simulation speed and a lack of test approaches are the main difficulties in the mixed-signal verification of a complex System-on-a-Chip (SoC). In this paper, an equivalent high-level Radio Frequency (RF) model is created by the SystemVerilog language and integrated into a mixed-signal SoC. Such a model can be executed on a digital simulator, which is dramatically faster than the traditional method using an analog solver. Some mixed-signal verification approaches based on digital methods (including constrained random data generation, assertion-based verification, coverage-driven verification, and Verification Methodology Manual) are also presented as well as a case on the integrated SoC. Keywords Mixed-Signal Verification; SoC; SystemVerilog I. INTRODUCTION With the ability to transfer multiple high-definition (HD) video streams wirelessly, a typical High-definition television (HDTV) System-on-a-Chip (SoC) today is inherently analog in dealing with Radio Frequency (RF) signals. To set up a verification environment of such a complex mixed-signal system is a big challenge for verification engineers. It not only needs to simulate in a reasonable amount of time, but also maintain an acceptable level of accuracy. To date, the industry has offered several co-simulation tools, e.g. SPICE, AMS [1, 2]. Since simulations run at the transistor level, these tools are often very time-consuming compared to digital register transfer level (RTL) simulation. Aiming at alleviating low-speed problems, two analog and mixed-signal languages, Verilog-AMS and VHDL-AMS, are proposed. They are partial solutions to the problem of simulation speed, but very weak on verification methods (e.g. constrained-random tests, coverage, assertions, verification methodologies) in order to reach acceptable standards. Currently, some EDA companies, e.g. Cadence and Synopsys, provide several analog Intellectual Properties (IPs) which are designed by wreal and real data. However, such mixed-signal IPs impose additional amount of work and constraints on how these IPs should be seamlessly integrated and verified at SoC level [3-6]. As mentioned above, traditional mixed-signal verification technologies are done at the lower level of abstraction. This ensures accuracy and functional correctness, with the idea of higher level language to describe the functional model just emerging. At the SoC level, a test plan is focused on connectivity and functional integration, where simulation speed is really critical. Thus, one of the contributions we have been trying to make is to achieve an optimum trade-off between performance and accuracy at the system level verification, that is, model analog activities to become more like digital, and reuse digital verification environment, technologies and methodologies. Using floating-point real data to describe analog activities, this research brings a high-level abstraction of the analog model by SystemVerilog verification language (IEEE 1800) [7, 8]. As an extension of Verilog, SystemVerilog is easier to adopt a modular approach for integrating analog models into an existing pure digital environment. In addition, being an integrated part of the simulation engine, it also eliminates the need for external verification tools and interfaces, and thus ensures optimal performance. In this paper, we demonstrate the integration of a mixedsignal SoC involving both digital and analog components, reasonable and verifiable. Key contributions for the implementation include: Model-based design of analog activities by using SystemVerilog verification language. Employing constrained random data generation during the analog simulation process. Employing code coverage analysis in the mixedsignal verification environment. Utilizing functional coverage analysis in the SoC verification environment. Adding assertions in the SoC verification environment. Completing the multi-level verification structure with reference of VMM verification methodology. The remainder of this paper is organized as follows. Section 2 is an overview of mixed-signal SoC architecture. The software programming is described in section 3. Following the functional registers map of the SoC, Section 4 proposes the mixed-signal SoC verification approaches. Section 5 covers experiment results and simulation waveforms and the conclusion in Section 6. 978-1-4799-0038-1/$31.00 2013 IEEE 17

II. SYSTEM ARCHITECTURE This research is based on a HDTV mixed-signal SoC including both digital and analog blocks. Figure 1 shows the overall structure of this circuit. Master bus (MBUS), which is the system bus, is used to configure functional registers from CPU model to devices. Slave bus (SBUS), which is the data bus, is used to transport data from hosts to the DDR. With the capability to transport HD images, two interfaces are available in this SoC. One is USB2.0 interface, which consists of CONTROL and BULK transfer function; the other is Wi-Fi module, which supports 802.11n IEEE wireless communication standard and also backwards compatible with 802.11 a/b/g specifications. A Wireless Fidelity (Wi-Fi) interface is generally divided into two parts. The first contains Media access controller (MAC) and BBP, which are digital modules using Verilog HDL design. The second contains RF components [9], which are analog models using SystemVerilog design. The amplifier gains of RF models are controlled by the Inter- Integrated (I2C) Circuit through the configuration of functional registers. In our research, MAC, Image Processing, DMA and DDR are considered to be golden models or black boxes. Some of the topics covered in the paper include, but are not limited to, the following: Check the function of amplifying or reducing the analog signal magnitude according to the functional registers configured by I2C-BUS controller. Check real data interaction between BBP digital modules and RF analog models. Verify mixed-signal chip by digital verification technologies. Amplifier (LNA), Variable Gain Amplifier (VGA) and Power amplifier (PA), which are shown in the Figure 2. Fig. 2. RF structure For the receiving process, LNA is at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. The LNA gain ranges from -3dB to 10dB or 35dB of this system, which is set through the I 2 C-BUS interface. VGA provides precise input attenuation and interpolation, a linear-in-db gain-only deviating ±0.5dB. For the transmitting process, PA is another output gain, which is configurable through I 2 C-BUS. All of these analog modules have different approaches to algorithm optimization, in which abstract equation models represent the circuits. III. SOFTERWARE PROGRAMMING The RF configuration process is a control function, which does not require a high-speed data transfer. We then can apply a serial bus structure, I 2 C-BUS, to adjust amplifier gains. Although serial bus does not have the throughput capability of parallel bus, it does require less wiring and fewer connecting pins. Two wires, serial data (SDA) and serial clock (SCL), carry information between RF configuration model and I 2 C-BUS controller. Figure 3 represents four commands combined with SDA and SCL wires. Fig. 1. System architecture The analog models contain Analog-to-Digital Converter (AD), Digital-to-Analog Converter (DA), Low Noise Fig. 3. I 2 C-BUS commands 18

As a master of this bus structure, I 2 C-BUS controller allows the users to configure the amplifier gains for specific functions or operations through a structured register space provided inside the chip with translating commands from MBUS to bit stream data on SCL and SDA serial ports. Different from digital module configuration approach, RF functional registers are accessed via the I 2 C-BUS serial port and can be written to or read via this port. Each of devices connected to the central bus, MBUS, can be handled by a specific register in the register map. This is basically how software interacts with hardware devices. The meaning of the register field represents a specific functional operation of the RF model. IV. SYSTEM LEVEL VERIFICATION Leveraging pre-existing digital verification technologies and verification environment on mixed-signal SoC is this research s motivation. It will effectively mitigate the cost of mixed-signal SoC verification procedure. A. Verification environment We set up the verification environment with the objectoriented programming (OOP) concept and multi-level hierarchical scheduling by SystemVerilog language, with reference to the VMM verification methodology. The test bench structure is shown in Figure 4. communicates with the functional layer using channels. Function-level layer gets input transactions from input channels, manipulates those transactions in a user-defined manner according to wireless specification and delivers one or more streams of transactions to outputs. Physical medium dependent (PMD) HT-mixed format physical layer convergence procedure (PLCP) protocol data unit (PPDU) is shown in Figure 5. Test-level layer generates a stream of constrained random transactions and delivers them to a transactor. Fig. 5. 802.11n PMD layer data frame (HT-mixed PPDU) B. Constrained random value generation Constrained random testing is more effective than directed testing approach. This co-simulation test bench uses constraint-driven test on top of an object-oriented data abstraction that models the data both on integral and real types to be randomized as objects that contain random variables and user-defined constraints. It s also an easier approach to find hard-to-reach corner cases in analog modules. Figure 6 illustrates the constrained random analog data input process. Fig. 4. System level verification environment For the signal-level layer, we add the analog models described in Figure 2 to digital RTL modules, which is designed for testing (DUT) in this test bench. All the analog models are dynamically controlled from digital side, so this test bench keeps the running speed as a pure digital simulation environment. This layer interacts with the mixedsignal modules by manipulating signals through interfaces with integer or real data type. Command-level layer connects the transaction data objects and activities on ports of the mixed-signal module, which is made up of DUT and analog models. It Fig. 6. Constrained random analog data generation C. Code and functional coverage For system level verification, coverage is used as a metric for evaluating the progress of a verification project in order to control the number of regression times. Particularly code coverage is used to tie the verification environment to the design intended or functionality. Functional coverage is a user-defined metric concerning test plans. It is used to 19

describe corner cases and functional points. This test bench includes both code coverage and functional coverage. An example of a code coverage report is shown in Figure 11 and we give an example of the functional coverage model as follows. Cover point expressions can be described by real or integral data with SystemVerilog. The example shown in Figure 7 illustrates two descriptions of integral valued cover points. The first is transmission data length of 802.11n data frame, which ranges from 0 Bytes to 65535 Bytes; the second is transmission rate, which ranges from MCS0 to MCS7 for 802.11n specification. A covergroup can contain one or more coverage points. The cover point expression takes places when the covergroup is sampled. Initializes DMA, DDR Controller, MAC and BBP modules through system bus MBUS; Initializes RF models by I2C-BUS controller. The graphic module reads image data from DDR, processes it and writes back to DDR using SBUS. Converts 10 bits digital iq data into real number and transmits over RF. Receiver acquires analog signal, which is adjusted according to the parameter, which is a measure by the PHY of the energy observed at the antenna used to receive the current PPDU, through a directional antenna. The receiving process includes: Configures DMA, DDR Controller, MAC and BBP modules through system bus MBUS; Configures RF models by I2C-BUS controller. RF receives analog signal from spatial channel. After decoding signal into 10 bits digital data, BBP transmit data to DDR using SBUS. Graphic module processes image data. Fig. 7. Covergroup example In the preceding example, the cross coverage group specifies cross coverage between two coverage points, transmission data length and data rate. Each coverage point includes a set of bins associated with sampled values or value transitions. D. Assertions To validate the behavior and timing of a design, this test bench inserts some assertions that state the verification function to be performed. For example: mbus_req_gnt: assert property (@posedge clk) req -> req[*1:$] ##0 gnt;) else $error ( assert failed for MBUS timing, %0t ns,$time); //hold request asserted until and including grant asserted If the assert fails at time 10 ns, the error message shall be printed at time 10 ns. V. EXPERIMENTAL RESULTS Using the test bench of Figure 4, this research finishes one 256x256 matrix data (an image) transfer process. A data sequence processed by graphic module is transmitted to spatial channel by means of the Wi-Fi interface. The transmitting process is described by Figure 8: Fig. 8. Data transfer process 20

The data transfer process presented is conceptually quite simple: it is a wireless data flow intended to produce a regular analog waveform, transmission wave form (Figure 9) and reception wave form (Figure 10). Fig. 9. 802.11a Transmission waveform Figure 9 illustrates the transmission frame including initial Legacy Short and Long Training Field (STF and LTF), and HT Signal Field (SIG) by real data. Figure 10 shows the reception waveform, which is adjusted after LNA and VGA gain, thus the magnitude decreases after a few seconds. VI. CONCLUSION This paper has presented a verification process of a HDTV mixed-signal SoC at system level. Much has been done in the digital design space, digital simulator and verification methods, to address this verification complexity and minimize time consumption during simulation. Key advantages for this implementation include (i) real data in a digital-metric simulation tool and test bench, (ii) verification methodologies applicable to mixed-signal SoC, (iii) reusable real signal models or verification IPs, (iv) a faster approach that can speed up the regression testing period, (v) constrained random input data, (vi) assertion-based verification, (vii) code coverage and functional coverage verification. The results show that it is one of the best choices for complex mixed-signal SoC level verification, because not only does it have faster simulation speed but also is easier to migrate to the advanced digital verification technologies. The drawbacks of such models tend to be less accurate and it is very difficult to write equivalent models for many classes of circuits. Applications of this mixed-signal verification solution are better used for functional simulation. In brief, this paper links analog and digital circuits in a common verification environment to help the verification engineer to apply more verification methods then in traditional approaches. The future research will focus on improving the accuracy of analog models, thereby increasing the flexibility and reusability of the verification. Fig. 10. Reception waveform Coverage analysis provides metrics to evaluate verification rate of progress. It is also possible, by means of code coverage analysis, to find missing test cases and possible bugs. Specifically, 100% functional coverage must be attained because the test bench writer usually sets a oneto-one relationship between the cover point and functional point of DUT. However, it is normally impossible to reach 100% for code coverage because of missing test cases or coding style that makes coverage cases logically uncoverable. The code coverage of I 2 C-BUS Controller, which is one module of the SoC, is shown in report example in Figure 11. Fig. 11. I 2 C-BUS controller code coverage REFERENCES [1] Ken Kundert, Principles of Top-Down mixed-signal design. [Online]. Available: http://www.designers-guide.org/design/ [2] Jones,K., Analog and mixed signal verification. Paper presented at the FMCAD 2008 Formal Methods in Computer Aided Design, 17-20 Nov 2008, Portland, OR, USA. [3] W.Hartong, L. Hedrich, and E. Barke, Model Checking Algorithms for Analog Verification. ACM/IEEE Design Automation Conference, 2002, pp.542-547. [4] H. D. Foster, A. Krolnik, and D. Lacey, Assertion-Based Design (2nd Edition). Kluwer Academic Publishers, 2004. [5] G.Bonfini, M.Chiavacci, R.Mariani, R.Saletti A New Verification Approach for Mixed-Signal Systems, 2005 IEEE International Behavioral Modeling and Simulation Conference(BMAS 2005),22-23 September 2005, San Jose, California, USA, accepted for web publication. [6] Prabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O Riordan, Vaibhav Bhutani, Bringing continous domain into SystemVerilog covergroups, DVCon 2012, San Jose, CA. [7] IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language Standard IEEE 1800, Design Automation Standards Committee, Nov. 2005 [8] N. Khan, Y. Kashai and H. Fang, Metric Diven Verification of MixedSignal Designs, Design and Verification Conference(DVCon), 2011. [9] Stefan Joeres, Hans-Werner Groh, Stefan Heinen, Event driven analog modeling of rf frontends, Behavioral Modeling and Simulation Workshop, 2007. BMAS 2007. IEEE International, pp. 46 51, 20-21 Sept. 2007 21