Design of OSC and Ramp Generator block for Boost Switching Regulator

Analog IC Design Contest 2011 Navis Team Hanoi University of Science and Technology Design of OSC and Ramp Generator block for Boost Switching Regulator Final Report Students: Advisors: Pham Van Danh (senior student) Nguyen Trong Toan (junior student) Dr. Vo Le Cuong Dr. Pham Nguyen Thanh Loan Hanoi, 26/06/2011

Contents ACKNOWLEDGMENTS... 5 A. Introduction... 6 I. Target specifications of OSC & Ramp Generator... 6 II. Selected architecture of OSC & Ramp Generator... 7 B. Schematic Design Phase... 9 I. Design and test of comparator block... 9 I.1. Principle of operation... 9 I.2. Simulation results & parameters... 9 II. RS Flip-flop design and testing... 11 II.1. Principle of operation... 11 II.2. Simulation results... 12 III. Switching System... 12 III.1. Principle of operation... 12 III.2. Schematic... 13 III.3. Simulation results... 14 IV. OSC & Ramp Generator block: module assembly and testing... 15 IV.1. Ramp Generator... 15 IV.2. Square waveform Generator... 17 V. OSC & Ramp Generator integrated in whole system... 18 VI. Conclusions... 20 C. Layout Design Phase... 21 I. Targets of Layout Design Phase and methods to achieve them... 21 I.1. Targets of Layout Design Phase... 21 I.2. Methods to achieve targets... 21 II. Layout design and simulation of OSC & Ramp Generator block... 21 II.1. Layout design and simulation of Comparator... 21 II.2. Layout design and simulation of RS Flip Flop... 25 2

II.3. Layout design and simulation of Switching System... 28 II.4. Layout design and simulation of OSC & Ramp Generator block, integrated into Boost Switching Regulator chip.... 29 III. Conclusions... 32 D. Conclusions... 33 Appendix A... 34 3

Figure 1: Output waveform required by contest organizer... 6 Figure 2: OSC & Ramp Generator symbols.... 7 Figure 3: Basic architecture of OSC & Ramp Generator... 8 Figure 4: Operational amplifier structure... 9 Figure 5: Comparator architecture... 10 Figure 6: Output square waveform is created from triangle input signal of Op-amp... 10 Figure 7: Schematic (a) and test configuration (b) of RS Flip-Flop.... 11 Figure 8: Simulation result all possible states of RS Flip-Flop... 12 Figure 9: Switching system architecture... 13 Figure 10: Switching system with 4 transistors (N-P-N-NMOS).... 14 Figure 11: Test configuration of Switching system... 14 Figure 12: Simulation results of Switching system.... 15 Figure 13: Ramp Generator architecture... 16 Figure 14: Ramp output signal obtained from the complete block... 16 Figure 15: Test configuration of complete block, OSC & Ramp Generator.... 17 Figure 16: Square and Ramp output signal obtained from the complete block.... 18 Figure 17: Boost switching regulator... 18 Figure 18: Load regulation simulation... 19 Figure 19: Line regulation simulation... 20 Figure 20: Comparator schematic block diagram... 22 Figure 21: Layout of transistors M0 and M3... 22 Figure 22: Layout of transistors M11 and M14... 23 Figure 23: Comparator block layout... 24 Figure 24: Simulation results of Comparator layout by DRC... 24 Figure 25: Simulation results of Comparator layout by LVS... 25 Figure 26: Simulation results of Comparator layout by LPE... 25 Figure 27: Schematic block diagram of RS Flip Flop... 26 Figure 28: Layout of transistors for NOR gate... 26 Figure 29: RS Flip Flop layout... 27 Figure 30: Simulation results of RS Flip Flop block by DRC... 27 Figure 31: Simulation results of RS Flip Flop block by LVS... 28 Figure 32: Simulation results of RS Flip Flop block by LPE... 28 Figure 33: OSC & Ramp layout block integrated into Boost Switching Regulator IC... 29 Figure 34: Simulation results of OSC & Ramp block by DRC... 30 Figure 35: Simulation results of OSC & Ramp block by LVS... 30 Figure 36: Simulation results of OSC & Ramp block by LPE... 31 Figure 37: Layout of Boost Switching Regulator chip... 31 Figure 38: Simulation results of Boost Switching Regulator layout by DRC... 32 Figure 39: Simulation results of Boost Switching Regulator layout by LVS... 32 4

ACKNOWLEDGMENTS We are a young team of students enthusiastic about Analog IC Design from Navis Center, Hanoi University of Science and Technology. The AICD2011 contest is a great opportunity for us to apply our learning into real work of IC design. Despite all the difficulties from the first days, our team really enjoy working together, sharing passion and facing challenges to go to the end of the contest. Our team would like to send special thanks to the sponsors: Synopsys, ANALOG DEVICES and ICDREC for organizing the contest. We also would like to thank Mr. Ho Quang Tay, Mr. Nguyen Van Kien and Mr. Xi Jiang for their fruitful advices and support helping us to complete our work. Finally, we also would like to thank Navis Center for providing us facilities and support during our contest. 5

A. Introduction I. Target specifications of OSC & Ramp Generator The requirement of this AICD contest is to design the missing block named OSC & Ramp Generator to complete the Boost switching regulator. The role of this missing block is to generate two kinds of waveform: - Ramp waveform (triangle waveform signal) - Square waveform The figure below shows the characteristics of the target waveform provided by the contest organizer: Figure 1: Output waveform required by contest organizer 6

The table below summarizes the target specifications of the OSC & Ramp Generator: Technology 250 nm VH 1.72 V VL 0.57 V T up (charged) 1.15 µs T down (discharged) 0.1 µs V in V out I out_max 3 V 12 V 150 ma T (f = 0.8 MHz) 1.25 µs Table 1: Target specifications The inputs of OSC & Ramp Generator (VH, VR, VL, RST) are determined from the symbols provided by the contest organizer (as figure below). Figure 2: OSC & Ramp Generator symbols. II. Selected architecture of OSC & Ramp Generator Based on the report submitted in the first round of the contest, we chose the below architecture to generate ramp and square-form signals (OSC and Ramp Generator). 7

Figure 3: Basic architecture of OSC & Ramp Generator The design of whole OSC and Ramp modules is divided into several stages as below: - Design of Op-amp to obtain a comparator - Design of Flip-Flop - Design of switching system In the next parts, we will mention in detail the principle of operation as well as target specifications of each block (module). Simulation test will be then carried out to verify whether the blocks meet the target specifications. Individual blocks will be connected together to build up the OSC and Ramp. The complete block will be benchmarked through simulation test according to requirements given by the contest organizer. The last step is to integrate the OSC and Ramp block into the whole system of Boost Switching Regulator to test its functionalities according to variation of input signal or voltage drop due to input load. Finally, we realize the layout of the OSC & Ramp Generator in minimizing and maintaining its square-form area. We then carry out DRC, LVS and LPE until reaching PASS and/or CLEAN messages. 8

B. Schematic Design Phase I. Design and test of comparator block I.1. Principle of operation In this part, we use operational amplifier (Op-amp in abbreviation) to design the comparator block. An operational amplifier is consisted of a differential amplifier, power amplifiers, mirror currents and a buffer. In our design, we use Op-amp structure in the library of PWM, provided by the organizer (as shown in Figure 4). Figure 4: Operational amplifier structure By connecting input waveforms into the non-inverting/inverting inputs of the Op-amp correctly, we can obtain the requested output waveform. I.2. Simulation results & parameters Figure 5 represents the test configuration of this Op-amp, with two input signals: - Triangle waveform (as in Figure 6), modeled by defining the parameters of pulse source, is connected to non-inverting input of Op-amp, as in Figure 5. - DC signal of 1.15V (as in Figure 6) is connected to inverting input of Op-amp, as in Figure 5. 9

Figure 5: Comparator architecture The square waveform of output signal (as in Figure 6, V MAX = 3V, V MIN = 0V) is created from the triangle input signal. The obtained results show a good match with the requirement of Op-amp. Figure 6: Output square waveform is created from triangle input signal of Op-amp 10

II. RS Flip-flop design and testing II.1. Principle of operation The table below shows the functionalities of a RS Flip-Flop. Table 2: RS Flip-Flop functionality We design RS Flip-Flop using four NOR logic gates which are available in the library of PWM. Its symbol is then created with R, S and Reset inputs and two outputs Q and Qn. The figure below represents the schematic (a) and the test configuration (b) of this RS Flip-Flop. (a) (b) Figure 7: Schematic (a) and test configuration (b) of RS Flip-Flop. 11

II.2. Simulation results The obtained results, as seen in Figure 8, show a good match with the functionality of a RS Flip-Flop (as mentioned in table 2). 0 1 0 0 0 0 0 0 1 0 To start Reset = 1 1 Q t-1 0 Q t-1 1 Q t-1 0 Q n, t-1 1 Q n, t-1 0 Q n, t-1 III. Switching System III.1. Principle of operation Figure 8: Simulation result all possible states of RS Flip-Flop (Pink curve: R input; Blue curve: S input; Red curve: Reset; Cyan curve: Q output; Green curve: Qn output) In this system, transistors play the role of switches and are controlled by S1 and S2 input signal corresponding to the output signal Q and Qn of RS Flip-Flop. These switches are responsible for the charge and discharge time of the capacitor C in a period. 0 It results the Ramp signal V C. 12

Figure 9: Switching system architecture As we demonstrated in the exercise 3 of the first round contest, the frequency of Ramp signal is defined as: (1) Where VH, VL are respectively the highest and lowest voltage of Ramp signal, C is the capacitor, I 1 and I 2 are respectively the current sources. Following the requirement of this block, T charged = 1.15 µs and T discharged = 0.1 µs, VH = 1.72 V, VL = 0.57 V. As observed in Eq.1, in order to meet the requirement, the appropriate values of C, I 1 and I 2 must be well chosen. III.2. Schematic We have tested with different circuits: 2 transistors (NMOS-NMOS or PMOS-PMOS) and 4 transistors (PMOS-NMOS-NMOS-NMOS), respectively. Finally, we chose this circuit of 4 transistors (named in top down order M1, M2, M3, M4 and showed in Figure 10) offering lower current that is more suitable for power optimization. As we mentioned above, the transistors M1 and M4 play the roles of current sources; while M2 and M3 play the role of switches. The main job is to optimize the widths and lengths of M1, M3 and the value of C. 13

III.3. Simulation results Figure 10: Switching system with 4 transistors (N-P-N-NMOS). In order to avoid a sophisticated test with Op-amp and Flip-Flop, we used pulse sources to replace Q and Qn signals coming into S1 and S2 inputs, respectively. Figure 11: Test configuration of Switching system As M1 and M4 always operate in saturation mode, the below equation can be used to define their according drain currents or I 1 and I 2 in our context. 14

1 W I ( ) 2 D = µ Cox Vgs Vth (2) 2 L Based on Eq. 1, for a given value of C, we can calculate I 1 and I 2, which, in turn, are the inputs of Eq. 2 resulting values of W/L of transistors M1 and M4. Finally, we figured out the following values: C = 2 pf M1: W = 0.4 µm, L = 0.36 µm M2, M3: W = 0.4 µm, L = 0.34 µm M4: W = 1.2 µm, L = 0.34 µm The obtained results show a good match with requirement. Figure 12: Simulation results of Switching system. IV. OSC & Ramp Generator block: module assembly and testing IV.1. Ramp Generator In this stage, all the modules are connected together to obtain a final circuit as shown below. 15

Figure 13: Ramp Generator architecture In the figure below, we show wave forms of ramp output signal (pink curve), Q signal (blue curve), current passing through M1 and M2 (red curve) and current passing through M3 and M4 (green curve). The obtained results meet the requirement. Figure 14: Ramp output signal obtained from the complete block 16

IV.2. Square waveform Generator As we mentioned previously on the part of comparator design, we can generate a square waveform from a ramp waveform using an Op-amp connected to be a comparator. Therefore, we added an Op-amp that takes ramp output signal as its input signal, as seen in Figure 13. Besides, other input of Op-amp is biased by a DC signal. Finally, we created a testbench for OSC & Ramp simulation as can be seen from Figure 15. Figure 15: Test configuration of complete block, OSC & Ramp Generator. We obtained a good match, as seen in Figure 16, regarding to the requirement. T charged = 1.1 µs T discharged = 0.15 µs V h = 1.72 V V l = 0.57 V T = T charged + T discharged = 1.25 µs (f = 800 khz) 17

V Ramp Q Qn Vr V OSC Figure 16: Square and Ramp output signal obtained from the complete block. V. OSC & Ramp Generator integrated in whole system The symbol of OSC & Ramp Generator is created with the inputs and outputs as required and then connected to the whole system to obtain the final block, Boost Switching Regulator, as shown in the figure below. Figure 17: Boost switching regulator 18

The figure below represents the variation of output signal (stable at12v) as a function of load current (varies from 0 A to 150 ma). It is observed that the output signal is stable at 12 V (as required) with the variation of load current below 150 ma. Figure 18: Load regulation simulation In order to test how the variation of input voltage affects the output voltage, we carried out a test configuration with the variation of Vdd as following: Vdd = 3V from 0s to 500 µs Vdd = 2.8 V from 500 µs to 600 Vdd = 3 V from 600 µs to 700 µs Vdd = 3.6 V from 700 µs to 800 µs Vdd = 3 V from 800 µs to 2.5 ms The figure below represents the simulation results of this test. It is observed that, the output voltage is almost 12 V with the variation (up or down) of input voltage. 19

Figure 19: Line regulation simulation VI. Conclusions Starting from the given parameters, we carried out the study to identify the key parameters of the circuit: transistor dimensions, architecture of RS Flip-Flop with reset, value of C. Finally, we can design a complete and functional circuit that meet the requirement from the AICD contest. 20

C. Layout Design Phase I. Targets of Layout Design Phase and methods to achieve them I.1. Targets of Layout Design Phase - Design the layout of the OSC and Ramp Generator schematic including layouts of RS Flip Flop, Comparator and Switching System. The layout has to achieve the following targets: + Meet basic requirements of the CMOS 90 nm fabrication process. + Occupy as small die area as possible. + High yield factor. - Integrate the layout into the entire Boost Switching Regulator IC in good balance with other blocks of the chip. I.2. Methods to achieve targets Based on experience learning from the other blocks designed by ICDREC, we introduce the following methods to achieve the targets explained in Section I.1. (1) All the layers (silicon(s), polysilicon(s), metal(s), via(s) ) of the layout design must follow rules of the CMOS 90 nm process strictly (Appendix A shows an example of the rules). (2) The use of polysilicon for routing is minimized. (3) The use of polysilicon to connect the gates together is minimized. (4) Contact(s) and via(s) are not directly connected on top of transistors gates. (5) Avoid routing over gates of critical transistors. (6) Avoid routing over active areas of critical transistors. (7) Avoid using of a single via between two layers, especially a small-size via such as one between metal layer 1 and polysilicon. (8) Use metal coverage of contact(s) and via(s). (9) Combine Source/ Drain gates of transistors into a same silicon area to minimize use of silicon. II. Layout design and simulation of OSC & Ramp Generator block II.1. Layout design and simulation of Comparator A layout design of the comparator was completed based on the comparator schematic block diagram in Figure 20. 21

M0 M3 M10 M6 M11 M14 M5 M1 M12 M4 Figure 20: Comparator schematic block diagram To decrease the silicon area required for the layout of the Comparator, we use method (9) in section C.I.2 above. Figures 21 and 22 show two examples of the combinations of gates of transistors to reduce total silicon area of the layout of the Comparator. S S S S M0 G G M3 G G G G D D D Figure 21: Layout of transistors M0 and M3 22

S S S M11 M14 G G G G G D D Figure 22: Layout of transistors M11 and M14 The final layout design of the Comparator is shown in Figure 23. We use other methods together with method (9) in Section I.1 to optimize the performance, silicon area and yield factor of the layout. 23

M0 M3 M12 M6 M11 M14 M2 M1 M10 M4 Figure 23: Comparator block layout The Comparator block layout in Figure 23 was simulated by DRC, LVS and LPE tools of Synopsys. It passes all the simulations without any error and gets significantly low parasitic R and C values for 800 khz operation frequency, as in Figures 24, 25 and 26 respectively. Figure 24: Simulation results of Comparator layout by DRC 24

Figure 25: Simulation results of Comparator layout by LVS Figure 26: Simulation results of Comparator layout by LPE II.2. Layout design and simulation of RS Flip Flop A layout design of the RS Flip Flop was made based on the schematic block diagram in Figure 27. 25

Figure 27: Schematic block diagram of RS Flip Flop As the Flip Flop is built from a basic NOR gate, we started its layout by designing the gate. Figure 28 shows an example of layout of transistors for the NOR gate. The gates then put together and optimized by using the methods in Section C.I.2 to achieve the final layout design of the RS Flip Flop with high performance, small silicon area and high yield factor, as can be seen from Figure 29. S D M1 M15 S D D M0 S D M14 Figure 28: Layout of transistors for NOR gate 26

INV2 INV1 NOR4 NOR1 NOR2 NOR3 Figure 29: RS Flip Flop layout The RS Flip flop in Figure 29 was simulated by DRC, LVS and LPE tools of Synopsys. It passes all the simulations without any error and gets significantly low parasitic R and C values for 800 khz operation frequency, as seen in Figures 30, 31 and 32 respectively. Figure 30: Simulation results of RS Flip Flop block by DRC 27

Figure 31: Simulation results of RS Flip Flop block by LVS Figure 32: Simulation results of RS Flip Flop block by LPE II.3. Layout design and simulation of Switching System Using the same ways to design and simulate the Comparator and RS Flip Flop, we have completed the layout design of the Switching System. Simulation results show that the layout passes through all the checking tools of Synopsys. 28

II.4. Layout design and simulation of OSC & Ramp Generator block, integrated into Boost Switching Regulator chip. In Figure 33, to reach a 1:1 ratio of the entire Boost Switching Regulator, we put the OSC & RAMP block at the top and left edges of the PWM_Control_AICD block. If we created only one physical capacitor layout for the Switching System, it would take a huge area of silicon resulting in difficulties in placing the OSC & Ramp block into the whole chip. Therefore, we decided to split the capacitor into 25 pieces. The Comparator, RS Flip Flop and Switching System are located close to Vdd, VL, VH, VR, bias, biasn of the PWM_Control_AICD block. COMP1 COMP2 RS_Flip Flop COMP3 Capacitor PWM_Cotrol_AICD Figure 33: OSC & Ramp layout block integrated into Boost Switching Regulator IC After fitting into the entire Boost Switching Regulator IC, the OSC & Ramp block was checked by using DRC, LVS and LPE tools of Synopsys. It passes all the simulations 29

without any error and gets significantly low parasitic R and C values for 800 khz operation frequency. Figures 34, 35 and 36 show simulation results using the DRC, LVS, LPE simulation tools respectively. Figure 34: Simulation results of OSC & Ramp block by DRC Figure 35: Simulation results of OSC & Ramp block by LVS 30

Figure 36: Simulation results of OSC & Ramp block by LPE Figures 37, 38 and 39 show the layout design and simulation results of the entire IC by the DRC and LVS tools respectively. Figure 37: Layout of Boost Switching Regulator chip 31

Figure 38: Simulation results of Boost Switching Regulator layout by DRC Figure 39: Simulation results of Boost Switching Regulator layout by LVS III. Conclusions In this phase, we have accomplished the Layout Design, which successfully achieves our targets of high performance, minimized die area and high yield factor. 32

D. Conclusions Throughout the contest, our team has learned new interesting things and developed important skills in analog IC design as well as soft skills to work more effectively. In addition, we have learned how to study a complete circuit (given by AICD) then identify the functions and schematic of missing blocks, OSC & Ramp Generator. We then break this big block down into basic functional sub-blocks. In each sub-block, based on theoretical equation, we can estimate the dimensional parameters of each component (transistors, capacitor). We then apply tools of Synopsys to design these sub-blocks and carry out repetitive simulations to achieve appropriate parameters to meet the target specifications. Finally, we have successfully designed the OSC & Ramp Generator block in accordance with the requirements of the contest. Besides, we have learned to use and get familiar with tools from Synopsys. We also learned teamwork as well as report skills. Making reports in English help us to improve our writing skill very much. 33

Appendix A Table 3: General Design Rules Rule Design Rule Description Design Rule Value 1 Minimum Enclosure of diff by nwell 0.23μm 2 Minimum Enclosure of diff within poly 0.16 μm 3 Minimum Width for contact 0.09 μm 4 Minimum Spacing for contact 0.1 μm 5 Minimum Spacing from Diffusion to Contact 0.1 μm 6 Minimum Enclosure of Contact within 0.05 μm Diffusion 7 Minimum Spacing from Poly to Contact 0.08 μm 8 Minimum Enclosure of Contact within M1 0.005 μm 9 Minimum End of Line Enclosure of Contact 0.04 μm within M1 10 Minimum width for M1 0.1 μm 11 Minimum Spacing from M1 to M1 0.1 μm 12 Minimum width for M2, M3, M4 0.15 μm 13 Minimum Spacing from M2 (M3, M4) to M2 0.15 μm (M3, M4) 14 PPLUS should not overlap NPLUS Table 4: PMOS, NMOS Design Rules Rule Design Rule Description Design Rule Value 1 Minimum Enclosure of PPLUS within Nwell 0.1 μm 2 Minimum Enclosure of Diffusion within 0.23 μm Nwell 3 Minimum Enclosure of Diffusion within PPLUS 0.13μm 4 Minimum Enclosure of Contact within PPLUS 0.06 μm 5 Minimum Spacing of PPLUS to Diffusion 0.13μm 6 Minimum Enclosure of Diffusion within NPLUS 0.13 μm 7 Minimum Enclosure of Contact within NPLUS 0.06 μm 34