Transmitter Characteristics (83D.3.1) Ryan Latchman, Mindspeed

Similar documents
Jitter Measurements in Serial Data Signals

USB 3.0 Jitter Budgeting White Paper Revision 0.5

Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance

RF Measurements Using a Modular Digitizer

Electrical Compliance Test Specification SuperSpeed Universal Serial Bus

PCI Express: The Evolution to 8.0 GT/s. Navraj Nandra, Director of Marketing Mixed-Signal and Analog IP, Synopsys

NRZ Bandwidth - HF Cutoff vs. SNR

Optical Fibres. Introduction. Safety precautions. For your safety. For the safety of the apparatus

Equalization/Compensation of Transmission Media. Channel (copper or fiber)

Timing Errors and Jitter

Electrical Compliance Test Specification SuperSpeed Universal Serial Bus

USB 3.0 CDR Model White Paper Revision 0.5

PCI-SIG ENGINEERING CHANGE NOTICE

The Effect of Network Cabling on Bit Error Rate Performance. By Paul Kish NORDX/CDT

AN-837 APPLICATION NOTE

Sheilded CATx Cable Characteristics

Application Note Noise Frequently Asked Questions

AN Application Note: FCC Regulations for ISM Band Devices: MHz. FCC Regulations for ISM Band Devices: MHz

Clock Jitter Definitions and Measurement Methods

Selecting RJ Bandwidth in EZJIT Plus Software

Dispersion penalty test 1550 Serial

Selecting the Optimum PCI Express Clock Source

Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D.

Equalization for High-Speed Serial Interfaces in Xilinx 7 Series FPGA Transceivers

The Effective Number of Bits (ENOB) of my R&S Digital Oscilloscope Technical Paper

Voice---is analog in character and moves in the form of waves. 3-important wave-characteristics:

Jitter Transfer Functions in Minutes

Suppression of Four Wave Mixing in 8 Channel DWDM System Using Hybrid Modulation Technique

Analog and Digital Signals, Time and Frequency Representation of Signals

Jitter Budget for 10 Gigabit Ethernet Applications with SiTime SiT9120/1 Oscillators

GETTING STARTED WITH LABVIEW POINT-BY-POINT VIS

APPLICATION NOTE ULTRASONIC CERAMIC TRANSDUCERS

Frequency Response of Filters

Understanding Dynamic Range in Acceleration Measurement Systems. February 2013 By: Bruce Lent

TECHNICAL TBR 12 BASIS for December 1993 REGULATION

Step Response of RC Circuits

Technical Innovation. Salland delivers fully Integrated Solutions for High Volume Testing of Ultra-fast SerDes Applications

Duobinary Modulation For Optical Systems

MODULATION Systems (part 1)

A 3.2Gb/s Clock and Data Recovery Circuit Without Reference Clock for a High-Speed Serial Data Link

EXPERIMENT NUMBER 5 BASIC OSCILLOSCOPE OPERATIONS

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

Eye Doctor II Advanced Signal Integrity Tools

Digital Modulation. David Tipper. Department of Information Science and Telecommunications University of Pittsburgh. Typical Communication System

Spike-Based Sensing and Processing: What are spikes good for? John G. Harris Electrical and Computer Engineering Dept

T = 1 f. Phase. Measure of relative position in time within a single period of a signal For a periodic signal f(t), phase is fractional part t p

CPU. PCIe. Link. PCIe. Refclk. PCIe Refclk. PCIe. PCIe Endpoint. PCIe. Refclk. Figure 1. PCIe Architecture Components

Accurate Loss-of-Signal Detection in 10Gbps Optical Receivers using the MAX3991

m Antenna Subnet Telecommunications Interfaces

A Laser Scanner Chip Set for Accurate Perception Systems

Introduction to FM-Stereo-RDS Modulation

TCOM 370 NOTES 99-4 BANDWIDTH, FREQUENCY RESPONSE, AND CAPACITY OF COMMUNICATION LINKS

LONGLINE 10Gbps 10km SFP+ Optical Transceiver

Implementation of Digital Signal Processing: Some Background on GFSK Modulation

AN952: PCIe Jitter Estimation Using an Oscilloscope

Making Accurate Voltage Noise and Current Noise Measurements on Operational Amplifiers Down to 0.1Hz

Sampling Theorem Notes. Recall: That a time sampled signal is like taking a snap shot or picture of signal periodically.

Managing High-Speed Clocks

High-Speed Gigabit Data Transmission Across Various Cable Media at Various Lengths and Data Rate

CHAPTER 6 Frequency Response, Bode Plots, and Resonance

Module 13 : Measurements on Fiber Optic Systems

HD Radio FM Transmission System Specifications Rev. F August 24, 2011

ε: Voltage output of Signal Generator (also called the Source voltage or Applied

Abstract. Cycle Domain Simulator for Phase-Locked Loops

Department of Electrical and Computer Engineering Ben-Gurion University of the Negev. LAB 1 - Introduction to USRP

81110A Pulse Pattern Generator Simulating Distorted Signals for Tolerance Testing

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT BIT DIFFERENTIAL ADC WITH I2C LTC2485 DESCRIPTION

TECHNICAL TBR 14 BASIS for April 1994 REGULATION

Agilent Technologies N5393B PCI Express 2.0 (Gen2) Electrical Performance Validation and Compliance Software for Infiniium Oscilloscopes

Laboratory 4: Feedback and Compensation

Large-Capacity Optical Transmission Technologies Supporting the Optical Submarine Cable System

Radar Systems Engineering Lecture 6 Detection of Signals in Noise

Current Probes, More Useful Than You Think

An Overview of the Electrical Validation of 10BASE-T, 100BASE-TX, and 1000BASE-T Devices

A PC-BASED TIME INTERVAL COUNTER WITH 200 PS RESOLUTION

MATRIX TECHNICAL NOTES

AND8090/D. AC Characteristics of ECL Devices APPLICATION NOTE

Using the On-Chip Signal Quality Monitoring Circuitry (EyeQ) Feature in Stratix IV Transceivers

Computer Networks and Internets, 5e Chapter 6 Information Sources and Signals. Introduction

Application Note. PCIEC-85 PCI Express Jumper. High Speed Designs in PCI Express Applications Generation GT/s

Experiment # (4) AM Demodulator

Non-Data Aided Carrier Offset Compensation for SDR Implementation

Serial ATA International Organization

Electrical Resonance

Reading: HH Sections , (pgs , )

Experiment 7: Familiarization with the Network Analyzer

Use and Application of Output Limiting Amplifiers (HFA1115, HFA1130, HFA1135)

Validation of Quasi-Analytical and Statistical Simulation Techniques for Multi-Gigabit Interconnect Channels

PCM Encoding and Decoding:

Probability and Random Variables. Generation of random variables (r.v.)

How To Understand And Understand Jitter On A Network Device

RECOMMENDATION ITU-R BO.786 *

Feasibility of 25 Gb/s Serial Transmission Over Copper Cable Assemblies

ANALYZER BASICS WHAT IS AN FFT SPECTRUM ANALYZER? 2-1

Lab #9: AC Steady State Analysis

E190Q Lecture 5 Autonomous Robot Navigation

Capacity Limits of MIMO Channels

A SIMULATION STUDY ON SPACE-TIME EQUALIZATION FOR MOBILE BROADBAND COMMUNICATION IN AN INDUSTRIAL INDOOR ENVIRONMENT

MICROPHONE SPECIFICATIONS EXPLAINED

Transcription:

Transmitter haracteristics (83D.3.) Ryan Latchman, Mindspeed

Transmit equalizer Transmitter equalizer range The AUI-4 chip-to-chip transmitter includes programmable equalization to compensate for the frequency-dependent loss of the channel and to facilitate data recovery at the receiver. The functional model for the transmit equalizer is the three tap transversal filter shown in TBD. The minimum pre cursor equalization (c(-)) supported is shown in table TBD. Pre ursor Equalizer Setting Pre ursor Equalization Value db +/- db 2.5dB +/-db 3 3dB +/-db The minimum post cursor equalization (c()) support is shown in table TBD Minimum transmit equalizer range: hange TBD to tables shown on right Post ursor Equalizer Setting Post ursor Equalization Value db +/- db 2 2dB +/- db 3 4dB +/-db 4 6dB +/-db The transmitter output equalization is characterized using the procedure described in TBD. 2

Transmit equalization characterization Measure per 86A.5.3.5 using square wave or PRBS9 defined in Table 86- using a test system with a fourthorder Bessel-Thomson low-pass response with 33 GHz 3 db bandwidth Set post-cursor equalization to the zero setting. Measure pre-cursor amplitude defined as the peak amplitude before a transition. Define, - as normalized main tap, and pre-cursor values per equations A and B. alculate pre-cursor value for each pre-cursor setting using equation Set pre cursor equalization to the zero setting. Measure post-cursor amplitude defined as the peak amplitude after a transition. Define, as normalized main tap, and post-cursor values per equations D and E. alculate post-cursor value for each post-cursor setting using equation F - Amplitude p-p Amplitude p-p Equation A Equation B Equation Equation D Equation E = = Amplitude p p Pr ecursor _ value = 2* LOG = = Amplitude p p Equation F Pr ecursor _ value = 2* LOG 3

Transmit wave form 4

Measurement of Transmit Jitter Transmitter output jitter The components of the transmitter output jitter are defined in this subclause: total jitter (TJ), deterministic jitter (DJ), and random jitter (RJ). Transmitter output is measured at TPa as defined in 83D.2. All co-propagating and counter propagating AUI-4 lanes are active during transmitter output jitter testing. ounter propagating lanes have a target differential peak-to-peak amplitude of 8 mv and transition time of 8 ps. All counter-propagating signals shall be asynchronous to the co-propagating signals using Pattern 5 (with or without FE encoding) Pattern 3 or a valid GBASE-R signal. Patterns 3 and 5 are defined in Table 86-. For the case of Pattern 3, with at least 3 UI delay between the PRBS3 patterns on one lane and any other lane. The effect of a single-pole high-pass filter with 3 db frequency of MHz is applied to the jitter. The test pattern for jitter measurements is PRBS9. The voltage threshold for the measurement of BER or crossing times is the mid-point ( V) of the A-coupled differential signal. Total jitter The total jitter (TJ) of a signal is defined as the range (the difference between the lowest and highest values) of sampling times around the signal transitions for which the BER at these sampling times is greater than or equal to -5. Total jitter for a AUI-4 chip-to-chip transmitter is less than or equal to.28 UI and is measured with optimal transmit equalizer setting. Deterministic and random jitter The random jitter (RJ) of a signal is defined to be the difference between the TJ and DJ. DJ is derived from the measured jitter distribution as follows Measure the jitter Jn which is defined to be the interval that includes all but -n of the jitter distribution. If measured by plotting BER vs. decision time, it is the time interval between the two points with BER of -n /4. Measure two values: J9 and J5 For each Jn determine the associated Qn from the inverse normal cumulative probability distribution adjusted for an assumed transition density of.5. Q9 is 5.998 and Q5 is 4.265 alculate the effective DJ as shown in 83D-4 83D-4 Deterministic jitter is less than or equal to.5 UI. Random jitter is less than or equal to.5 UI. 5

Measurement Methodology for Eye Mask Leverage 83E Transmitter output waveform The eye mask show in is defined at a BER of -5, using the methodology described in TBD. Transmitter equalizer may be adjusted for optimum mask results. TBD section: The transmit output waveform in AUI-4 chip-to-chip is measured using a fourth-order Bessel- Thomson low-pass filter response with 33 GHz 3 db bandwidth. ompliance with X is verified using the methodology described in 83D.3..4 where the maximum TJ is 2 x X. ompliance with Y2 is verified using the methodology described in 83D.3... ompliance with Y is verified using the following procedure with a PRBS9 waveform: apture the PRBS9 pattern using a clock recovery unit with 3 db tracking bandwidth of MHz and maximum peaking of. db and a minimum sampling rate of 3 samples per bit. ollect sufficient samples equivalent to at least 4 million bits to allow for construction of a normalized cumulative distribution function (DF) to a probability of -6 without extrapolation. Use the differential signal from step to construct the DF of the signal amplitude at X2, midpoint (.5) and -X2, for both logic (DF) and logic (DF), as a distance from the center of the eye. alculate the eye height for each point (EH6) as the difference in amplitude between DF and DF with a value of -6. DF and DF are calculated as the cumulative sum of histograms of the amplitude at the top and bottom of the eye normalized by the total number of sampled bits. For a well balanced number of ones and zeros the maximum value for DF and DF will be.5. Apply the Dual-Dirac and tail fitting techniques to DF and DF to estimate the noise at X2,.5 and -X2 points. alculate the best linear fit in Q-scale over the range of probabilities of -4 and -6 of DF and DF to yield relative noise one (RN) and relative noise zero (RN). The eye height for plotting against the eye mask at X2,.5, and -X2 is then given by EH5 = EH6-3.9 x (RN + RN) where EH5 peak is the eye height extrapolated to -5 probability EH6 is the eye height at -6 probability RN is the RMS value of the noise estimated from DF RN is the RMS value of the noise estimated from DF 6