Semiconductor doping. Si solar Cell



Similar documents
Graduate Student Presentations

Conductivity of silicon can be changed several orders of magnitude by introducing impurity atoms in silicon crystal lattice.

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli

ELEC 3908, Physical Electronics, Lecture 15. BJT Structure and Fabrication

CONTENTS. Preface Energy bands of a crystal (intuitive approach)

AN900 APPLICATION NOTE

How To Implant Anneal Ion Beam

Lezioni di Tecnologie e Materiali per l Elettronica

Sheet Resistance = R (L/W) = R N L

Advanced VLSI Design CMOS Processing Technology

MOS (metal-oxidesemiconductor) 李 2003/12/19

Etching Etch Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between

Semiconductors, diodes, transistors

Grad Student Presentation Topics PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory

The MOSFET Transistor

Solar Photovoltaic (PV) Cells

Solid State Detectors = Semi-Conductor based Detectors

INTRODUCTION TO ION IMPLANTATION Dr. Lynn Fuller, Dr. Renan Turkman Dr Robert Pearson

Chapter 5. Second Edition ( 2001 McGraw-Hill) 5.6 Doped GaAs. Solution

The Physics of Energy sources Renewable sources of energy. Solar Energy

Lecture 12. Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12. ECE Dr. Alan Doolittle

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

Fabrication and Manufacturing (Basics) Batch processes

Chapter 11 PVD and Metallization

Chapter 5: Diffusion. 5.1 Steady-State Diffusion

Damage-free, All-dry Via Etch Resist and Residue Removal Processes

Optical Hyperdoping: Transforming Semiconductor Band Structure for Solar Energy Harvesting

CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor

3. Diodes and Diode Circuits. 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1

Implementation Of High-k/Metal Gates In High-Volume Manufacturing

The MOS Transistor in Weak Inversion

Sample Exercise 12.1 Calculating Packing Efficiency

Solid-State Physics: The Theory of Semiconductors (Ch ) SteveSekula, 30 March 2010 (created 29 March 2010)

Coating Technology: Evaporation Vs Sputtering

Module 7 Wet and Dry Etching. Class Notes

Development and Comparison of Small and Large Area Boron Doped Solar Cells in n-type and p-type Cz-Si

Characteristic curves of a solar cell

Process simulation. Maria Concetta Allia

A Plasma Doping Process for 3D FinFET Source/ Drain Extensions

Types of Epitaxy. Homoepitaxy. Heteroepitaxy

Results Overview Wafer Edge Film Removal using Laser

Project 2B Building a Solar Cell (2): Solar Cell Performance

Photovoltaics photo volt Photovoltaic Cells Crystalline Silicon Cells Photovoltaic Systems

Silicon-On-Glass MEMS. Design. Handbook

LAB IV. SILICON DIODE CHARACTERISTICS

Dry Etching and Reactive Ion Etching (RIE)

Contamination. Cleanroom. Cleanroom for micro and nano fabrication. Particle Contamination and Yield in Semiconductors.

VLSI Fabrication Process

Winbond W2E512/W27E257 EEPROM

Resistivity. V A = R = L ρ (1)

Theory of Transistors and Other Semiconductor Devices

Fabrication and Characterization of Schottky Diode

Improved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process

Crystalline solids. A solid crystal consists of different atoms arranged in a periodic structure.

Silicon Dioxide Layer Key to High Efficiency Crystalline Solar Cells

FEATURE ARTICLE. Figure 1: Current vs. Forward Voltage Curves for Silicon Schottky Diodes with High, Medium, Low and ZBD Barrier Heights

Deposition Overview for Microsytems

FUNDAMENTAL PROPERTIES OF SOLAR CELLS

High Open Circuit Voltage of MQW Amorphous Silicon Photovoltaic Structures

Fabrication of PN-Junction Diode by IC- Fabrication process

Defect Engineering in Semiconductors

UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES. Ex parte KEVIN MUKAI and SHANKAR CHANDRAN

High power picosecond lasers enable higher efficiency solar cells.

BJT Ebers-Moll Model and SPICE MOSFET model

OLED display. Ying Cao

MOS Capacitor CHAPTER OBJECTIVES

Laboratory #3 Guide: Optical and Electrical Properties of Transparent Conductors -- September 23, 2014

III. Wet and Dry Etching

SiC activities at Linköping University

Wafer Manufacturing. Reading Assignments: Plummer, Chap 3.1~3.4

Understanding the p-n Junction by Dr. Alistair Sproul Senior Lecturer in Photovoltaics The Key Centre for Photovoltaic Engineering, UNSW

Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors

ELECTRICAL CONDUCTION

EE 332 Photovoltaic Cell Design Iowa State University Electrical and Computer Engineering Dept

Figure Process flow from starting material to polished wafer.

Etching and Pattern Transfer (1) OUTLINE J / 3.155J -- Spring Term 2005 Lecture 12 - Etch and Pattern Transfer I (Wet Etch) 1.

Application Notes FREQUENCY LINEAR TUNING VARACTORS FREQUENCY LINEAR TUNING VARACTORS THE DEFINITION OF S (RELATIVE SENSITIVITY)

Lecture 15 - application of solid state materials solar cells and photovoltaics. Copying Nature... Anoxygenic photosynthesis in purple bacteria

Spectroscopic Ellipsometry:

Chapter 10 CVD and Dielectric Thin Film

ENEE 313, Spr 09 Midterm II Solution

Department of Physics Halvlederkomponenter

Peltier Application Note

Thin Is In, But Not Too Thin!

Study of tungsten oxidation in O 2 /H 2 /N 2 downstream plasma

Chapter Outline. Diffusion - how do atoms move through solids?

MICROPOSIT LOL 1000 AND 2000 LIFTOFF LAYERS For Microlithography Applications

Radiation Enhanced Diffusion of Nickel in Silicon Diodes

Chapter 10 Liquids & Solids

Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination

Introduction OLEDs OTFTs OPVC Summary. Organic Electronics. Felix Buth. Walter Schottky Institut, TU München. Joint Advanced Student School 2008

Diodes and Transistors

1700V Bi-Mode Insulated Gate Transistor (BIGT) on Thin Wafer Technology

ELG4126: Photovoltaic Materials. Based Partially on Renewable and Efficient Electric Power System, Gilbert M. Masters, Wiely

Silicon Wafer Solar Cells

BASIC LAB 1 INTRODUCTION TO BASIC PROCESS SIMULATION USING TSUPREM4 & TWB

Solar Energy Discovery Lab

Figure 1. Diode circuit model

University of California at Santa Cruz Electrical Engineering Department EE-145L: Properties of Materials Laboratory

COURSE: PHYSICS DEGREE: COMPUTER ENGINEERING year: 1st SEMESTER: 1st

Transcription:

Semiconductor doping Si solar Cell Two Levels of Masks - photoresist, alignment Etch and oxidation to isolate thermal oxide, deposited oxide, wet etching, dry etching, isolation schemes Doping - diffusion/ion implantation Metallization - Materials deposition, PVD, CVD

What s a metal, a semiconductor? IV How do we dope a semiconductor

Electrons and holes Conduction Band E D E c E A Valence Band E v

Sheet Resistance, what is it? What is the Resistance of this bar of material with resistivity ρ? W R = ρ L/Wt L We can rearrange to get a film dependent quantity called the Sheet Resistance R s = ρ/t =R / (L/W) Notice L/W is unit less, but gives us the number of squares in the length of the bar. The units of R s are ohms, but they are often given as Ω /. t

Sheet Resistance - Four Point Probe If Probe spacing is: Larger than film thickness Smaller than distance to edge of film Probe points are small Using a four point approach is a standard technique for eliminating the effects of contact resistance R s =4.53 V/I and ρ=r s t where t is thickness

How do we get the doping? R s and t give us ρ, which gives us doping (but we must know t)

Another way to get doping - from C-V of a diode Formation of a p-n junction Formation of a Schottky junction

1/C 2 vs V C -2 Slope gives carrier Concentration Assumes an abrupt junction - Schottky, p + n or n + p x-intercept give V v bi What if the line isn t straight?

How about the thickness of our Oxide? Again, C = εa/w, so we should have another way to measure W. In practice, we must be careful about what C we use. Corresponds to oxide thickness What about trapped charge?

Inversion in an MOS structure accumulation (negative bias) no bias inversion (positive bias)

What about I-V Characteristics? Forward biased pn junction: Probability that carriers are over the barrier is like a Boltzmann factor But, there is also an electric field pushing carriers back so at V = 0 there should be no current. We can write this in a simpler form as: What about when light is shining on the device? Note, there is a sign difference with respect to the capacitance analysis

How can we tell the carrier type Thermovoltage V Hot Probe e e e e e e e e Hall Effect carrier type mobility sheet concentration

Other methods of getting at the carriers SIMS RBS Rutherford Backscattering Polaron profiler Spreading Resistance...

Doping - reminder Goal of Doping: Substitution of atoms with excess or deficiency of valence electrons e.g. B or P substituting for Si Diffusion doping (in fact most doping) is typically done in two steps: (Almost all doping is now ion implantation) Predeposition - Use a source to create the desired dose Drive in - Source at surface removed, additional diffusion to get desired distribution (in ion implantation the anneal also removes damage and activates the dopant).

Generic Predeposition Process Deliver Dopants to Partially Masked Substrates Diffusion (Hot) Ion Implantation (Cold) Structure: Dopants Mask: Oxide, Nitride, Photoresist Silicon

Dopant delivery Options for Diffusion Gas Source: C B δ Nasty Gases: AsH 3, PH 3, B 2 H 6 Very similar to Deal Grove Oxidation C s x j C o Liquid Source: SOG: Spin-On Glass Doped SiO 2 dissolved in solvents Apply exactly like Photoresist C i Solid Source: Glass Discs (B 2 O 3, P 2 O 5 ) Close-space Sublimation Vapors sublime/diffuse/react Which is Best?

Drive-in - estimating the profile Fick s law - You need the PDE, but you also need the boundary conditions! C(z,0) = 0, Z 0 dc(0,t)/dz = 0 C(,t) = 0 0 C(z,t)dz = Q T Solution: C(z, t) = 2 -z Q T 4Dt πdt = constant e We can model the drive in step from our homework, here after a P predep with p8545 we had a sheet resistance of 12Ω/ and depth of 1.1µm. This gave a carrier concentration of 5x10 19 / cm 3 and a surface concentration of 5.5x10 15 /cm 2 Characteristic Length Scale - Diffusion Length

What about the diffusion Coefficient? Use first three terms in Fair s vacancy model. D = D o + n n i D + n n i 2 D 2 I told you to assume n~n i ~10 19 /cm 3 Is this reasonable? From Campbell table 3.2 (1100C=1373K) D o = 3.9cm 2 /s e -(3.66/k1373) = 1.43 x 10-13 cm 2 /s D - = 4.4cm 2 /s e -(4.0/k1373) = 9.13 x 10-15 cm 2 /s D 2- = 44cm 2 /s e -(4.37/k1373) = 4.00 x 10-15 cm 2 /s D = 1.56 x 10-13 cm 2 /s

Simulations Suprem-IV is a process simulation tool developed at Stanford University

nanohub TCAD tools https://nanohub.org/tools

Suprem simulation of boron predep and drive-in Boron Diffusion Log10(Boron) 20 15 10 5 0 0 2 4 Depth in microns Boron Predep 1100C 30 min. Boron drivein 1100C 30 min. Boron drivein 1100C 60 min. Boron drivein 1100C 60 min 200 angstrom oxide cap Boron predep in gas at 5 x 10 20 /cm 3 concentration followed by drive-ins. Effect of oxide cap on profile near the surface Boron Diffusion Why 5x10 20 /cm 3? 1) Damage threshold 2) Solubility limit 3) B partial pressure 1) Dimensional argument Log10(Boron) 21.0 20.5 20.0 19.5 19.0 18.5 18.0 0 0.5 1 1.5 2 2.5 Depth in microns

Solid Solubility, what is it? 1100C 5x10 20 /cm 3

Oxide is an effective anti-diffusion barrier for Si VLSI? 1) For boron but not for phosphorus 2) For phosphorus but not for boron 3) It works well for both 4) It depends

Final Topic on Diffusion: Oxide How fast do dopants diffuse through oxide? Diffusivity important, Solubility important Consider D o of Boron Si prefactor 0.37cm 2 /s Activation Energy 3.46eV SiO 2 prefactor 0.0003cm 2 /s Activation Energy 3.53eV Now D o of Phosphorous Si prefactor 3.9 cm 2 /s Activation Energy 3.66eV SiO 2 prefactor 0.19 cm 2 /s Activation Energy 4.03eV Oxide is often used as a diffusion mask- how thick does it need to be? Oxide is used for isolation - does it isolate? What is the thermal load? Oxide is also a gate dielectric with heavily B doped polysilicon gates - diffusion through gate is an issue M Metal O S Oxide Silicon Doped polysilicon

Suprem-IV Wet Oxide then Diffusion Oxide antidiffusion barrier 20 Log10(Boron) 15 10 5 60 min wet O2 at 1000C, 30 min boron predep at 1100C 30 minute boron predep at 1100C 0 Effect of oxide cap on profile near the surface 0 1 2 3 4 Depth in microns Substrate is P doped at 1 x 10 14 /cm 3, Wet oxide growth at atmospheric pressure for 60 minutes at 1000C, Boron predep from 30 minutes at 1100C in gas with a concentration of 5 x 10 20 /cc.

Simulation of predep and drive-in to find junction depth 1000 C P predep in p-type wafer doped at 1x10 17 /cm 3. 1100 C drive in. How long to get a 4.0µm deep junction?