AUTOMOTIVE GRADE AUIRFS845 AUIRFSL845 Features l Advanced Process Technology l New Ultra Low On-Resistance l 175 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax l Lead-Free, RoHS Compliant l Automotive Qualified * Description Specifically designed for Automotive applications, this HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and wide variety of other applications. Applications l Electric Power Steering (EPS) l Battery Switch l Start/Stop Micro Hybrid l Heavy Loads l DC-DC Applications G D S D V DSS S D G D 2 Pak AUIRFS845 HEXFET Power MOSFET R DS(on) typ. max. I D (Silicon Limited) I D (Package Limited) D S D G TO-262 AUIRFSL845 G D S Gate Drain Source 4V 1.9mΩ 2.3mΩ 193Ac 12A Base part number Package Type Standard Pack Complete Part Number Form Quantity AUIRFSL845 TO-262 Tube 5 AUIRFSL845 AUIRFS845 D2Pak Tube 5 AUIRFS845 Tape and Reel Left 8 AUIRFS845TRL Tape and Reel Right 8 AUIRFS845TRR Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (T A ) is 25 C, unless otherwise specified. Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon Limited) 193c I D @ T C = C Continuous Drain Current, V GS @ V (Silicon Limited) 137c I D @ T C = 25 C Continuous Drain Current, V GS @ V (Package Limited) 12 A I DM Pulsed Drain Current d 94 P D @T C = 25 C Maximum Power Dissipation 163 W Linear Derating Factor 1.1 W/ C V GS Gate-to-Source Voltage ± 2 V T J Operating Junction and -55 to + 175 T STG Storage Temperature Range Soldering Temperature, for seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw 3 lbfx in (1.1Nx m) C HEXFET is a registered trademark of International Rectifier. *Qualification standards can be found at http://www.irf.com/ 1
Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e E AS (tested) Single Pulse Avalanche Energy Tested Value l I AR Avalanche Currentd See Fig. 14, 15, 24a, 24b A E AR Repetitive Avalanche Energy d mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc Junction-to-Case kl.92 C/W R θja Junction-to-Ambient (PCB Mount) j 4 Static @ T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage 4 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.26 V/ C R DS(on) Static Drain-to-Source On-Resistance 1.9 2.3 mω V GS(th) Gate Threshold Voltage 2.2 3. 3.9 V I DSS I GSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage 1. Gate-to-Source Reverse Leakage 15 - µa na R G Internal Gate Resistance 2.3 Ω Dynamic @ T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance S Q g Total Gate Charge 7 161 Q gs Gate-to-Source Charge 29 Q gd Gate-to-Drain ("Miller") Charge 39 Q sync Total Gate Charge Sync. (Q g - Q gd ) 68 t d(on) Turn-On Delay Time 14 t r Rise Time 128 t d(off) Turn-Off Delay Time 55 t f Fall Time 77 C iss Input Capacitance 5193 C oss Output Capacitance 754 C rss Reverse Transfer Capacitance 519 C oss eff. (ER) Effective Output Capacitance (Energy Related) 878 C oss eff. (TR) Effective Output Capacitance (Time Related) 1225 nc ns pf 181 247 Conditions V GS = V, I D = 25µA Reference to 25 C, I D = 1.mAd V GS = V, I D = A g V DS = V GS, I D = µa V DS = 4V, V GS = V V DS = 4V, V GS = V, T J = 125 C V GS = 2V V GS = -2V Conditions V DS = V, I D = A I D = A mj V DS =2V V GS = V g I D = A, V DS =V, V GS = V V DD = 26V I D = A R G = 2.7Ω V GS = V g V GS = V V DS = 25V ƒ = 1. MHz, See Fig. 5 V GS = V, V DS = V to 32V i, See Fig. 11 V GS = V, V DS = V to 32V h 2
Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 193c (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 94 S (Body Diode)Ãd p-n junction diode. V SD Diode Forward Voltage.9 1.3 V T J = 25 C, I S = A, V GS = V g dv/dt Peak Diode Recovery f 1.7 V/ns T J = 175 C, I S = A, V DS = 4V t rr Reverse Recovery Time 44 T J = 25 C V R = 34V, ns 45 T J = 125 C I F = A Q rr Reverse Recovery Charge 44 T J = 25 C di/dt = A/µs g nc 46 T J = 125 C I RRM Reverse Recovery Current 1.9 A T J = 25 C t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 12A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-114) Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting T J = 25 C, L =.36mH, R G = 5Ω, I AS = A, V GS =V. Part not recommended for use above this value. I SD A, di/dt 1295A/µs, V DD V (BR)DSS, T J 175 C. Pulse width 4µs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. ˆ When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. R θ is measured at T J approximately 9 C. Š R θjc value shown is at time zero. 3
C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) AUIRFS/SL845 VGS TOP 15V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V VGS TOP 15V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V 4.5V 6µs PULSE WIDTH Tj = 25 C 1.1 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 4.5V 6µs PULSE WIDTH Tj = 175 C.1 1 V DS, Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics 2. 1.8 I D = A V GS = V T J = 175 C 1.6 1.4 T J = 25 C 1.2 1. V DS = V 6µs PULSE WIDTH 1. 2 3 4 5 6 7 8 9 V GS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics.8.6-6 -4-2 2 4 6 8 12141618 T J, Junction Temperature ( C) Fig 4. Normalized On-Resistance vs. Temperature V GS = V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd C iss 14. 12.. 8. I D = A V DS = 32V V DS = 2V C oss C rss 6. 4. 2. 1 V DS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage. 2 4 6 8 12 14 Q G, Total Gate Charge (nc) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 4
Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) Drain-to-Source Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) AUIRFS/SL845 OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 175 C 1msec µsec T J = 25 C Limited by package msec 1. 2 15 V GS = V.2.6 1. 1.4 1.8 2.2 V SD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Limited By Package 1 Tc = 25 C DC Tj = 175 C Single Pulse.1.1 1 V DS, Drain-to-Source Voltage (V) 5 48 Fig 8. Maximum Safe Operating Area Id = 1.mA 46 44 5 42 25 5 75 125 15 175 T C, Case Temperature ( C).9.8.7.6.5.4.3.2 Fig 9. Maximum Drain Current vs. Case Temperature 4-6 -4-2 2 4 6 8 12141618 T J, Temperature ( C ) 8 7 6 5 4 3 2 Fig. Drain-to-Source Breakdown Voltage I D TOP 17A 36A BOTTOM A.1 5. -5 5 15 2 25 3 35 4 45 25 5 75 125 15 175 V DS, Drain-to-Source Voltage (V) Starting T J, Junction Temperature ( C) Fig 11. Typical C OSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
E AR, Avalanche Energy (mj) Avalanche Current (A) AUIRFS/SL845 Thermal Response ( Z thjc ) C/W 1 D =.5.1.1.2..5.2.1 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc.1 1E-6 1E-5.1.1.1.1 1 t 1, Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 15 C and Tstart =25 C (Single Pulse).1.5. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τj = 25 C and Tstart = 15 C. 1 1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 tav (sec) Fig 14. Typical Avalanche Current vs.pulsewidth 2 18 16 14 12 8 6 4 2 TOP Single Pulse BOTTOM 1.% Duty Cycle I D = A Notes on Repetitive Avalanche Curves, Figures 14, 15 (For further info, see AN-5 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 24a, 24b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 14, 15). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 13) Fig 15. Maximum Avalanche Energy vs. Temperature 6 25 5 75 125 15 175 Starting T J, Junction Temperature ( C) P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc I av = 2DT/ [1.3 BV Z th ] E AS (AR) = P D (ave) t av
I RRM (A) Q RR (nc) I RRM (A) Q RR (nc) R DS(on), Drain-to -Source On Resistance (m Ω) V GS(th), Gate threshold Voltage (V) AUIRFS/SL845 8. I D = A 4.5 4. 6. 3.5 3. 4. 2. T J = 125 C 2.5 2. I D = µa I D = 1.mA I D = 1.A T J = 25 C 1.5. 4 6 8 12 14 16 18 2 V GS, Gate -to -Source Voltage (V) 1. -75-5 -25 25 5 75 125 15 175 T J, Temperature ( C ) Fig 16. On-Resistance vs. Gate Voltage Fig 17. Threshold Voltage vs. Temperature I F = 6A 2 I F = 6A 8 V R = 34V T J = 25 C T J = 125 C 15 V R = 34V T J = 25 C T J = 125 C 6 4 2 5 2 4 6 8 di F /dt (A/µs) Fig. 18 - Typical Recovery Current vs. di f /dt 2 4 6 8 di F /dt (A/µs) Fig. 19 - Typical Stored Charge vs. di f /dt 12 I F = A 2 I F = A 8 V R = 34V T J = 25 C T J = 125 C 15 V R = 34V T J = 25 C T J = 125 C 6 4 2 5 7 2 4 6 8 2 4 6 8 di F /dt (A/µs) di F /dt (A/µs) Fig. 2 - Typical Recovery Current vs. di f /dt Fig. 21 - Typical Stored Charge vs. di f /dt
R DS (on), Drain-to -Source On Resistance ( mω) AUIRFS/SL845 6 5 4 V GS = 5.5V V GS = 6.V V GS = 7.V V GS = 8.V V GS =V 3 2 2 3 4 5 I D, Drain Current (A) Fig 22. Typical On-Resistance vs. Drain Current 8
+ - D.U.T + ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - + Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD + - Re-Applied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 23. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs 15V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T IAS.1Ω + - V DD A I AS Fig 24a. Unclamped Inductive Test Circuit Fig 24b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 9% R G + - V DD VV GS Pulse Width 1 µs Duty Factor.1 % % V GS t d(on) t r t d(off) t f Fig 25a. Switching Time Test Circuit Fig 25b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 5KΩ Vgs 12V.2µF.3µF V GS D.U.T. + V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr 9 Fig 26a. Gate Charge Test Circuit Fig 26b. Gate Charge Waveform
D 2 Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D 2 Pak (TO-263AB) Part Marking Information Part Number IR Logo AUIRFS845 YWWA XX or XX Date Code Y= Year WW= Work Week A= Automotive, LeadFree Lot Code Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information Part Number IR Logo AUIRFSL845 YWWA XX or XX Date Code Y= Year WW= Work Week A= Automotive, LeadFree Lot Code Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 11
D 2 Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.6 (.63) 1.5 (.59) 4. (.161) 3.9 (.153) 1.6 (.63) 1.5 (.59).368 (.145).342 (.135) FEED DIRECTION 1.85 (.73) 1.65 (.65) 11.6 (.457) 11.4 (.449) 15.42 (.69) 15.22 (.61) 24.3 (.957) 23.9 (.941) TRL.9 (.429).7 (.421) 16. (.634) 15.9 (.626) 1.75 (.69) 1.25 (.49) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.5 (.532) 12.8 (.54) 27.4 (1.79) 23.9 (.941) 4 33. (14.173) MAX. 6. (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.4 (1.39) 24.4 (.961) 3 3.4 (1.197) MAX. 4 12
Qualification Information Qualification Level Automotive (per AEC-Q1) Comments: This part number(s) passed Automotive qualification. IR s Industrial and Consumer qualification level is granted by extension of the higher Automotive level. ESD RoHS Compliant TO-262 N/A D 2 PAK MSL1 Machine Model Class M3 (+/- 4V) AEC-Q1-2 Human Body Model Class H1C (+/- 2V) AEC-Q1-1 Charged Device Model Class C5 (+/- 2V) AEC-Q1-5 Yes Qualification standards can be found at International Rectifier s web site: http//www.irf.com/ Highest passing voltage. 13
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