74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register



Similar documents
74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

74AC191 Up/Down Counter with Preset and Ripple Clock

DM74LS05 Hex Inverters with Open-Collector Outputs

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

DM74LS00 Quad 2-Input NAND Gate

74AC138 74ACT138 1-of-8 Decoder/Demultiplexer


74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

CD4013BC Dual D-Type Flip-Flop

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

MM74C74 Dual D-Type Flip-Flop

MM74HC273 Octal D-Type Flip-Flops with Clear

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate

MM74HC174 Hex D-Type Flip-Flops with Clear

DM74LS151 1-of-8 Line Data Selector/Multiplexer

74AC139 74ACT139 Dual 1-of-4 Decoder/Demultiplexer

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer

CD4013BC Dual D-Type Flip-Flop

DM74LS157 DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers

DM74LS153 Dual 1-of-4 Line Data Selectors/Multiplexers

MM74HC14 Hex Inverting Schmitt Trigger

CD4043BC CD4044BC Quad 3-STATE NOR R/S Latches Quad 3-STATE NAND R/S Latches

MM74HC4538 Dual Retriggerable Monostable Multivibrator

DM Segment Decoder/Driver/Latch with Constant Current Source Outputs

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs

DM74121 One-Shot with Clear and Complementary Outputs

5495A DM Bit Parallel Access Shift Registers

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer

DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM74157 Quad 2-Line to 1-Line Data Selectors/Multiplexers

74F168*, 74F169 4-bit up/down binary synchronous counter

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook.

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control

NM93CS06 CS46 CS56 CS Bit Serial EEPROM with Data Protect and Sequential Read

DM54LS260 DM74LS260 Dual 5-Input NOR Gate

5485 DM5485 DM Bit Magnitude Comparators

Obsolete Product(s) - Obsolete Product(s)

54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock

54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter

CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14-Stage Ripple Carry Binary Counters

DM74184 DM74185A BCD-to-Binary and Binary-to-BCD Converters

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook Jun 30

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset

74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

CD4008BM CD4008BC 4-Bit Full Adder

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

Features. Instruction. Decoder Control Logic, And Clock Generators. Address Compare amd Write Enable. Protect Register V PP.

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION

54157 DM54157 DM74157 Quad 2-Line to 1-Line Data Selectors Multiplexers

Quad 2-Line to 1-Line Data Selectors Multiplexers

Description. Table 1. Device summary. Order code Temperature range Package Packing Marking

74VHC112 Dual J-K Flip-Flops with Preset and Clear

MC74AC138, MC74ACT of-8 Decoder/Demultiplexer

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648 SOIC D SUFFIX CASE 751B

Features. Applications

SN54/74LS192 SN54/74LS193

1 TO 4 CLOCK BUFFER ICS551. Description. Features. Block Diagram DATASHEET

74HC595; 74HCT General description. 2. Features and benefits. 3. Applications

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register

INTEGRATED CIRCUITS. 74F153 Dual 4-line to 1-line multiplexer. Product specification 1996 Jan 05 IC15 Data Handbook

Link-65 MHz, +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

Semiconductor MSM82C43

CD4511BM CD4511BC BCD-to-7 Segment Latch Decoder Driver

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

MC14175B/D. Quad Type D Flip-Flop

74HC595; 74HCT General description. 2. Features and benefits. 3. Applications

How to Read a Datasheet

PHOTOTRANSISTOR OPTOCOUPLERS

HCF4010B HEX BUFFER/CONVERTER (NON INVERTING)

MC14008B. 4-Bit Full Adder

HCC/HCF4032B HCC/HCF4038B

CAT28C64B F R E E. 64K-Bit CMOS PARALLEL EEPROM L E A D FEATURES DESCRIPTION BLOCK DIAGRAM

High-Speed, Low r ON, SPST Analog Switch (1-Bit Bus Switch)

. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP.

HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION

Features INSTRUCTION DECODER CONTROL LOGIC AND CLOCK GENERATORS COMPARATOR AND WRITE ENABLE EEPROM ARRAY READ/WRITE AMPS 16

MC14001B Series. B Suffix Series CMOS Gates MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B

MM54C150 MM74C Line to 1-Line Multiplexer

HCF4001B QUAD 2-INPUT NOR GATE

DG2302. High-Speed, Low r ON, SPST Analog Switch. Vishay Siliconix. (1-Bit Bus Switch with Level-Shifter) RoHS* COMPLIANT DESCRIPTION FEATURES

ICS514 LOCO PLL CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

MC10SX1190. Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit

74HC165; 74HCT bit parallel-in/serial out shift register

HCF4028B BCD TO DECIMAL DECODER

LM78XX Series Voltage Regulators

1-Mbit (128K x 8) Static RAM

Fairchild Solutions for 133MHz Buffered Memory Modules

HCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

Transcription:

74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description The 74F675A contai a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pi are provided for expaion to longer words. By mea of a separate clock, the contents of the shift register are traferred to the storage register. The contents of the storage register can also be loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel loading. Ordering Code: Features April 1988 Revised October 2000 Serial-to-parallel converter 16-Bit serial I/O shift register 16-Bit parallel out storage register Recirculating parallel trafer Expandable for longer words Slim 24 lead package 74F675A version prevents false clocking through CS or R/W inputs Order Number Package Number Package Description 74F675ASC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F675APC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide 74F675ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Logic Symbols 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register IEEE/IEC Connection Diagram 2000 Fairchild Semiconductor Corporation DS009587 www.fairchildsemi.com

74F675A Unit Loading/Fan Out U.L. Input I IH /I IL Pin Names Description HIGH/LOW Output I OH /I OL SI Serial Data Input 1.0/1.0 20 µa/ 0.6 ma CS Chip Select Input (Active LOW) 1.0/1.0 20 µa/ 0.6 ma SHCP Shift Clock Pulse Input (Active Falling Edge) 1.0/1.0 20 µa/ 0.6 ma STCP Store Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µa/ 0.6 ma R/W Read/Write Input 1.0/1.0 20 µa/ 0.6 ma SO Serial Data Output 50/33.3 1 ma/20 ma Q 0 Q 15 Parallel Data Outputs 50/33.3 1 ma/20 ma Functional Description The 16-Bit shift register operates in one of four modes, as determined by the signals applied to the Chip Select (CS), Read/Write (R/W) and Store Clock Pulse (STCP) input. State changes are indicated by the falling edge of the Shift Clock Pulse (SHCP). In the Shift Right mode, data enters D 0 from the Serial Input (SI) pin and exits from Q 15 via the Serial Data Output (SO) pin. In the Parallel Load mode, data from the storage register outputs enter the shift register and serial shifting is inhibited. The storage register is in the Hold mode when either CS or R/W is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register on the rising edge of STCP. To prevent false clocking of the shift register, SHCP should be in the LOW state during a LOW-to-HIGH traition of CS. To prevent false clocking of the storage register, STCP should be LOW during a HIGH-to-LOW traition of CS if R/W is LOW, and should also be LOW during a HIGH-to-LOW traition of R/W if CS is LOW. Shift Register Operatio Table Control Inputs Operating CS R/W SHCP STCP Mode H X X X Hold L L X Shift Right L H L Shift Right L H H Parallel Load, No Shifting Logic Diagram Storage Register Operatio Table Inputs Operating CS R/W STCP Mode H X X Hold L H X Hold L L Parallel Load H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = HIGH-to-LOW Traition = LOW-to-HIGH Traition Please note that this diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays. www.fairchildsemi.com 2

Absolute Maximum Ratings(Note 1) Storage Temperature 65 C to +150 C Ambient Temperature under Bias 55 C to +125 C Junction Temperature under Bias 55 C to +150 C V CC Pin Potential to Ground Pin 0.5V to +7.0V Input Voltage (Note 2) 0.5V to +7.0V Input Current (Note 2) 30 ma to +5.0 ma Voltage Applied to Output in HIGH State (with V CC = 0V) Standard Output 0.5V to V CC 3-STATE Output 0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (ma) Recommended Operating Conditio Free Air Ambient Temperature Supply Voltage 0 C to +70 C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditio is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. 74F675A DC Electrical Characteristics Symbol Parameter Min Typ Max Units V CC Conditio V IH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal V IL Input LOW Voltage 0.8 V Recognized as a LOW Signal V CD Input Clamp Diode Voltage 1.2 V Min I IN = 18 ma V OH Output HIGH 10% V CC 2.5 I OH = 1 ma V Min Voltage 5% V CC 2.7 I OH = 1 ma V OL Output LOW Voltage 10% V CC 0.5 V Min I OL = 20 ma I IH Input HIGH Current 5.0 µa Max V IN = 2.7V I BVI Input HIGH Current Breakdown Test 7.0 µa Max V IN = 7.0V I CEX Output HIGH Leakage Current 50 µa Max V OUT = V CC V ID Input Leakage I ID = 1.9 µa 4.75 V 0.0 Test All Other Pi Grounded I OD Output Leakage V IOD = 150 mv 3.75 µa 0.0 Circuit Current All Other Pi Grounded I IL Input LOW Current 0.6 ma Max V IN = 0.5V I OS Output Short-Circuit Current 60 150 ma Max V OUT = 0V I CCH Power Supply Current 106 160 ma Max V O = HIGH I CCL Power Supply Current 106 160 ma Max V O = LOW 3 www.fairchildsemi.com

74F675A AC Electrical Characteristics T A = +25 C T A = 0 C to +70 C V CC = +5.0V V CC = +5.0V Symbol Parameter Units C L = 50 pf C L = 50 pf Min Typ Max Min Max f MAX Maximum Clock Frequency 100 130 85 MHz t PLH Propagation Delay 3.0 8.0 10.5 2.5 12.0 t PHL STCP to Q n 3.0 10.5 13.5 2.5 15.0 t PLH Propagation Delay 4.0 7.0 9.5 3.5 10.5 t PHL SHCP to SO 4.5 8.0 10.5 4.0 12.0 AC Operating Requirements T A = +25 C T A = 0 C to +70 C Symbol Parameter V CC = +5.0V V CC = +5.0V Units Min Max Min Max t S (H) Setup Time, HIGH or LOW 3.5 4.0 t S (L) CS or R/W to STCP 5.5 6.5 t H (H) Hold Time, HIGH or LOW 0 0 t H (L) CS or R/W to STCP 0 0 t S (H) Setup Time, HIGH or LOW 3.0 3.5 t S (L) SI to SHCP 3.0 3.5 t H (H) Hold Time, HIGH or LOW 3.0 3.5 t H (L) SI to SHCP 3.0 3.5 t S (H) Setup Time, HIGH or LOW 6.5 7.5 t S (L) R/W to SHCP 9.0 10.0 t H (H) Hold Time, HIGH or LOW 0 0 t H (L) R/W to SHCP 0 0 t S (H) Setup Time, HIGH or LOW 7.0 8.0 t S (L) STCP to SHCP 7.0 8.0 t H (H) Hold Time, HIGH or LOW 0 0 t H (L) STCP to SHCP 0 0 t S (H) Setup Time, HIGH or LOW 3.0 3.5 t S (L) CS to SHCP 3.0 3.5 t H (H) Hold Time, HIGH or LOW 3.0 3.5 t H (L) CS to SHCP 3.0 3.5 t W (H) SHCP Pulse Width 5.0 6.0 t W (L) HIGH or LOW 5.0 6.0 t W (H) STCP Pulse Width 6.0 7.0 t W (L) HIGH or LOW 5.0 6.0 t S (L) SHCP to STCP 8.0 9.0 t H (H) SHCP to STCP 0.0 0.0 www.fairchildsemi.com 4

Physical Dimeio inches (millimeters) unless otherwise noted 74F675A 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide Package Number N24A 5 www.fairchildsemi.com

74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com