3.1 Etching wet etching, micromachining, dry etching, applications, diagnostics and end point detection, challenges in dry etching

3.0 Etching and Chemo-Mechanical Polishing 3.1 Etching wet etching, micromachining, dry etching, applications, diagnostics and end point detection, challenges in dry etching 3.2 Chemo-Mechanical Polishing (CMP) mechanisms, dielectric CMP, metal CMP, commercial CMP tools, endpoint detection, pads, slurry, post CMP cleaning, CMP issues Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.1

3.1 Etching - Introduction There are two types of etching mechanisms: Physical etching (or sputter etch, and relies on momentum transfer from particles hitting and eroding the surface) and wet/dry chemical etching (where reaction products formed are either soluble in the etch solution or volatile at low pressures). The removal of material from a substrate by chemical reaction or by ion bombardment is referred to as an etch process. The material that is not masked is removed resulting in patterned regions. The rate of material removal is known as etch rate (ER) and is the thickness removed per unit time (nm/min). For high production throughput, we need etch rates above 50 nm/min. Depending on the etch process and material, the etching can occur in both horizontal and vertical directions. The anisotropy of an etch process is given by A = 1 (ER L /ER V ) ER L = lateral etch rate, ER V = vertical etch rate. Chemical etch processes are typically isotropic; ER L = ER V and A = 0. The effect of an isotropic etch rate is to create undercuts below the mask see Fig. 3.1. An ideal etch process would transfer the pattern on the mask to the underlying film with zero lateral etch, creating a vertical profile. Fig 3.1 Comparison of anisotropic and isotropic processes. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.2

Introduction (contd.) Typically the masking material as well as substrate are also attacked by the etch process. The ratio of etch rates of different materials is called the selectivity of an etch process. High selectivity between masking and substrate materials is critical if the masking material is etched too quickly, control over the feature size is lost. And to cope with film thickness and etch rate non-uniformities, overetching must be performed to ensure the film is etched completely on the whole wafer. Wet Etching A purely chemical process which consists of three different steps - reactive species present in the solution move to the wafer surface, reaction yields soluble etch products, movement of etch products away from the surface. There are a large number of recipes that exist to etch virtually every material, and they can be tailored to have high selectivity. Any damage induced to the substrate by the wet etch process is very low. The concentration of the etch solution has to be tightly controlled on a microscopic scale to have constant and uniform etch rate over large areas. Agitation and cycling of the solution or even continuous spraying of the solution is employed at automated etch stations. High purity chemicals and filtration is needed to avoid particle contamination of the surface. The drawback of wet etching is the large consumption of chemicals and the handling of toxic waste. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.3

Wet Etching (contd.) Etch solutions with orientation dependence have been developed that etch certain crystal planes faster than others. This type of etch process is anisotropic and is widely used for fabrication of MEMS. The anisotropy comes from the different density of atoms and bond strength in the different planes. The Si unit cell is shown in Fig. 3.2. The highest density of atoms for silicon is found in the <111> direction this is difficult to see even in a 3-D model of silicon. On a (111) surface, there is just one Si dangling bond on the surface, as compared to two potential dangling bonds on the (110) and (100) surfaces. For example, a 1:1 solution of KOH and water with propanol added, etches the Si <100> plane hundred times faster than the <111> plane. Due to the crystal face selectivity, the etch rate virtually stops on <111> planes and the etch depth is determined only by the mask opening and the etch time. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.4

Wet Etching (contd.) Fig. 3.2 The major crystal planes in silicon true for simple cubic lattice systems. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.5

Wet Etching (contd.) Fig. 3.3 Isotropic etching of silicon with HNA. Fig. 3.4 Anisotropic etching of silicon, with e.g. ethylenediamine (EDA), KOH, TMAH, etc. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.6

Wet (Anisotropic) Etching (contd.) Fig. 3.5 Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.7

Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.8

Bulk and Surface Micromachining Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.9

Examples Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.10

Examples (contd.) Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.11

Important Materials and Etch Solutions in IC Processing An important wet etch process is the removal of native oxide (SiO 2 ) in a dilute solution of hydrofluoric acid (HF) as it offers high selectivity to Si (about 1:100). The masking material here can be photoresist. To maintain a constant HF concentration and in turn a constant etch rate, buffered solutions (BHF) are used. Ammonium fluoride as a buffering agent maintains a constant HF concentration. The photoresist mask must be removed after each patterning step. Standard wet stripping techniques can be used although dry ashing in an oxygen plasma is an option. Strippers can be organic or inorganic. Organic strippers break down the structure of the resist material and remove any residue from the wafer surface. Inorganic strippers are oxidising agents e.g. solution of H 2 SO 4 and H 2 O 2. When heated to higher temperatures (>120C), even hardened resist can be removed residue-free. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.12

Dry Etching Plasma-assisted etching techniques make use of partially ionized gases produced in low pressure (1 microbar 10mbar) discharges, where ions, electrons, and activated neutrals are produced from relatively inert molecular gases. Two distinctly different etch mechanisms are encountered in dry etching see Fig. 3.6. In the sputter etch process, ions of inert gases like argon are accelerated to the surface. Due to momentum transfer, atoms are knocked off. The etch products are not volatile and the process is not selective. In the chemical etching process volatile products are formed, and the process is selective. Examples include silicon etching in a fluorine atmosphere or photoresist mask removal (or dry ashing) in an oxygen ambient. Fig. 3.6 Sputtering and chemical etching regimes. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.13

Dry Etching (contd.) In reactive ion etching (RIE), a combination of sputter etch and chemical etch processes are used. Inert gases, reactive gases containing fluorine, chlorine, bromine, or oxygen are used. Ions are accelerated and their role can be to make the surface more reactive (by slight damage of the surface) or to supply additional energy for etch products to desorb from the surface. As the gas phase can react more readily and form volatile etch products, the etch rate increases. Fig. 3.7 Reactive ion etching. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.14

Dry Etch - Applications Si-Gate Etch Principal gate material is either poly-si or a compound gate stack of tungsten silicide (WSi x ) and poly-si to lower interconnect resistance. The etch process needs to control the etched profile, etch selectivity, and the critical dimension (gate length), regardless of doping (dual-doped n and p poly-si). Fluorine-containing gas is used to minimise n/p profile differences see Fig. 3.8. Fig. 3.8 SEM micrograph of gate etch. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.15

Etching Applications (contd.) Deep Trench in Si Deep-trench storage node capacitor is used in some DRAM structures. Trench etching is typically carried out with a SiO 2 hard mask. The process must provide high etch rate, high anisotropy (for high aspect ratios 30:1), and control of taper angles to very tight limits. Taper angles can be controlled by the O 2 partial pressure in a HBr/NF 3 /Cl 2 etching process and the wafer surface temperature. The oxygen react with exposed Si to form a SiO x layer which is not etched by the halogen chemistry. Also, the etch products (mainly SiBr y, SiCl z ) are incorporated in this sidewall and help reduce sidewall etching. The passivation at the bottom of the feature gets destroyed by the high arriving rate and energy of impinging ions. Thus the etch process becomes highly anisotropic. The etch rate is controlled by the plasma density and ion energy. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.16

Etching Applications (contd.) Deep Reactive Ion Etching (DRIE) of Si In MEMS applications, bulk micromachining of Si with very high aspect ratios (deep channels with small lateral opening) are needed to realize devices such as gyroscopes, suspended seismic masses, or rotor blades see Fig. 3.9. The DRIE process was invented by Bosch in 1993 used to be called the Bosch process. Surface Technology Systems continued to develop the technology, enhanced the method, and launched the Advanced Silicon Etch (ASE) process. Fig. 3.9 MEMS structures realized by DRIE. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.17

Etching Applications - Si DRIE (contd.) The ASE process has three alternating passivation and etch steps see Fig. 3.10: Passivation step at the beginning of each cycle, a C 4 F 8 based plasma is used to conformally deposit a few monolayers of PTFE-type fluorocarbon across all surfaces exposed to the plasma. Etch step 1 the plasma is switched to SF 6 - an isotropic Si etchant. DC bias on the wafer increases ion energy in the vertical direction consequently increasing the etch rate on surfaces parallel to the wafer surface. Etch step 2 following selective polymer removal, the Si at the base of the trench is exposed to the SF 6 plama but sidewalls are protected by the PTFE. This cycle is repeated and by careful control of etch time, high aspect ratio trenches are possible but control over feature size is not tight. Fig. 3.10 Mechanisms underlying the DRIE process. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.18

Etching Applications (contd.) Dielectrics Etching dielectrics such as silicon dioxide or silicon nitride typically rely on competing processes (of polymer deposition and reactive ion etching) to achieve vertical sidewalls and etch stopping at underlying layers. Vertical profiles are achieved by sidewall passivation by introducing carbon-containing fluorine species (e.g. CF 4, CHF 3, C 4 F 8 ) into the plasma. Anisotropic dielectric etching is done in two ways use of dielectric as a masking layer for patterning underlying layers (e.g. deep trench example earlier) or a dielectric is patterned using another dielectric as an etch stop (e.g. contact hole formation see Fig. 3.11). Here selectivity is the biggest concern since the etch process must be chosen to provide sufficient polymerization on the silicon nitride. Fig. 3.11 Schematic and cross section of contact structure. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.19

Etching Applications (contd.) Metals Interconnect metallization is generally Al (with 0.5% Cu). Critical aspects of etching are profile control and corrosion prevention of the metal after etching. Fluorine based chemistries cannot be used to etch Al because of formation of the non-volatile AlF 3. On the other hand Cl 2 etches pure Al even at room temperature to form Al 2 Cl 6. Thus chlorine based chemistries are very common despite being more hazardous than fluorine based chemistries. The main difficulty in etching Al lies in the formation of native oxide (~ 3nm Al 2 O 3 ) on its surface. To break the Al 2 O 3, a reducing chemistry and ion bombardment is needed can be achieved with BCl 3 and Cl 2. Unfortunately the etched wafer can corrode by reacting with oxygen and water. Reacting with water forms Levis acids with residual chlorine on the metal surface. Typically before exposing wafer to atmosphere, the resist is removed by plasma ashing or the Cl can be replaced with F by exposing wafer to F plasma. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.20

Etching Applications (contd.) Compound Semiconductors This family includes semiconductors such as GaAs or AlGaAs and they are widely used in optoelectronics devices such as lasers, transistors, waveguides, distributed Bragg reflectors (DBR) which can formed on the same chip. Smooth sidewalls for these devices are extremely important to minimize optical scattering/loss difficult to achieve particularly for deep structures. Figure 3.12 shows an example of a 5 micron high reflector made of GaAs/AlGaAs heterostructure. Typical etch chemistries are based on chlorine or CH 4 /H 2 gas mixtures. Fig. 3.12 SEM of 5 micron deep GaAs/AlGaAs ICP etch using a Cl chemistry. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.21

Etching Applications (contd.) Photoresist Ashing and Polymer Removal The masking material (photoresist) must be removed after etching. It can stripped using wet agents like acetone or by subjecting it to an oxygen plasma (ashing). Even after this step, there remains the (Si x Cl y Br z -rich) polymer formation created by the etch process see Fig. 3.13. The wafer can be treated with a CF 4 plasma using an Aspen Strip ICP system. Fig. 3.13 SEM of 5 micron deep GaAs/AlGaAs ICP etch using a Cl chemistry. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.22

Plasma Diagnostics To gain more knowledge about the process the plasma must be monitored to gain control of the process for reproducibility, machine portability, and to derive an end point signal to stop the process at the desired etch depth. Various methods can be used. Optical emission spectroscopy collects the light emitted from the plasma. Changes in the signal intensity associated with film clearing off or etch start of the underlying film. Can even get spatial information over the wafer through use of optical fibre. Fig. 3.14 Endpoint signal from OES. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.23

Plasma Diagnostics (contd.) Interferometry by directing monochromatic light from a laser onto the wafer surface and recombining the reflected light beam with a reference beam. The resulting modulation of the recombined intensity (due to interference) is monitored as the film is etched. The film thickness, d, can be calculated using the equation: d = λ / [ 2n cos φ ] where φ = angle of incident beam from normal incidence, n the refractive index of film, and λ the wavelength. Mass spectroscopy allows for a direct sampling of the species in the plasma. Enables measurement of ions and their energy distribution. Great feedback tool for process control and insight into reaction mechanisms. Electrical measurements direct measurement can be done at the generator (of its power output, reflected power, phase shift) or at the wafer electrode in the chamber (of its DC bias and RF peak-to-peak voltage). A far more sophisticated measurement involves use of Langmuir probes (inserted into the plasma itself) which provide a non-destructive measurement of the electron density, electron temperature, and plasma potentials. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.24

Challenges in Dry Etching Feature size control with increase in wafer sizes and reduction in feature size intraand inter-wafer reproducibility is critical. The etch rate depends on various factors and primarily on see Fig. 3.15: Macroscopic loading number of wafers in reactor chamber. Microscopic loading local feature density on the wafer where etch areas of different features are different. Thus consumption of etch species are different. Aspect ratio dependent etch (ARDE) the smaller (and deeper) the feature size becomes, the harder it is for enough species to get to the bottom of the feature and for removal of etch products. Fig. 3.15 Effects of microloading and ARDE. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.25

3.2 Chemo-Mechanical Polishing (CMP) Enables the integration of more metal layers onto the chip. With increasing number of dielectricmetal layers, the surface becomes highly uneven, which causes varying metal cross sections (varying metal resistivities) and suffers from the small depth of focus of modern lithography. CMP has been employed for several years now to provide the global planarization required by advanced IC designs see Fig. 3.16. CMP makes Moore s Law possible! In a CMP process, the wafer is mounted face down in a carrier assembly held above a moving polishing pad. The carrier and wafer are rotated and a chemically active abrasive liquid called slurry is introduced onto the pad. The carrier assembly is then pressed down bringing the wafer in contact with the pad and slurry. The chemical mechanical action results in selective removal of material from the raised feature (high spots) on the wafer and the film being polished becomes planarized. Fig. 3.16 TSMC s first 0.13 micron mixed-signal process with 8 levels of CMP Cu/oxo-silicate glass. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.26

CMP Mechanisms Consists of two components: chemical etching and mechanical abrasion in the right balance. Not so simple because mechanisms can be quite complex! Mechanisms differ by film and slurry type and depend on a number of process parameters, which include: down force (force applied between the wafer and pad), pad velocity and hardness, slurry type (chemistry, PH, particle type), slurry delivery rate, slurry distribution, temperature, configuration of polishing tool, etc. Polishing Pads Made of polyurethane (some sort of synthetic rubber) coated material and its surface may be smooth or grooved and/or pored. Grooves and pores aid the distribution of slurry across the pad. Harder/stiffer pads provide better local planarization whereas softer pads provide better uniformity of removal rate. Pad conditioning is a critical aspect of CMP - the pad surface can become glazed during the polishing surface. The conditioning process involves sweeping the surface of the pad with a pad conditioner whose surface is impregnated with diamonds fancy sandpaper! Slurry A stabilised suspension of small (<100nm) abrasive particles in water with some dissolved chemicals most common are alumina or silica for metal CMP and silica or cerium oxide (ceria) for oxide CMP. The particles must be of the same hardness as the material to be polished. The purpose of the dissolved chemicals is to better the wetting conditions, modify the polished surface, stabilize the suspension, influence the friction coefficient, dissolve process by-products. Slurry management is critical particles can agglomerate into clusters and they can settle at the bottom of the storage container. But at PH > 7.5, silica particles attain sufficient charge to generate electrostatic repulsion and maintain particle dispersion. Slurries have finite shelf life ranging from 1 week to several months after this agglomeration level becomes excessive! Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.27

Dielectric CMP Mechanisms for CMP of SiO 2 not well understood but similarities exist between CMP of SiO 2 and the polishing of optical glass. Following Preston s Law developed for polishing of optical glass, the polishing rate, R p (thickness removed per unit time), is defined as R p = K p P ν where K p is Preston s coefficient and a strong function of the process conditions, P the applied pressure, and ν the linear velocity. The basic principle of polishing is that there is formation of a hydrated layer by means of a chemical reaction between the glass surface and water, followed by removal of hydrated layer by the abrasive particles. Dielecric CMP is typically used in trench isolation applications see Fig. 3.17. Fig. 3.17 Simplified (shallow) trench isolation process (a) etching of trenches with nitride mask, (b) filling with CVD glass, (c) planarization and subsequent stripping of nitride mask. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.28

Metal CMP Mechanisms for CMP of (W, Cu) are relatively simple in comparison to those of SiO 2. In general the surface of the metal is first chemically oxidized, and then the metal oxide is mechanically removed from the surface by abrasion. Metals that do not readily form oxides may be polished by more abrasive means. Tungsten CMP see Fig. 3.18 has been developed to replace the tungsten etchback step previously used in the formation of W plugs. The polishing of W proceeds by the oxidation of W to form WO 3, which is then removed by mechanical abrasion of the slurry particles and pressure on pad. Typical chemicals used are ferric nitrate, potassium iodate, and hydrogen peroxide. The issue with polishing for W plug formation see Fig. 3.18 are the differing polish rates for the different materials. The TiN/Ti is slower than that of W. This problem is overcome using multi-step processes using different polish modules. Fig. 3.18 Tungsten plug formation using CMP (a) W dep over Ti/TiN barrier layers (b) W and Ti/TiN CMP leaves recessed plugs (c) oxide CMP eliminates recess. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.29

Commercial CMP Tools Modern CMP systems provide fully integrated process capabilities with polishing, endpoint detection, and cleaning included in a single system see Fig. 3.19. Fig. 3.19 Reflexion CMP tool from Applied Materials. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.30

Commercial CMP Tools (contd.) Fig. 3.20 Schematic drawings of rotary and linear polishing systems. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.31

CMP Endpoint Detection Needed to enable the CMP process to stop at the desired point in the process most useful technique is the real-time in situ endpoint detection method using laser interferometry. The laser is aimed at the front side of the wafer and a detector is used to sense the reflected light, which is subsequently sampled and processed using sophisticated DSP. Post CMP Cleaning Directly following CMP, the wafer is contaminated with a combination of residual slurry particles, CMP by-products, metal contaminants and chemicals, and must be cleaned/removed since they can adversely affect the wafer yield. Cleaning typically starts with de-ionized (DI) water which immediately removes majority of the slurry and the wafer is now moved to a brush scrubber where soft poly vinyl alcohol (PVA) brushes are brought into contact with both sides of the wafer. This is followed by a spin rinse drying cycle. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.32

CMP Problems Dishing occurs due to the flexing of the polish pad into a trench, which then forms a concave surface that propagates with the polishing front leaving dished material see Fig. 3.21. Generally greater for larger features Erosion local loss of supporting material surrounding the trench. Generally greater for small-pitch, high density lines. Fig. 3.21 Cu deposition topography before and after CMP. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.33

CMP-induced Defects Defects include metal residues, corrosion, scratches, pinholes, and microcracks. Fig. 3.22 Line corrosion and scratches in Cu CMP. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.34

CMP-induced Defects (contd.) CMP can reveal other defects such as voids, seams, embedded particles, incomplete patterning and other lithographic errors, random thickness variations, etc. Fig. 3.23 Lithographic errors and residual barrier pools. Arokia Nathan E&CE 493 Topic 2/730 Topic 13 Nanoelectronics: Winter 2005 3.35