Si33DS P-Channel -V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) (Ω) I D (A).39 at V GS = -.5 V -.7 -.5 at V GS = -.5 V -..68 at V GS = -.8 V - 3.5 FEATURES Halogen-free According to IEC 69-- Available TrenchFET Power MOSFET APPLICATIONS Load Switch PA Switch TO-36 (SOT-3) G 3 D S Top View Si33DS (D3)* * Marking Code Ordering Information: Si33DS-T Si33DS-T-E3 (Lead (Pb)-free) Si33DS-T-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS T A = 5 C, unless otherwise noted Parameter Symbol 5 s Steady State Unit Drain-Source Voltage V DS - V Gate-Source Voltage V GS ± 8 Continuous Drain Current (T J = 5 C) a, b T A = 5 C -.7-3.7 I D T A = 7 C - 3.8 -.9 A Pulsed Drain Current I DM - Continuous Source Current (Diode Conduction) a, b I S -. -.6 T A = 5 C Maximum Power Dissipation a, b.5.75 P D W T A = 7 C.8.8 Operating Junction and Storage Temperature Range T J, T stg - 55 to 5 C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambient a t 5 s 75 R thja Steady State 66 C/W Maximum Junction-to-Foot (Drain) Steady State R thjf 5 Notes: a. Surface Mounted on " x " FR board. b. Pulse width limited by maximum junction temperature. * Pb containing terminations are not RoHS compliant, exemptions may apply. Document Number: 7 S9-33-Rev. D, -Feb-9
Si33DS Drain-Source On-Resistance a R DS(on) SPECIFICATIONS T J = 5 C, unless otherwise noted Limits Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage V (BR)DSS V GS = V, I D = - 5 µa - Gate-Threshold Voltage V GS(th) V DS = V GS, I D = - 5 µa -. -. V Gate-Body Leakage I GSS V DS = V, V GS = ± 8 V ± na V DS = - 6 V, V GS = V - Zero Gate Voltage Drain Current I DSS V DS = - 6 V, V GS = V, T J = 55 C - µa On-State Drain Current a I D(on) V DS - 5 V, V GS = -.5 V - A V GS = -.5 V, I D = -. A..5 Ω V GS = -.5 V, I D = -.7 A.3.39 V GS = -.8 V, I D = -. A.5.68 Forward Transconductance a g fs V DS = - 5 V, I D = -.7 A 6 S Diode Forward Voltage V SD I S = -. A, V GS = V -.7 -. V Dynamic b Total Gate Charge Q g.5 9 V DS = - V, V GS = -.5 V Gate-Source Charge Q gs.7 I D -.7 A Gate-Drain Charge Q gd 3.3 nc Input Capacitance C iss Output Capacitance C oss V DS = - V, V GS = V, f = MHz 9 pf Reverse Transfer Capacitance C rss Switching c t d(on) 5 Turn-On Time V DD = - V, R L = Ω t r 3 65 I D -. A, V GEN = -.5 V t d(off) 7 Turn-Off Time R G = 6 Ω t f 8 75 ns Notes: a. Pulse test: PW 3 µs, duty cycle %. b. For DESIGN AID ONLY, not subject to production testing. c. Switching time is essentially independent of operating temperature. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 7 S9-33-Rev. D, -Feb-9
Si33DS TYPICAL CHARACTERISTICS 5 C, unless otherwise noted V GS = 5 thru.5 V T C = - 55 C I D - Drain Current (A) 6 8 V.5 V - Drain Current (A) I D 6 8 5 C 5 C V 3 5 V DS - Drain-to-Source Voltage (V) Output Characteristics..5..5..5 V GS - Gate-to-Source Voltage (V) Transfer Characteristics.5 8 - On-Resistance (Ω) R DS(on)..9.6.3 V GS =.8 V V GS =.5 V V GS =.5 V C - Capacitance (pf) 5 9 6 3 C iss C oss. 8 6 I D - Drain Current (A) On-Resistance vs. Drain Current C rss 8 6 V DS - Drain-to-Source Voltage (V) Capacitance 5.5 - Gate-to-Source Voltage (V) V GS 3 V DS = 6 V I D =.7 A - On-Resistance R DS(on) (Normalized)..3....9.8 V GS =.5 V I D =.7 A.7 3 6 9 5 Q g - Total Gate Charge (nc) Gate Charge.6-5 - 5 5 5 75 5 5 T J - Junction Temperature ( C) On-Resistance vs. Junction Temperature Document Number: 7 S9-33-Rev. D, -Feb-9 3
Si33DS TYPICAL CHARACTERISTICS 5 C, unless otherwise noted.5 I S - Source Current (A) T J = 5 C T J = 5 C - On-Resistance (Ω) R DS(on)..9.6.3 I D = A I D =.7 A.....6.8... 3 5 V SD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage V GS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage..3 I D = µa Variance (V) V GS(th)... Power (W) 8 6 T A = 5 C -. -. - 5-5 5 5 75 5 5.. 6 T J - Temperature ( C) Time (s) Threshold Voltage Single Pulse Power Limited by R DS(on)* I DM Limited I D - Drain Current (A). I D(on) Limited T A = 5 C Single Pulse BVDSS Limited.. V DS - Drain-to-Source Voltage (V) *V GS > minimum V GS at which R DS(on) is specified Safe Operating Area P(t) =. P(t) =. P(t) =. P(t) =. P(t) = P(t) = DC Document Number: 7 S9-33-Rev. D, -Feb-9
Si33DS TYPICAL CHARACTERISTICS 5 C, unless otherwise noted Normalized Effective Transient Thermal Impedance Duty Cycle =.5. Notes:. P DM. t.5 t t. Duty Cycle, D =. t. Per Unit Base = R thja = C/W 3. T JM - T A = P DM Z (t) thja. Surface Mounted Single Pulse. - -3 - - 6 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?7. Document Number: 7 S9-33-Rev. D, -Feb-9 5
Package Information SOT-3 (TO-36): 3-LEAD b 3 E E S e e D A A. mm C." Seating Plane C q.5 mm Gauge Plane Seating Plane A C L L Dim MILLIMETERS INCHES Min Max Min Max A.89..35. A.... A.88..36. b.35.5.. c.85.8.3.7 D.8 3... E..6.83. E...7.55 e.95 BSC.37 Ref e.9 BSC.78 Ref L..6.6. L.6 Ref.5 Ref S.5 Ref. Ref q 3 8 3 8 ECN: S-396-Rev. K, 9-Jul- DWG: 579 Document Number: 796 9-Jul-
AN87 Mounting LITTLE FOOT SOT-3 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. ambient air. This pattern uses all the available area underneath the body for this purpose...9 See Application Note 86, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs, (http:///doc?786), for the basis of the pad design for a LITTLE FOOT SOT-3 power MOSFET footprint. In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package..59.5.39..37.95.8.5.5 3.8 FIGURE. Footprint With Copper Spreading The electrical connections for the SOT-3 are very simple. Pin is the gate, pin is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, thermal connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. Figure shows the footprint with copper spreading for the SOT-3 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least. inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device. Document Number: 7739 6-Nov-3
Application Note 86 RECOMMENDED MINIMUM PADS FOR SOT-3.37 (.95). (.559).9 (.7).6 (.69).9 (.5).53 (.3).97 (.59) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 769 Revision: -Jan-8 5
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