Q UA R T U S P R I M E D E S I G N S O F T WA R E
Fastest Path to Your Design Quartus Prime software is number one in performance and productivity for FPGA, CPLD, and SoC designs, providing the fastest path to convert your concept into reality. The Quartus Prime software can easily adapt to your specific needs in all phases of FPGA, CPLD, and SoC design in different platforms. The Quartus Prime software provides everything you need to design with Altera devices. Key features include: Qsys system integration tool BluePrint Platform Designer Physical Synthesis Hybrid Placer PowerPlay Power Analyzer TimeQuest timing analyzer DSP Builder ModelSim -Altera Edition simulation software Altera Edition Quartus Prime Software Key Benefits Industry-Leading Compile Time Accelerated time-to-market Improved Design Productivity Fewer Design Iterations The Quartus Prime software is available in three editions based on your design requirements: Pro, Standard, and Lite Edition. Quartus Prime Pro Editon The Quartus Prime Pro Edition software is optimized to support the advanced features in Altera s next-generation FPGAs and SoCs, starting with the Arria 10 device family. Quartus Prime Standard Edition The Quartus Prime Standard Edition software includes the most extensive support for Altera s latest device families and requires a subscription license. Quartus Prime Lite Edition The Quartus Prime Lite Edition software provides an ideal entry point to Altera s high-volume device families and is available as a free download with no license file required. 2
Qsys Pro System Integration Tool The new Qsys Pro system integration tool in the Pro Edition software retains the powerful functionality of Qsys, but with a new hierarchical framework of Spectra-Q TM engine. This enables the Qsys Pro tool to provide 100X faster response time while opening systems and creating new connections by regenerating or operating on intellectual property (IP) blocks that have changed. The new Qsys Pro tool also supports a variety of design entry methods, such as register transfer level (RTL), block-based design entry, to schematic entry, and black boxes. Hierarchical Framework Standard Interconnects AXI, AHB, APB Avalon Interfaces IP-XACT Design Descriptors Multiple Sources RTL Black Box OpenCL Kernel DSP Builder Subsystem Design Reuse IP Library BluePrint Platform Designer The BluePrint Platform Designer explores a device s peripheral architecture and efficiently assigns interfaces. BluePrint prevents illegal pin assignments by performing fitter and legal checks in real time. This flow eliminates complex error messages and the need to wait for a full compile, thereby speeding up your I/O design by 10X. 3
Physical Synthesis Once the design is placed, the new physical synthesis further optimizes the timing performance of the design. Using fast incremental timing analysis, physical synthesis works on targeted sections of the design and performs various transformations including but not limited to register retiming, combinational re-synthesis, LUT input rotations, and logic duplication to improve the overall timing performance of the design. Physical synthesis also incrementally ensures that the placement of the design remains legal, and enables better flow convergence. Hybrid Placer The Quartus Prime software also includes a new Hybrid Placement feature that uses advanced placement algorithms to speed up overall logic placement. The Hybrid Placer combines analytical and advanced annealing techniques for overall improved quality of results and a reduction in seed noise enabling faster timing closure. PowerPlay Power Analyzer Altera s PowerPlay power analysis technology features Excel-based PowerPlay early power estimators (EPE) and the PowerPlay power analyzer tool in the Quartus Prime software. These power analysis tools give you the ability to estimate power consumption from early design concept through design implementation. Design Entry Constraints Speed Area Power Synthesis Placement and Routing Optimize Power PowerPlay Power Analyzer Power-Optimized Design 4
TimeQuest Timing Analyzer TimeQuest timing analyzer is the second generation, easy-to-use timing analyzer which leverages industrystandard Synopsys Design Constraints (SDC) support to achieve accurate timing, resulting in faster timing closure. DSP Builder DSP Builder generates HDL for digital signal processing (DSP) algorithms in model-based design flow. DSP Builder integrates the algorithm development, simulation, and verification capabilities of MathWorks MATLAB and Simulink system-level design tools with the Altera Quartus Prime design software. You can shorten DSP design cycles by creating the hardware representation of a DSP design in an algorithm-friendly development environment. DSP Builder consists of Standard Blockset and Advanced Blockset. Advanced Blockset is recommended for new designs. Features: Provides superior fixed-point and IEEE 754 single-precision, floating-point DSP implementation with vector processing Offers bit-accurate and cycle-accurate simulation models Performs automatic generation of VHDL test benches Facilitates integration of complex DSP functions Use MATLAB or Simulink to Design Algorithm Add Functions in DSP Builder DSP Libraries Perform Synthesis, Place-and-Route (Quartus Prime Software) Evaluate Hardware in a DSP Development Kit ModelSim-Altera Edition Software The ModelSim-Altera Edition software is a version of the ModelSim software licensed from Mentor Graphics targeted for Altera devices. The software supports Altera gate-level simulation libraries and includes behavioral simulation, HDL testbenches, and Tcl scripting. The ModelSim-Altera Edition software supports dual-language simulation. This includes designs that are written in a combination of Verilog, SystemVerilog, and VHDL languages, also known as mixed HDL. Both the ModelSim-Altera Edition software and ModelSim-Altera Starter Edition software are available for all versions of Quartus Prime software. The ModelSim-Altera Starter Edition software is the same as the ModelSim-Altera Edition software except for the following areas: The ModelSim-Altera Edition software is licensed The ModelSim-Altera Starter Edition software simulation performance is lower than that of ModelSim-Altera Edition, and has a line limit of 10,000 executable lines compared to an unlimited number of lines allowed in the ModelSim-Altera Edition software 5
The Quartus Prime software is number one in performance and productivity for FPGA, CPLD, and SoC designs, providing the fastest path to convert your concept into reality. The Quartus Prime software also supports many third-party tools for synthesis, static timing analysis, board-level simulation, signal integrity analysis, and formal verification. Device Support Design Entry Functional Simulation Notes: 1. The only Arria II FPGA supported is the EP2AGX45 device. 2. Available for Stratix V, Arria V, Cyclone V. 3. Requires an additional license. 4. Available for Arria 10, Stratix V, Arria V, Cyclone V 5. Available with TalkBack feature enabled. Quartus Prime Software Key Features Quartus Prime Software Design Flow Availability Lite Edition (Free) Standard Edition ($) Pro Edition ($) Cyclone, MAX, and Arria II device support 3 1 3 Arria and Stratix device support 3 Arria 10 device support 3 3 Multiprocessor support (faster compile time) 3 3 IP Base Suite Available for purchase 3 3 Qsys 3 3 3 Qsys Pro 3 Rapid Recompile 3 2 3 BluePrint Platform Designer 3 ModelSim-Altera Starter Edition software 3 3 3 ModelSim-Altera Edition software 3 3 3 3 3 3 Synthesis Spectra-Q Synthesis 3 Placement and Routing Timing and Power Verification In-System Debug Operating System (OS) Support Add-On Development Tools Price Fitter (Place and Route) 3 3 Incremental Optimization 3 Spectra-Q Hybrid Placer 3 4 3 Spectra-Q Router 3 4 3 TimeQuest Static Timing Analyzer 3 3 3 PowerPlay Power Analyzer 3 3 3 SignalTap TM II Logic Analyzer 3 5 3 3 Transceiver toolkit 3 3 JNEye link analysis tool 3 3 Windows/Linux 64 bit support 3 3 3 Altera SDK for OpenCL TM 3 3 3 3 3 3 DSP Builder 3 3 3 3 3 3 Nios II Embedded Design Suite 3 3 3 SoC Embedded Design Suite 3 3 3 Free Buy Fixed - $2,995 Float - $3,995 Buy Fixed - $3,995 Float - $4,995 Download Download Now Download Now Download Now 6
Quartus Prime Design Software Features Summary BluePrint Platform Designer Pin planner Platform designer tool that enables you to quickly create your I/O design using real time legality checks. Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs. Design Flow Methodology Qsys or Qsys Pro Off-the-shelf IP cores Automates system development by integrating IP functions and subsystems (collection of IP functions) using a hierarchical approach and a high-performance interconnect based on a network-on-a-chip architecture. Lets you construct your system-level design using IP cores from Altera and from Altera s third-party IP partners. Synthesis Now with expanded language support for System Verilog and VHDL 2008. Scripting support Rapid Recompile Supports command-line operation and Tcl scripting, as well as graphical user interface (GUI) design. Maximizes your productivity by reducing your compilation time up to 4X (for a small design change after a full compile). Improves design timing preservation. Incremental Optimization The incremental optimizations capability in the Quartus Prime Pro Edition software offers a faster methodology to converge to design sign-off. The traditional fitter stage is divided into finer stages for more control over the design flow. Performance and Timing Closure Methodology Physical synthesis Design space explorer (DSE) Extensive cross-probing Optimization advisors Chip planner Uses post placement and routing delay knowledge of a design to improve performance. Increases performance by automatically iterating through combinations of Quartus Prime software settings to find optimal results. Provides support for cross-probing between verification tools and design source files. Provides design-specific advice to improve performance, resource usage, and power consumption. Reduces verification time while maintaining timing closure by enabling small, post placement and routing design changes to be implemented in minutes. TimeQuest timing analyzer Provides native Synopsys Design Constraint (SDC) support and allows you to create, manage, and analyze complex timing constraints and quickly perform advanced timing verification. Verification SignalTap II logic analyzer 1 System Console Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering capabilities available in an embedded logic analyzer. Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to quickly create a GUI to help monitor and send data into your FPGA. PowerPlay technology Enables you to analyze and optimize both dynamic and static power consumption accurately. Third-Party Support EDA partners Offers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-level simulation, signal integrity analysis, and formal verification. To see a complete list of partners, visit www.altera.com/eda-partners. Notes: 1. Available with Talkback feature enabled in Quartus Prime Lite Edition software. Getting Started Steps Step 1: Download the free Quartus Prime Lite Edition software www.altera.com/download Step 2: Get oriented with the Quartus Prime software interactive tutorial After installation, open the interactive tutorial on the welcome screen. Step 3: Sign up for training www.altera.com/training 7
M AIN CORPORATE OFFICES Altera Corporation 101 Innovation Drive San Jose, CA 95134 USA Telephone: (408) 544 7000 www.altera.com Altera European Headquarters Holmers Farm Way High Wycombe Buckinghamshire HP12 4XF United Kingdom Telephone: (44) 1 494 602 000 Altera Japan Ltd. Shinjuku i-land Tower 32F 6-5-1, Nishi Shinjuku Shinjuku-ku, Tokyo 163-1332 Japan Telephone: (81) 3 3340 9480 www.altera.co.jp Altera International Ltd. Unit 11-18, 9/F Millennium City 1, Tower 1 388 Kwun Tong Road Kwun Tong Kowloon, Hong Kong Telephone: (852) 2945 7000 www.altera.com.cn Altera Corporation Technology Center Plot 6, Bayan Lepas Technoplex Medan Bayan Lepas 11900 Bayan Lepas Penang, Malaysia Telephone: 604 636 6100 Altera European Trading Company Ltd. Building 2100 Cork Airport Business Park, Cork, Republic of Ireland Telephone: +353 21 454 7500 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/legal. M 2016 GB-1001-3.4